sim/aarch64/
* simulator.c (do_vec_ADDV): Mov val declaration inside each case,
with type set to input type size.
(do_vec_xtl): Change bias from 3 to 4 for byte case.
sim/testsuite/sim/aarch64/
* bit.s: Change cmp immediates to account for addv bug fix.
* cmtst.s, ldn_single.s, stn_single.s: Likewise.
* xtl.s: New.