8sa1-binutils-gdb/sim/testsuite/sim
Richard Henderson 07f5f4c683 or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.

Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.

The changes also required a few fixups for tests and additional sim helpers.

cpu/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>
	    Stafford Horne  <shorne@gmail.com>

	* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
	(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
	(l-mul): Fix overflow support and indentation.
	(l-mulu): Fix overflow support and indentation.
	(l-muld, l-muldu, l-msbu, l-macu): New instructions.
	(l-div); Remove incorrect carry behavior.
	(l-divu): Fix carry and overflow behavior.
	(l-mac): Add overflow support.
	(l-msb, l-msbu): Add carry and overflow support.

opcodes/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>
	    Stafford Horne  <shorne@gmail.com>

	* or1k-desc.c: Regenerate.
	* or1k-desc.h: Regenerate.
	* or1k-opc.c: Regenerate.
	* or1k-opc.h: Regenerate.
	* or1k-opinst.c: Regenerate.

sim/common/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
	(ADDOFDI): New function, add overflow flag DI variant.
	(SUBCFDI): New function, subtract carry flag DI variant.
	(SUBOFDI): New function, subtract overflow flag DI variant.

sim/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* or1k/cpu.h: Regenerate.
	* or1k/decode.c: Regenerate.
	* or1k/decode.h: Regenerate.
	* or1k/model.c: Regenerate.
	* or1k/sem-switch.c: Regenerate.
	* or1k/sem.c: Regenerate:

sim/testsuite/sim/or1k/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* div.S: Fix tests to match correct overflow/carry semantics.
	* mul.S: Likewise.

gas/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* testsuite/gas/or1k/allinsn.s: Add instruction tests for
	l.muld, l.muldu, l.macu, l.msb, l.msbu.
	* testsuite/gas/or1k/allinsn.d: Add test results for new
	instructions.
2018-10-05 11:41:42 +09:00
..
aarch64 Fix ldn/stn multiple instructions. Fix testcases with unaligned data. 2017-04-22 16:36:01 -07:00
arm
avr
bfin sim: bfin: handle negative left saturated shifts as ashifts [BZ #18407] 2015-10-11 03:42:09 -04:00
cr16 sim: make LMA loading the default for all targets 2015-12-24 21:50:17 -05:00
cris Update copyright year range in all GDB files 2018-01-02 07:38:06 +04:00
fr30
frv
ft32 sim: ft32: test coverage for link parameters and PM write port 2015-10-12 20:23:26 -04:00
h8300
iq2000
lm32
m32c Update copyright year range in all GDB files 2018-01-02 07:38:06 +04:00
m32r
m68hc11
mcore sim: mcore: add a fail testcase 2015-11-15 07:55:48 -05:00
microblaze
mips Update copyright year range in all GDB files 2018-01-02 07:38:06 +04:00
mn10300
moxie
msp430 Fix the execution of the MSP430 simulator testsuite. 2016-01-05 16:43:58 +00:00
or1k or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns 2018-10-05 11:41:42 +09:00
sh
sh64
v850