Dimitar Dimitrov e2e9097bd2 Add testsuite for the PRU simulator port ... sim/testsuite/ChangeLog: * configure: Regenerate. sim/testsuite/sim/pru/ChangeLog: * add.s: New test. * allinsn.exp: New file. * dmem-zero-pass.s: New test. * dmem-zero-trap.s: New test. * dram.s: New test. * jmp.s: New test. * loop-imm.s: New test. * loop-reg.s: New test. * mul.s: New test. * subreg.s: New test. * testutils.inc: New file.		2019-09-23 22:11:16 +01:00
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aarch64	Fix ldn/stn multiple instructions. Fix testcases with unaligned data.	2017-04-22 16:36:01 -07:00
arm
avr
bfin	sim: bfin: handle negative left saturated shifts as ashifts [BZ #18407]	2015-10-11 03:42:09 -04:00
cr16	sim: make LMA loading the default for all targets	2015-12-24 21:50:17 -05:00
cris	Update copyright year range in all GDB files.	2019-01-01 10:01:51 +04:00
fr30
frv
ft32	sim: ft32: test coverage for link parameters and PM write port	2015-10-12 20:23:26 -04:00
h8300
iq2000
lm32
m32c	Update copyright year range in all GDB files.	2019-01-01 10:01:51 +04:00
m32r
m68hc11
mcore	sim: mcore: add a fail testcase	2015-11-15 07:55:48 -05:00
microblaze
mips	Update copyright year range in all GDB files.	2019-01-01 10:01:51 +04:00
mn10300
moxie
msp430	Fix the execution of the MSP430 simulator testsuite.	2016-01-05 16:43:58 +00:00
or1k	sim/testsuite/or1k: Add tests for unordered compares	2019-06-13 21:27:10 +09:00
pru	Add testsuite for the PRU simulator port	2019-09-23 22:11:16 +01:00
sh
sh64
v850