8d3b723419
* sparc-desc.h: New file. * sparc-opc.h: New file. * decode64.c: New file. * decode64.h: New file. * sem64.c: New file. * cpu64.c: New file. * cpu64.h: New file. * model64.h: New file. * mloop64.in: New file. * regs64.h: New file. * trap64.c: New file. * cpu32.h,decode32.c,decode32.h,model32.c,sem32.c: Rebuild.
819 lines
24 KiB
C
819 lines
24 KiB
C
/* CPU family header for sparc64.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1999 Cygnus Solutions, Inc.
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This file is part of the Cygnus Simulators.
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*/
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#ifndef CPU_SPARC64_H
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#define CPU_SPARC64_H
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/* Maximum number of instructions that are fetched at a time.
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This is for LIW type instructions sets (e.g. m32r). */
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#define MAX_LIW_INSNS 1
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/* Maximum number of instructions that can be executed in parallel. */
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#define MAX_PARALLEL_INSNS 1
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/* CPU state information. */
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typedef struct {
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/* Hardware elements. */
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struct {
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/* program counter */
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USI h_pc;
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#define GET_H_PC() CPU (h_pc)
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#define SET_H_PC(x) (CPU (h_pc) = (x))
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/* next pc */
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SI h_npc;
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#define GET_H_NPC() CPU (h_npc)
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#define SET_H_NPC(x) (CPU (h_npc) = (x))
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/* GET_H_GR macro user-written */
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/* SET_H_GR macro user-written */
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/* icc carry bit */
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BI h_icc_c;
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#define GET_H_ICC_C() CPU (h_icc_c)
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#define SET_H_ICC_C(x) (CPU (h_icc_c) = (x))
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/* icc negative bit */
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BI h_icc_n;
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#define GET_H_ICC_N() CPU (h_icc_n)
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#define SET_H_ICC_N(x) (CPU (h_icc_n) = (x))
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/* icc overflow bit */
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BI h_icc_v;
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#define GET_H_ICC_V() CPU (h_icc_v)
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#define SET_H_ICC_V(x) (CPU (h_icc_v) = (x))
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/* icc zero bit */
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BI h_icc_z;
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#define GET_H_ICC_Z() CPU (h_icc_z)
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#define SET_H_ICC_Z(x) (CPU (h_icc_z) = (x))
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/* xcc carry bit */
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BI h_xcc_c;
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#define GET_H_XCC_C() CPU (h_xcc_c)
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#define SET_H_XCC_C(x) (CPU (h_xcc_c) = (x))
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/* xcc negative bit */
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BI h_xcc_n;
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#define GET_H_XCC_N() CPU (h_xcc_n)
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#define SET_H_XCC_N(x) (CPU (h_xcc_n) = (x))
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/* xcc overflow bit */
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BI h_xcc_v;
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#define GET_H_XCC_V() CPU (h_xcc_v)
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#define SET_H_XCC_V(x) (CPU (h_xcc_v) = (x))
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/* xcc zero bit */
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BI h_xcc_z;
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#define GET_H_XCC_Z() CPU (h_xcc_z)
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#define SET_H_XCC_Z(x) (CPU (h_xcc_z) = (x))
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/* GET_H_Y macro user-written */
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/* SET_H_Y macro user-written */
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/* ancilliary state registers */
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SI h_asr[32];
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#define GET_H_ASR(a1) CPU (h_asr)[a1]
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#define SET_H_ASR(a1, x) (CPU (h_asr)[a1] = (x))
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/* annul next insn? - assists execution */
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BI h_annul_p;
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#define GET_H_ANNUL_P() CPU (h_annul_p)
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#define SET_H_ANNUL_P(x) (CPU (h_annul_p) = (x))
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/* floating point regs */
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SF h_fr[32];
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#define GET_H_FR(a1) CPU (h_fr)[a1]
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#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
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/* version */
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UDI h_ver;
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#define GET_H_VER() CPU (h_ver)
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#define SET_H_VER(x) (CPU (h_ver) = (x))
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/* processor state */
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UDI h_pstate;
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#define GET_H_PSTATE() CPU (h_pstate)
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#define SET_H_PSTATE(x) (CPU (h_pstate) = (x))
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/* trap base address */
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UDI h_tba;
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#define GET_H_TBA() CPU (h_tba)
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#define SET_H_TBA(x) (CPU (h_tba) = (x))
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/* trap type */
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UDI h_tt;
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#define GET_H_TT() CPU (h_tt)
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#define SET_H_TT(x) (CPU (h_tt) = (x))
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/* trap pc */
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UDI h_tpc;
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#define GET_H_TPC() CPU (h_tpc)
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#define SET_H_TPC(x) (CPU (h_tpc) = (x))
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/* trap npc */
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UDI h_tnpc;
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#define GET_H_TNPC() CPU (h_tnpc)
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#define SET_H_TNPC(x) (CPU (h_tnpc) = (x))
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/* trap state */
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UDI h_tstate;
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#define GET_H_TSTATE() CPU (h_tstate)
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#define SET_H_TSTATE(x) (CPU (h_tstate) = (x))
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/* trap level */
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UQI h_tl;
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#define GET_H_TL() CPU (h_tl)
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#define SET_H_TL(x) (CPU (h_tl) = (x))
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/* address space identifier */
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UQI h_asi;
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#define GET_H_ASI() CPU (h_asi)
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#define SET_H_ASI(x) (CPU (h_asi) = (x))
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/* tick counter */
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UDI h_tick;
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#define GET_H_TICK() CPU (h_tick)
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#define SET_H_TICK(x) (CPU (h_tick) = (x))
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/* savable window registers */
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UDI h_cansave;
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#define GET_H_CANSAVE() CPU (h_cansave)
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#define SET_H_CANSAVE(x) (CPU (h_cansave) = (x))
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/* restorable window registers */
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UDI h_canrestore;
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#define GET_H_CANRESTORE() CPU (h_canrestore)
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#define SET_H_CANRESTORE(x) (CPU (h_canrestore) = (x))
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/* other window registers */
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UDI h_otherwin;
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#define GET_H_OTHERWIN() CPU (h_otherwin)
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#define SET_H_OTHERWIN(x) (CPU (h_otherwin) = (x))
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/* clean window registers */
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UDI h_cleanwin;
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#define GET_H_CLEANWIN() CPU (h_cleanwin)
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#define SET_H_CLEANWIN(x) (CPU (h_cleanwin) = (x))
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/* window state */
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UDI h_wstate;
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#define GET_H_WSTATE() CPU (h_wstate)
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#define SET_H_WSTATE(x) (CPU (h_wstate) = (x))
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/* */
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UQI h_fcc0;
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#define GET_H_FCC0() CPU (h_fcc0)
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#define SET_H_FCC0(x) (CPU (h_fcc0) = (x))
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/* */
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UQI h_fcc1;
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#define GET_H_FCC1() CPU (h_fcc1)
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#define SET_H_FCC1(x) (CPU (h_fcc1) = (x))
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/* */
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UQI h_fcc2;
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#define GET_H_FCC2() CPU (h_fcc2)
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#define SET_H_FCC2(x) (CPU (h_fcc2) = (x))
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/* */
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UQI h_fcc3;
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#define GET_H_FCC3() CPU (h_fcc3)
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#define SET_H_FCC3(x) (CPU (h_fcc3) = (x))
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/* fsr rounding direction */
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UQI h_fsr_rd;
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#define GET_H_FSR_RD() CPU (h_fsr_rd)
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#define SET_H_FSR_RD(x) (CPU (h_fsr_rd) = (x))
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/* fsr trap enable mask */
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UQI h_fsr_tem;
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#define GET_H_FSR_TEM() CPU (h_fsr_tem)
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#define SET_H_FSR_TEM(x) (CPU (h_fsr_tem) = (x))
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/* fsr nonstandard fp */
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BI h_fsr_ns;
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#define GET_H_FSR_NS() CPU (h_fsr_ns)
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#define SET_H_FSR_NS(x) (CPU (h_fsr_ns) = (x))
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/* fsr version */
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UQI h_fsr_ver;
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#define GET_H_FSR_VER() CPU (h_fsr_ver)
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#define SET_H_FSR_VER(x) (CPU (h_fsr_ver) = (x))
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/* fsr fp trap type */
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UQI h_fsr_ftt;
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#define GET_H_FSR_FTT() CPU (h_fsr_ftt)
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#define SET_H_FSR_FTT(x) (CPU (h_fsr_ftt) = (x))
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/* fsr queue not empty */
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BI h_fsr_qne;
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#define GET_H_FSR_QNE() CPU (h_fsr_qne)
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#define SET_H_FSR_QNE(x) (CPU (h_fsr_qne) = (x))
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/* fsr accrued exception */
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UQI h_fsr_aexc;
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#define GET_H_FSR_AEXC() CPU (h_fsr_aexc)
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#define SET_H_FSR_AEXC(x) (CPU (h_fsr_aexc) = (x))
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/* fsr current exception */
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UQI h_fsr_cexc;
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#define GET_H_FSR_CEXC() CPU (h_fsr_cexc)
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#define SET_H_FSR_CEXC(x) (CPU (h_fsr_cexc) = (x))
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/* fpsr enable fp */
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BI h_fpsr_fef;
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#define GET_H_FPSR_FEF() CPU (h_fpsr_fef)
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#define SET_H_FPSR_FEF(x) (CPU (h_fpsr_fef) = (x))
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/* fpsr dirty upper */
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BI h_fpsr_du;
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#define GET_H_FPSR_DU() CPU (h_fpsr_du)
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#define SET_H_FPSR_DU(x) (CPU (h_fpsr_du) = (x))
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/* fpsr dirty lower */
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BI h_fpsr_dl;
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#define GET_H_FPSR_DL() CPU (h_fpsr_dl)
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#define SET_H_FPSR_DL(x) (CPU (h_fpsr_dl) = (x))
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/* GET_H_FPSR macro user-written */
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/* SET_H_FPSR macro user-written */
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} hardware;
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#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
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} SPARC64_CPU_DATA;
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/* Cover fns for register access. */
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USI sparc64_h_pc_get (SIM_CPU *);
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void sparc64_h_pc_set (SIM_CPU *, USI);
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SI sparc64_h_npc_get (SIM_CPU *);
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void sparc64_h_npc_set (SIM_CPU *, SI);
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SI sparc64_h_gr_get (SIM_CPU *, UINT);
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void sparc64_h_gr_set (SIM_CPU *, UINT, SI);
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BI sparc64_h_icc_c_get (SIM_CPU *);
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void sparc64_h_icc_c_set (SIM_CPU *, BI);
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BI sparc64_h_icc_n_get (SIM_CPU *);
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void sparc64_h_icc_n_set (SIM_CPU *, BI);
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BI sparc64_h_icc_v_get (SIM_CPU *);
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void sparc64_h_icc_v_set (SIM_CPU *, BI);
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BI sparc64_h_icc_z_get (SIM_CPU *);
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void sparc64_h_icc_z_set (SIM_CPU *, BI);
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BI sparc64_h_xcc_c_get (SIM_CPU *);
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void sparc64_h_xcc_c_set (SIM_CPU *, BI);
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BI sparc64_h_xcc_n_get (SIM_CPU *);
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void sparc64_h_xcc_n_set (SIM_CPU *, BI);
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BI sparc64_h_xcc_v_get (SIM_CPU *);
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void sparc64_h_xcc_v_set (SIM_CPU *, BI);
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BI sparc64_h_xcc_z_get (SIM_CPU *);
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void sparc64_h_xcc_z_set (SIM_CPU *, BI);
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SI sparc64_h_y_get (SIM_CPU *);
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void sparc64_h_y_set (SIM_CPU *, SI);
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SI sparc64_h_asr_get (SIM_CPU *, UINT);
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void sparc64_h_asr_set (SIM_CPU *, UINT, SI);
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BI sparc64_h_annul_p_get (SIM_CPU *);
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void sparc64_h_annul_p_set (SIM_CPU *, BI);
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SF sparc64_h_fr_get (SIM_CPU *, UINT);
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void sparc64_h_fr_set (SIM_CPU *, UINT, SF);
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UDI sparc64_h_ver_get (SIM_CPU *);
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void sparc64_h_ver_set (SIM_CPU *, UDI);
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UDI sparc64_h_pstate_get (SIM_CPU *);
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void sparc64_h_pstate_set (SIM_CPU *, UDI);
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UDI sparc64_h_tba_get (SIM_CPU *);
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void sparc64_h_tba_set (SIM_CPU *, UDI);
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UDI sparc64_h_tt_get (SIM_CPU *);
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void sparc64_h_tt_set (SIM_CPU *, UDI);
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UDI sparc64_h_tpc_get (SIM_CPU *);
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void sparc64_h_tpc_set (SIM_CPU *, UDI);
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UDI sparc64_h_tnpc_get (SIM_CPU *);
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void sparc64_h_tnpc_set (SIM_CPU *, UDI);
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UDI sparc64_h_tstate_get (SIM_CPU *);
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void sparc64_h_tstate_set (SIM_CPU *, UDI);
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UQI sparc64_h_tl_get (SIM_CPU *);
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void sparc64_h_tl_set (SIM_CPU *, UQI);
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UQI sparc64_h_asi_get (SIM_CPU *);
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void sparc64_h_asi_set (SIM_CPU *, UQI);
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UDI sparc64_h_tick_get (SIM_CPU *);
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void sparc64_h_tick_set (SIM_CPU *, UDI);
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UDI sparc64_h_cansave_get (SIM_CPU *);
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void sparc64_h_cansave_set (SIM_CPU *, UDI);
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UDI sparc64_h_canrestore_get (SIM_CPU *);
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void sparc64_h_canrestore_set (SIM_CPU *, UDI);
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UDI sparc64_h_otherwin_get (SIM_CPU *);
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void sparc64_h_otherwin_set (SIM_CPU *, UDI);
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UDI sparc64_h_cleanwin_get (SIM_CPU *);
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void sparc64_h_cleanwin_set (SIM_CPU *, UDI);
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UDI sparc64_h_wstate_get (SIM_CPU *);
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void sparc64_h_wstate_set (SIM_CPU *, UDI);
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UQI sparc64_h_fcc0_get (SIM_CPU *);
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void sparc64_h_fcc0_set (SIM_CPU *, UQI);
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UQI sparc64_h_fcc1_get (SIM_CPU *);
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void sparc64_h_fcc1_set (SIM_CPU *, UQI);
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UQI sparc64_h_fcc2_get (SIM_CPU *);
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void sparc64_h_fcc2_set (SIM_CPU *, UQI);
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UQI sparc64_h_fcc3_get (SIM_CPU *);
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void sparc64_h_fcc3_set (SIM_CPU *, UQI);
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UQI sparc64_h_fsr_rd_get (SIM_CPU *);
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void sparc64_h_fsr_rd_set (SIM_CPU *, UQI);
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UQI sparc64_h_fsr_tem_get (SIM_CPU *);
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void sparc64_h_fsr_tem_set (SIM_CPU *, UQI);
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BI sparc64_h_fsr_ns_get (SIM_CPU *);
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void sparc64_h_fsr_ns_set (SIM_CPU *, BI);
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UQI sparc64_h_fsr_ver_get (SIM_CPU *);
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void sparc64_h_fsr_ver_set (SIM_CPU *, UQI);
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UQI sparc64_h_fsr_ftt_get (SIM_CPU *);
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void sparc64_h_fsr_ftt_set (SIM_CPU *, UQI);
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BI sparc64_h_fsr_qne_get (SIM_CPU *);
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void sparc64_h_fsr_qne_set (SIM_CPU *, BI);
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UQI sparc64_h_fsr_aexc_get (SIM_CPU *);
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void sparc64_h_fsr_aexc_set (SIM_CPU *, UQI);
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UQI sparc64_h_fsr_cexc_get (SIM_CPU *);
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void sparc64_h_fsr_cexc_set (SIM_CPU *, UQI);
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BI sparc64_h_fpsr_fef_get (SIM_CPU *);
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void sparc64_h_fpsr_fef_set (SIM_CPU *, BI);
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BI sparc64_h_fpsr_du_get (SIM_CPU *);
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void sparc64_h_fpsr_du_set (SIM_CPU *, BI);
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BI sparc64_h_fpsr_dl_get (SIM_CPU *);
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void sparc64_h_fpsr_dl_set (SIM_CPU *, BI);
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UQI sparc64_h_fpsr_get (SIM_CPU *);
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void sparc64_h_fpsr_set (SIM_CPU *, UQI);
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/* These must be hand-written. */
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extern CPUREG_FETCH_FN sparc64_fetch_register;
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extern CPUREG_STORE_FN sparc64_store_register;
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typedef struct {
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int empty;
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} MODEL_SPARC64_DEF_DATA;
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/* The ARGBUF struct. */
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struct argbuf {
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/* These are the baseclass definitions. */
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IADDR addr;
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const IDESC *idesc;
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char trace_p;
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char profile_p;
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/* cpu specific data follows */
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CGEN_INSN_INT insn;
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int written;
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};
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/* A cached insn.
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??? SCACHE used to contain more than just argbuf. We could delete the
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type entirely and always just use ARGBUF, but for future concerns and as
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a level of abstraction it is left in. */
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struct scache {
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struct argbuf argbuf;
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};
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/* Macros to simplify extraction, reading and semantic code.
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These define and assign the local vars that contain the insn's fields. */
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#define EXTRACT_IFMT_EMPTY_VARS \
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/* Instruction fields. */ \
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unsigned int length;
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#define EXTRACT_IFMT_EMPTY_CODE \
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length = 0; \
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#define EXTRACT_IFMT_BEQZ_VARS \
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/* Instruction fields. */ \
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INT f_disp16; \
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UINT f_disp16_hi; \
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UINT f_disp16_lo; \
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UINT f_rs1; \
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UINT f_p; \
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UINT f_op2; \
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UINT f_fmt2_rcond; \
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INT f_bpr_res28_1; \
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UINT f_a; \
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UINT f_op; \
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unsigned int length;
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#define EXTRACT_IFMT_BEQZ_CODE \
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length = 4; \
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f_disp16_hi = EXTRACT_UINT (insn, 32, 10, 2); \
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f_disp16_lo = EXTRACT_UINT (insn, 32, 18, 14); \
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do {\
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f_disp16 = ((((f_disp16_hi) << (14))) | (f_disp16_low));\
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} while (0);\
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f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
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f_p = EXTRACT_UINT (insn, 32, 19, 1); \
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f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
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f_fmt2_rcond = EXTRACT_UINT (insn, 32, 27, 3); \
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f_bpr_res28_1 = EXTRACT_INT (insn, 32, 28, 1); \
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f_a = EXTRACT_UINT (insn, 32, 29, 1); \
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f_op = EXTRACT_UINT (insn, 32, 31, 2); \
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#define EXTRACT_IFMT_BPCC_BA_VARS \
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/* Instruction fields. */ \
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INT f_disp19; \
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UINT f_p; \
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UINT f_fmt2_cc0; \
|
|
UINT f_fmt2_cc1; \
|
|
UINT f_op2; \
|
|
UINT f_fmt2_cond; \
|
|
UINT f_a; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_BPCC_BA_CODE \
|
|
length = 4; \
|
|
f_disp19 = EXTRACT_INT (insn, 32, 13, 19); \
|
|
f_p = EXTRACT_UINT (insn, 32, 19, 1); \
|
|
f_fmt2_cc0 = EXTRACT_UINT (insn, 32, 20, 1); \
|
|
f_fmt2_cc1 = EXTRACT_UINT (insn, 32, 21, 1); \
|
|
f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
|
|
f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
|
|
f_a = EXTRACT_UINT (insn, 32, 29, 1); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_DONE_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_res_18_19; \
|
|
UINT f_op3; \
|
|
UINT f_fcn; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_DONE_CODE \
|
|
length = 4; \
|
|
f_res_18_19 = EXTRACT_INT (insn, 32, 18, 19); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_fcn = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_FLUSH_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
INT f_res_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_FLUSH_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_FLUSH_IMM_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_simm13; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_FLUSH_IMM_CODE \
|
|
length = 4; \
|
|
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_FLUSHW_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_simm13; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_FLUSHW_CODE \
|
|
length = 4; \
|
|
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_IMPDEP1_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_impdep19; \
|
|
UINT f_op3; \
|
|
INT f_impdep5; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_IMPDEP1_CODE \
|
|
length = 4; \
|
|
f_impdep19 = EXTRACT_INT (insn, 32, 18, 19); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_impdep5 = EXTRACT_INT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_MEMBAR_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_membarmask; \
|
|
INT f_membar_res12_6; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_MEMBAR_CODE \
|
|
length = 4; \
|
|
f_membarmask = EXTRACT_UINT (insn, 32, 6, 7); \
|
|
f_membar_res12_6 = EXTRACT_INT (insn, 32, 12, 6); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_MOVA_ICC_ICC_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
INT f_fmt4_res10_6; \
|
|
UINT f_fmt4_cc1_0; \
|
|
UINT f_i; \
|
|
UINT f_fmt4_cc2; \
|
|
UINT f_op3; \
|
|
UINT f_fmt2_cond; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_MOVA_ICC_ICC_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_fmt4_res10_6 = EXTRACT_INT (insn, 32, 10, 6); \
|
|
f_fmt4_cc1_0 = EXTRACT_UINT (insn, 32, 12, 2); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_fmt4_cc2 = EXTRACT_UINT (insn, 32, 18, 1); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_simm11; \
|
|
UINT f_fmt4_cc1_0; \
|
|
UINT f_i; \
|
|
UINT f_fmt4_cc2; \
|
|
UINT f_op3; \
|
|
UINT f_fmt2_cond; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE \
|
|
length = 4; \
|
|
f_simm11 = EXTRACT_INT (insn, 32, 10, 11); \
|
|
f_fmt4_cc1_0 = EXTRACT_UINT (insn, 32, 12, 2); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_fmt4_cc2 = EXTRACT_UINT (insn, 32, 18, 1); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_LDSB_REG_REG_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
INT f_res_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LDSB_REG_REG_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_LDSB_REG_IMM_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_simm13; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LDSB_REG_IMM_CODE \
|
|
length = 4; \
|
|
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
UINT f_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_LDD_REG_REG_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
INT f_res_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LDD_REG_REG_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_LDD_REG_IMM_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_simm13; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LDD_REG_IMM_CODE \
|
|
length = 4; \
|
|
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_LDD_REG_REG_ASI_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
UINT f_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LDD_REG_REG_ASI_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_FP_LD_REG_REG_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
INT f_res_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_FP_LD_REG_REG_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_FP_LD_REG_IMM_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_simm13; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_FP_LD_REG_IMM_CODE \
|
|
length = 4; \
|
|
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
UINT f_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_SETHI_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_hi22; \
|
|
UINT f_op2; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_SETHI_CODE \
|
|
length = 4; \
|
|
f_hi22 = EXTRACT_INT (insn, 32, 21, 22); \
|
|
f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_UNIMP_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_imm22; \
|
|
UINT f_op2; \
|
|
UINT f_rd_res; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_UNIMP_CODE \
|
|
length = 4; \
|
|
f_imm22 = EXTRACT_INT (insn, 32, 21, 22); \
|
|
f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
|
|
f_rd_res = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_CALL_VARS \
|
|
/* Instruction fields. */ \
|
|
SI f_disp30; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_CALL_CODE \
|
|
length = 4; \
|
|
f_disp30 = ((((EXTRACT_INT (insn, 32, 29, 30)) << (2))) + (pc)); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_BA_VARS \
|
|
/* Instruction fields. */ \
|
|
SI f_disp22; \
|
|
UINT f_op2; \
|
|
UINT f_fmt2_cond; \
|
|
UINT f_a; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_BA_CODE \
|
|
length = 4; \
|
|
f_disp22 = ((((EXTRACT_INT (insn, 32, 21, 22)) << (2))) + (pc)); \
|
|
f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
|
|
f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
|
|
f_a = EXTRACT_UINT (insn, 32, 29, 1); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_TA_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
INT f_res_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_fmt2_cond; \
|
|
UINT f_a; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_TA_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
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f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
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f_i = EXTRACT_UINT (insn, 32, 13, 1); \
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f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
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f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
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f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
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f_a = EXTRACT_UINT (insn, 32, 29, 1); \
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f_op = EXTRACT_UINT (insn, 32, 31, 2); \
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|
|
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#define EXTRACT_IFMT_TA_IMM_VARS \
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/* Instruction fields. */ \
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|
INT f_simm13; \
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|
UINT f_i; \
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UINT f_rs1; \
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|
UINT f_op3; \
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|
UINT f_fmt2_cond; \
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|
UINT f_a; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_TA_IMM_CODE \
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|
length = 4; \
|
|
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
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|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
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|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
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|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
|
|
f_a = EXTRACT_UINT (insn, 32, 29, 1); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
/* Collection of various things for the trace handler to use. */
|
|
|
|
typedef struct trace_record {
|
|
IADDR pc;
|
|
/* FIXME:wip */
|
|
} TRACE_RECORD;
|
|
|
|
#endif /* CPU_SPARC64_H */
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