8d3b723419
* sparc-desc.h: New file. * sparc-opc.h: New file. * decode64.c: New file. * decode64.h: New file. * sem64.c: New file. * cpu64.c: New file. * cpu64.h: New file. * model64.h: New file. * mloop64.in: New file. * regs64.h: New file. * trap64.c: New file. * cpu32.h,decode32.c,decode32.h,model32.c,sem32.c: Rebuild.
760 lines
11 KiB
C
760 lines
11 KiB
C
/* Misc. support for CPU family sparc64.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1999 Cygnus Solutions, Inc.
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This file is part of the Cygnus Simulators.
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*/
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#define WANT_CPU sparc64
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#define WANT_CPU_SPARC64
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#include "sim-main.h"
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/* Get the value of h-pc. */
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USI
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sparc64_h_pc_get (SIM_CPU *current_cpu)
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{
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return CPU (h_pc);
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}
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/* Set a value for h-pc. */
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void
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sparc64_h_pc_set (SIM_CPU *current_cpu, USI newval)
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{
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CPU (h_pc) = newval;
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}
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/* Get the value of h-npc. */
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SI
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sparc64_h_npc_get (SIM_CPU *current_cpu)
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{
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return CPU (h_npc);
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}
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/* Set a value for h-npc. */
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void
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sparc64_h_npc_set (SIM_CPU *current_cpu, SI newval)
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{
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CPU (h_npc) = newval;
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}
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/* Get the value of h-gr. */
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SI
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sparc64_h_gr_get (SIM_CPU *current_cpu, UINT regno)
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{
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return GET_H_GR (regno);
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}
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/* Set a value for h-gr. */
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void
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sparc64_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
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{
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SET_H_GR (regno, newval);
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}
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/* Get the value of h-icc-c. */
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BI
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sparc64_h_icc_c_get (SIM_CPU *current_cpu)
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{
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return CPU (h_icc_c);
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}
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/* Set a value for h-icc-c. */
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void
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sparc64_h_icc_c_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_icc_c) = newval;
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}
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/* Get the value of h-icc-n. */
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BI
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sparc64_h_icc_n_get (SIM_CPU *current_cpu)
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{
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return CPU (h_icc_n);
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}
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/* Set a value for h-icc-n. */
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void
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sparc64_h_icc_n_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_icc_n) = newval;
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}
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/* Get the value of h-icc-v. */
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BI
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sparc64_h_icc_v_get (SIM_CPU *current_cpu)
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{
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return CPU (h_icc_v);
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}
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/* Set a value for h-icc-v. */
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void
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sparc64_h_icc_v_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_icc_v) = newval;
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}
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/* Get the value of h-icc-z. */
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BI
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sparc64_h_icc_z_get (SIM_CPU *current_cpu)
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{
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return CPU (h_icc_z);
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}
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/* Set a value for h-icc-z. */
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void
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sparc64_h_icc_z_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_icc_z) = newval;
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}
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/* Get the value of h-xcc-c. */
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BI
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sparc64_h_xcc_c_get (SIM_CPU *current_cpu)
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{
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return CPU (h_xcc_c);
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}
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/* Set a value for h-xcc-c. */
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void
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sparc64_h_xcc_c_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_xcc_c) = newval;
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}
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/* Get the value of h-xcc-n. */
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BI
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sparc64_h_xcc_n_get (SIM_CPU *current_cpu)
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{
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return CPU (h_xcc_n);
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}
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/* Set a value for h-xcc-n. */
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void
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sparc64_h_xcc_n_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_xcc_n) = newval;
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}
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/* Get the value of h-xcc-v. */
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BI
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sparc64_h_xcc_v_get (SIM_CPU *current_cpu)
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{
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return CPU (h_xcc_v);
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}
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/* Set a value for h-xcc-v. */
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void
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sparc64_h_xcc_v_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_xcc_v) = newval;
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}
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/* Get the value of h-xcc-z. */
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BI
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sparc64_h_xcc_z_get (SIM_CPU *current_cpu)
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{
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return CPU (h_xcc_z);
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}
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/* Set a value for h-xcc-z. */
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void
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sparc64_h_xcc_z_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_xcc_z) = newval;
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}
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/* Get the value of h-y. */
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SI
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sparc64_h_y_get (SIM_CPU *current_cpu)
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{
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return GET_H_Y ();
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}
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/* Set a value for h-y. */
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void
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sparc64_h_y_set (SIM_CPU *current_cpu, SI newval)
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{
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SET_H_Y (newval);
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}
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/* Get the value of h-asr. */
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SI
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sparc64_h_asr_get (SIM_CPU *current_cpu, UINT regno)
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{
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return CPU (h_asr[regno]);
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}
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/* Set a value for h-asr. */
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void
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sparc64_h_asr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
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{
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CPU (h_asr[regno]) = newval;
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}
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/* Get the value of h-annul-p. */
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BI
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sparc64_h_annul_p_get (SIM_CPU *current_cpu)
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{
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return CPU (h_annul_p);
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}
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/* Set a value for h-annul-p. */
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void
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sparc64_h_annul_p_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_annul_p) = newval;
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}
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/* Get the value of h-fr. */
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SF
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sparc64_h_fr_get (SIM_CPU *current_cpu, UINT regno)
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{
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return CPU (h_fr[regno]);
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}
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/* Set a value for h-fr. */
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void
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sparc64_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
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{
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CPU (h_fr[regno]) = newval;
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}
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/* Get the value of h-ver. */
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UDI
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sparc64_h_ver_get (SIM_CPU *current_cpu)
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{
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return CPU (h_ver);
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}
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/* Set a value for h-ver. */
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void
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sparc64_h_ver_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_ver) = newval;
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}
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/* Get the value of h-pstate. */
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UDI
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sparc64_h_pstate_get (SIM_CPU *current_cpu)
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{
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return CPU (h_pstate);
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}
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/* Set a value for h-pstate. */
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void
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sparc64_h_pstate_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_pstate) = newval;
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}
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/* Get the value of h-tba. */
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UDI
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sparc64_h_tba_get (SIM_CPU *current_cpu)
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{
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return CPU (h_tba);
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}
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/* Set a value for h-tba. */
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void
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sparc64_h_tba_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_tba) = newval;
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}
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/* Get the value of h-tt. */
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UDI
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sparc64_h_tt_get (SIM_CPU *current_cpu)
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{
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return CPU (h_tt);
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}
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/* Set a value for h-tt. */
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void
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sparc64_h_tt_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_tt) = newval;
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}
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/* Get the value of h-tpc. */
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UDI
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sparc64_h_tpc_get (SIM_CPU *current_cpu)
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{
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return CPU (h_tpc);
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}
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/* Set a value for h-tpc. */
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void
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sparc64_h_tpc_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_tpc) = newval;
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}
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/* Get the value of h-tnpc. */
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UDI
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sparc64_h_tnpc_get (SIM_CPU *current_cpu)
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{
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return CPU (h_tnpc);
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}
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/* Set a value for h-tnpc. */
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void
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sparc64_h_tnpc_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_tnpc) = newval;
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}
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/* Get the value of h-tstate. */
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UDI
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sparc64_h_tstate_get (SIM_CPU *current_cpu)
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{
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return CPU (h_tstate);
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}
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/* Set a value for h-tstate. */
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void
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sparc64_h_tstate_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_tstate) = newval;
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}
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/* Get the value of h-tl. */
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UQI
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sparc64_h_tl_get (SIM_CPU *current_cpu)
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{
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return CPU (h_tl);
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}
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/* Set a value for h-tl. */
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void
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sparc64_h_tl_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_tl) = newval;
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}
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/* Get the value of h-asi. */
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UQI
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sparc64_h_asi_get (SIM_CPU *current_cpu)
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{
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return CPU (h_asi);
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}
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/* Set a value for h-asi. */
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void
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sparc64_h_asi_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_asi) = newval;
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}
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/* Get the value of h-tick. */
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UDI
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sparc64_h_tick_get (SIM_CPU *current_cpu)
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{
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return CPU (h_tick);
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}
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/* Set a value for h-tick. */
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void
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sparc64_h_tick_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_tick) = newval;
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}
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/* Get the value of h-cansave. */
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UDI
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sparc64_h_cansave_get (SIM_CPU *current_cpu)
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{
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return CPU (h_cansave);
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}
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/* Set a value for h-cansave. */
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void
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sparc64_h_cansave_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_cansave) = newval;
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}
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/* Get the value of h-canrestore. */
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UDI
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sparc64_h_canrestore_get (SIM_CPU *current_cpu)
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{
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return CPU (h_canrestore);
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}
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/* Set a value for h-canrestore. */
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void
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sparc64_h_canrestore_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_canrestore) = newval;
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}
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/* Get the value of h-otherwin. */
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UDI
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sparc64_h_otherwin_get (SIM_CPU *current_cpu)
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{
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return CPU (h_otherwin);
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}
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/* Set a value for h-otherwin. */
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void
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sparc64_h_otherwin_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_otherwin) = newval;
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}
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/* Get the value of h-cleanwin. */
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UDI
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sparc64_h_cleanwin_get (SIM_CPU *current_cpu)
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{
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return CPU (h_cleanwin);
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}
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/* Set a value for h-cleanwin. */
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void
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sparc64_h_cleanwin_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_cleanwin) = newval;
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}
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/* Get the value of h-wstate. */
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UDI
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sparc64_h_wstate_get (SIM_CPU *current_cpu)
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{
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return CPU (h_wstate);
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}
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/* Set a value for h-wstate. */
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void
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sparc64_h_wstate_set (SIM_CPU *current_cpu, UDI newval)
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{
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CPU (h_wstate) = newval;
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}
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/* Get the value of h-fcc0. */
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UQI
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sparc64_h_fcc0_get (SIM_CPU *current_cpu)
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{
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return CPU (h_fcc0);
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}
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/* Set a value for h-fcc0. */
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void
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sparc64_h_fcc0_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_fcc0) = newval;
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}
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/* Get the value of h-fcc1. */
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UQI
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sparc64_h_fcc1_get (SIM_CPU *current_cpu)
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{
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return CPU (h_fcc1);
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}
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/* Set a value for h-fcc1. */
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void
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sparc64_h_fcc1_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_fcc1) = newval;
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}
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/* Get the value of h-fcc2. */
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UQI
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sparc64_h_fcc2_get (SIM_CPU *current_cpu)
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{
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return CPU (h_fcc2);
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}
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/* Set a value for h-fcc2. */
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void
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sparc64_h_fcc2_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_fcc2) = newval;
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}
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/* Get the value of h-fcc3. */
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UQI
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sparc64_h_fcc3_get (SIM_CPU *current_cpu)
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{
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return CPU (h_fcc3);
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}
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/* Set a value for h-fcc3. */
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void
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sparc64_h_fcc3_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_fcc3) = newval;
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}
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/* Get the value of h-fsr-rd. */
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UQI
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sparc64_h_fsr_rd_get (SIM_CPU *current_cpu)
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{
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return CPU (h_fsr_rd);
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}
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/* Set a value for h-fsr-rd. */
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void
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sparc64_h_fsr_rd_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_fsr_rd) = newval;
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}
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/* Get the value of h-fsr-tem. */
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UQI
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sparc64_h_fsr_tem_get (SIM_CPU *current_cpu)
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{
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return CPU (h_fsr_tem);
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}
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/* Set a value for h-fsr-tem. */
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void
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sparc64_h_fsr_tem_set (SIM_CPU *current_cpu, UQI newval)
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{
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CPU (h_fsr_tem) = newval;
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}
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/* Get the value of h-fsr-ns. */
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BI
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sparc64_h_fsr_ns_get (SIM_CPU *current_cpu)
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{
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return CPU (h_fsr_ns);
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}
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/* Set a value for h-fsr-ns. */
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void
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sparc64_h_fsr_ns_set (SIM_CPU *current_cpu, BI newval)
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{
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CPU (h_fsr_ns) = newval;
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}
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|
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/* Get the value of h-fsr-ver. */
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|
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UQI
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sparc64_h_fsr_ver_get (SIM_CPU *current_cpu)
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|
{
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|
return CPU (h_fsr_ver);
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}
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|
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/* Set a value for h-fsr-ver. */
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|
|
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void
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sparc64_h_fsr_ver_set (SIM_CPU *current_cpu, UQI newval)
|
|
{
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|
CPU (h_fsr_ver) = newval;
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}
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|
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/* Get the value of h-fsr-ftt. */
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|
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UQI
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sparc64_h_fsr_ftt_get (SIM_CPU *current_cpu)
|
|
{
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|
return CPU (h_fsr_ftt);
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}
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|
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/* Set a value for h-fsr-ftt. */
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|
|
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void
|
|
sparc64_h_fsr_ftt_set (SIM_CPU *current_cpu, UQI newval)
|
|
{
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|
CPU (h_fsr_ftt) = newval;
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|
}
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|
|
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/* Get the value of h-fsr-qne. */
|
|
|
|
BI
|
|
sparc64_h_fsr_qne_get (SIM_CPU *current_cpu)
|
|
{
|
|
return CPU (h_fsr_qne);
|
|
}
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|
|
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/* Set a value for h-fsr-qne. */
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|
|
|
void
|
|
sparc64_h_fsr_qne_set (SIM_CPU *current_cpu, BI newval)
|
|
{
|
|
CPU (h_fsr_qne) = newval;
|
|
}
|
|
|
|
/* Get the value of h-fsr-aexc. */
|
|
|
|
UQI
|
|
sparc64_h_fsr_aexc_get (SIM_CPU *current_cpu)
|
|
{
|
|
return CPU (h_fsr_aexc);
|
|
}
|
|
|
|
/* Set a value for h-fsr-aexc. */
|
|
|
|
void
|
|
sparc64_h_fsr_aexc_set (SIM_CPU *current_cpu, UQI newval)
|
|
{
|
|
CPU (h_fsr_aexc) = newval;
|
|
}
|
|
|
|
/* Get the value of h-fsr-cexc. */
|
|
|
|
UQI
|
|
sparc64_h_fsr_cexc_get (SIM_CPU *current_cpu)
|
|
{
|
|
return CPU (h_fsr_cexc);
|
|
}
|
|
|
|
/* Set a value for h-fsr-cexc. */
|
|
|
|
void
|
|
sparc64_h_fsr_cexc_set (SIM_CPU *current_cpu, UQI newval)
|
|
{
|
|
CPU (h_fsr_cexc) = newval;
|
|
}
|
|
|
|
/* Get the value of h-fpsr-fef. */
|
|
|
|
BI
|
|
sparc64_h_fpsr_fef_get (SIM_CPU *current_cpu)
|
|
{
|
|
return CPU (h_fpsr_fef);
|
|
}
|
|
|
|
/* Set a value for h-fpsr-fef. */
|
|
|
|
void
|
|
sparc64_h_fpsr_fef_set (SIM_CPU *current_cpu, BI newval)
|
|
{
|
|
CPU (h_fpsr_fef) = newval;
|
|
}
|
|
|
|
/* Get the value of h-fpsr-du. */
|
|
|
|
BI
|
|
sparc64_h_fpsr_du_get (SIM_CPU *current_cpu)
|
|
{
|
|
return CPU (h_fpsr_du);
|
|
}
|
|
|
|
/* Set a value for h-fpsr-du. */
|
|
|
|
void
|
|
sparc64_h_fpsr_du_set (SIM_CPU *current_cpu, BI newval)
|
|
{
|
|
CPU (h_fpsr_du) = newval;
|
|
}
|
|
|
|
/* Get the value of h-fpsr-dl. */
|
|
|
|
BI
|
|
sparc64_h_fpsr_dl_get (SIM_CPU *current_cpu)
|
|
{
|
|
return CPU (h_fpsr_dl);
|
|
}
|
|
|
|
/* Set a value for h-fpsr-dl. */
|
|
|
|
void
|
|
sparc64_h_fpsr_dl_set (SIM_CPU *current_cpu, BI newval)
|
|
{
|
|
CPU (h_fpsr_dl) = newval;
|
|
}
|
|
|
|
/* Get the value of h-fpsr. */
|
|
|
|
UQI
|
|
sparc64_h_fpsr_get (SIM_CPU *current_cpu)
|
|
{
|
|
return GET_H_FPSR ();
|
|
}
|
|
|
|
/* Set a value for h-fpsr. */
|
|
|
|
void
|
|
sparc64_h_fpsr_set (SIM_CPU *current_cpu, UQI newval)
|
|
{
|
|
SET_H_FPSR (newval);
|
|
}
|
|
|
|
/* Record trace results for INSN. */
|
|
|
|
void
|
|
sparc64_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
|
|
int *indices, TRACE_RECORD *tr)
|
|
{
|
|
}
|