c14d22a7a7
(CPU_OBJS): New variable. (SIM_OBJS): Add sparc-desc.o. (SIM_EXTRA_DEPS): Replace cpu-opc.h with sparc-desc.h. (sim-core.o): Add dev64.h dependency. (dev64.o): Add rule. (stamp-arch,stamp-cpu32): Update FLAGS variable, option syntax changed. (stamp-cpu64): Ditto. (stamp-desc): New rule. * configure.in (sim_link_files,sim_link_links): Delete. Set cpu_objs to one of SPARC32_OBJS,SPARC64_OBJS. * configure: Rebuild. * acconfig.h: Rebuild. * config.in: Rebuild. * dev64.c: New file. * dev64.h: New file. * sparc64.c: New file. * trap64.h: New file. * arch.c,arch.h,cpuall.h: Rebuild. * cpu32.c,decode32.c,decode32.h,model32.c,sem32.c: Rebuild. * sim-if.c (sparc_disassemble_insn): New function. (sim_open): sparc_cgen_cpu_open renamed from sparc_cgen_opcode_open. Set disassembler. (sim_close): sparc_cgen_cpu_open renamed from sparc_cgen_opcode_open. * sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include sparc-desc.h,sparc-opc.h,sparc-sim.h.
619 lines
17 KiB
C
619 lines
17 KiB
C
/* CPU family header for sparc32.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1999 Cygnus Solutions, Inc.
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This file is part of the Cygnus Simulators.
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*/
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#ifndef CPU_SPARC32_H
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#define CPU_SPARC32_H
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/* Maximum number of instructions that are fetched at a time.
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This is for LIW type instructions sets (e.g. m32r). */
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#define MAX_LIW_INSNS 1
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/* Maximum number of instructions that can be executed in parallel. */
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#define MAX_PARALLEL_INSNS 1
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/* CPU state information. */
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typedef struct {
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/* Hardware elements. */
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struct {
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/* program counter */
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USI h_pc;
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#define GET_H_PC() CPU (h_pc)
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#define SET_H_PC(x) (CPU (h_pc) = (x))
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/* next pc */
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SI h_npc;
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#define GET_H_NPC() CPU (h_npc)
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#define SET_H_NPC(x) (CPU (h_npc) = (x))
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/* GET_H_GR macro user-written */
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/* SET_H_GR macro user-written */
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/* icc carry bit */
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BI h_icc_c;
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#define GET_H_ICC_C() CPU (h_icc_c)
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#define SET_H_ICC_C(x) (CPU (h_icc_c) = (x))
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/* icc negative bit */
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BI h_icc_n;
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#define GET_H_ICC_N() CPU (h_icc_n)
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#define SET_H_ICC_N(x) (CPU (h_icc_n) = (x))
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/* icc overflow bit */
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BI h_icc_v;
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#define GET_H_ICC_V() CPU (h_icc_v)
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#define SET_H_ICC_V(x) (CPU (h_icc_v) = (x))
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/* icc zero bit */
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BI h_icc_z;
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#define GET_H_ICC_Z() CPU (h_icc_z)
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#define SET_H_ICC_Z(x) (CPU (h_icc_z) = (x))
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/* xcc carry bit */
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BI h_xcc_c;
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#define GET_H_XCC_C() CPU (h_xcc_c)
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#define SET_H_XCC_C(x) (CPU (h_xcc_c) = (x))
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/* xcc negative bit */
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BI h_xcc_n;
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#define GET_H_XCC_N() CPU (h_xcc_n)
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#define SET_H_XCC_N(x) (CPU (h_xcc_n) = (x))
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/* xcc overflow bit */
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BI h_xcc_v;
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#define GET_H_XCC_V() CPU (h_xcc_v)
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#define SET_H_XCC_V(x) (CPU (h_xcc_v) = (x))
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/* xcc zero bit */
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BI h_xcc_z;
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#define GET_H_XCC_Z() CPU (h_xcc_z)
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#define SET_H_XCC_Z(x) (CPU (h_xcc_z) = (x))
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/* GET_H_Y macro user-written */
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/* SET_H_Y macro user-written */
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/* ancilliary state registers */
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SI h_asr[32];
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#define GET_H_ASR(a1) CPU (h_asr)[a1]
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#define SET_H_ASR(a1, x) (CPU (h_asr)[a1] = (x))
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/* annul next insn? - assists execution */
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BI h_annul_p;
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#define GET_H_ANNUL_P() CPU (h_annul_p)
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#define SET_H_ANNUL_P(x) (CPU (h_annul_p) = (x))
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/* floating point regs */
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SF h_fr[32];
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#define GET_H_FR(a1) CPU (h_fr)[a1]
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#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
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/* psr register */
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USI h_psr;
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/* GET_H_PSR macro user-written */
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/* SET_H_PSR macro user-written */
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/* supervisor bit */
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BI h_s;
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#define GET_H_S() CPU (h_s)
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#define SET_H_S(x) (CPU (h_s) = (x))
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/* previous supervisor bit */
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BI h_ps;
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#define GET_H_PS() CPU (h_ps)
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#define SET_H_PS(x) (CPU (h_ps) = (x))
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/* processor interrupt level */
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UQI h_pil;
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#define GET_H_PIL() CPU (h_pil)
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#define SET_H_PIL(x) (CPU (h_pil) = (x))
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/* enable traps bit */
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BI h_et;
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#define GET_H_ET() CPU (h_et)
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#define SET_H_ET(x) (CPU (h_et) = (x))
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/* tbr register */
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SI h_tbr;
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/* GET_H_TBR macro user-written */
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/* SET_H_TBR macro user-written */
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/* current window pointer */
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UQI h_cwp;
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/* GET_H_CWP macro user-written */
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/* SET_H_CWP macro user-written */
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/* window invalid mask */
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USI h_wim;
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/* GET_H_WIM macro user-written */
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/* SET_H_WIM macro user-written */
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/* alternate global indicator */
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QI h_ag;
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#define GET_H_AG() CPU (h_ag)
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#define SET_H_AG(x) (CPU (h_ag) = (x))
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/* enable coprocessor bit */
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BI h_ec;
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#define GET_H_EC() CPU (h_ec)
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#define SET_H_EC(x) (CPU (h_ec) = (x))
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/* enable fpu bit */
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BI h_ef;
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#define GET_H_EF() CPU (h_ef)
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#define SET_H_EF(x) (CPU (h_ef) = (x))
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/* floating point status register */
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USI h_fsr;
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#define GET_H_FSR() CPU (h_fsr)
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#define SET_H_FSR(x) (CPU (h_fsr) = (x))
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} hardware;
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#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
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} SPARC32_CPU_DATA;
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/* Cover fns for register access. */
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USI sparc32_h_pc_get (SIM_CPU *);
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void sparc32_h_pc_set (SIM_CPU *, USI);
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SI sparc32_h_npc_get (SIM_CPU *);
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void sparc32_h_npc_set (SIM_CPU *, SI);
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SI sparc32_h_gr_get (SIM_CPU *, UINT);
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void sparc32_h_gr_set (SIM_CPU *, UINT, SI);
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BI sparc32_h_icc_c_get (SIM_CPU *);
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void sparc32_h_icc_c_set (SIM_CPU *, BI);
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BI sparc32_h_icc_n_get (SIM_CPU *);
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void sparc32_h_icc_n_set (SIM_CPU *, BI);
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BI sparc32_h_icc_v_get (SIM_CPU *);
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void sparc32_h_icc_v_set (SIM_CPU *, BI);
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BI sparc32_h_icc_z_get (SIM_CPU *);
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void sparc32_h_icc_z_set (SIM_CPU *, BI);
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BI sparc32_h_xcc_c_get (SIM_CPU *);
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void sparc32_h_xcc_c_set (SIM_CPU *, BI);
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BI sparc32_h_xcc_n_get (SIM_CPU *);
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void sparc32_h_xcc_n_set (SIM_CPU *, BI);
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BI sparc32_h_xcc_v_get (SIM_CPU *);
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void sparc32_h_xcc_v_set (SIM_CPU *, BI);
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BI sparc32_h_xcc_z_get (SIM_CPU *);
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void sparc32_h_xcc_z_set (SIM_CPU *, BI);
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SI sparc32_h_y_get (SIM_CPU *);
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void sparc32_h_y_set (SIM_CPU *, SI);
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SI sparc32_h_asr_get (SIM_CPU *, UINT);
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void sparc32_h_asr_set (SIM_CPU *, UINT, SI);
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BI sparc32_h_annul_p_get (SIM_CPU *);
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void sparc32_h_annul_p_set (SIM_CPU *, BI);
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SF sparc32_h_fr_get (SIM_CPU *, UINT);
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void sparc32_h_fr_set (SIM_CPU *, UINT, SF);
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USI sparc32_h_psr_get (SIM_CPU *);
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void sparc32_h_psr_set (SIM_CPU *, USI);
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BI sparc32_h_s_get (SIM_CPU *);
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void sparc32_h_s_set (SIM_CPU *, BI);
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BI sparc32_h_ps_get (SIM_CPU *);
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void sparc32_h_ps_set (SIM_CPU *, BI);
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UQI sparc32_h_pil_get (SIM_CPU *);
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void sparc32_h_pil_set (SIM_CPU *, UQI);
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BI sparc32_h_et_get (SIM_CPU *);
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void sparc32_h_et_set (SIM_CPU *, BI);
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SI sparc32_h_tbr_get (SIM_CPU *);
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void sparc32_h_tbr_set (SIM_CPU *, SI);
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UQI sparc32_h_cwp_get (SIM_CPU *);
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void sparc32_h_cwp_set (SIM_CPU *, UQI);
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USI sparc32_h_wim_get (SIM_CPU *);
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void sparc32_h_wim_set (SIM_CPU *, USI);
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QI sparc32_h_ag_get (SIM_CPU *);
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void sparc32_h_ag_set (SIM_CPU *, QI);
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BI sparc32_h_ec_get (SIM_CPU *);
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void sparc32_h_ec_set (SIM_CPU *, BI);
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BI sparc32_h_ef_get (SIM_CPU *);
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void sparc32_h_ef_set (SIM_CPU *, BI);
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USI sparc32_h_fsr_get (SIM_CPU *);
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void sparc32_h_fsr_set (SIM_CPU *, USI);
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/* These must be hand-written. */
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extern CPUREG_FETCH_FN sparc32_fetch_register;
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extern CPUREG_STORE_FN sparc32_store_register;
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typedef struct {
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int empty;
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} MODEL_SPARC32_DEF_DATA;
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/* The ARGBUF struct. */
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struct argbuf {
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/* These are the baseclass definitions. */
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IADDR addr;
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const IDESC *idesc;
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char trace_p;
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char profile_p;
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/* cpu specific data follows */
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CGEN_INSN_INT insn;
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int written;
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};
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/* A cached insn.
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??? SCACHE used to contain more than just argbuf. We could delete the
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type entirely and always just use ARGBUF, but for future concerns and as
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a level of abstraction it is left in. */
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struct scache {
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struct argbuf argbuf;
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};
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/* Macros to simplify extraction, reading and semantic code.
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These define and assign the local vars that contain the insn's fields. */
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#define EXTRACT_IFMT_EMPTY_VARS \
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/* Instruction fields. */ \
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unsigned int length;
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#define EXTRACT_IFMT_EMPTY_CODE \
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length = 0; \
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#define EXTRACT_IFMT_RD_ASR_VARS \
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/* Instruction fields. */ \
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INT f_simm13; \
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UINT f_i; \
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UINT f_rs1; \
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UINT f_op3; \
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UINT f_rd; \
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UINT f_op; \
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unsigned int length;
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#define EXTRACT_IFMT_RD_ASR_CODE \
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length = 4; \
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f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
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f_i = EXTRACT_UINT (insn, 32, 13, 1); \
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f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
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f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
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f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
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f_op = EXTRACT_UINT (insn, 32, 31, 2); \
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#define EXTRACT_IFMT_WR_ASR_VARS \
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/* Instruction fields. */ \
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UINT f_rs2; \
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INT f_res_asi; \
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UINT f_i; \
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UINT f_rs1; \
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UINT f_op3; \
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UINT f_rd; \
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UINT f_op; \
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unsigned int length;
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#define EXTRACT_IFMT_WR_ASR_CODE \
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length = 4; \
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f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
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f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
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f_i = EXTRACT_UINT (insn, 32, 13, 1); \
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f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
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f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
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f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
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f_op = EXTRACT_UINT (insn, 32, 31, 2); \
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#define EXTRACT_IFMT_WR_ASR_IMM_VARS \
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/* Instruction fields. */ \
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INT f_simm13; \
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UINT f_i; \
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UINT f_rs1; \
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UINT f_op3; \
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UINT f_rd; \
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UINT f_op; \
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unsigned int length;
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#define EXTRACT_IFMT_WR_ASR_IMM_CODE \
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length = 4; \
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f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
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f_i = EXTRACT_UINT (insn, 32, 13, 1); \
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f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
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f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
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f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
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f_op = EXTRACT_UINT (insn, 32, 31, 2); \
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#define EXTRACT_IFMT_RD_PSR_VARS \
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/* Instruction fields. */ \
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INT f_simm13; \
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UINT f_i; \
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UINT f_rs1; \
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UINT f_op3; \
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UINT f_rd; \
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UINT f_op; \
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unsigned int length;
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#define EXTRACT_IFMT_RD_PSR_CODE \
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length = 4; \
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f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
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f_i = EXTRACT_UINT (insn, 32, 13, 1); \
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f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
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f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
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f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
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f_op = EXTRACT_UINT (insn, 32, 31, 2); \
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#define EXTRACT_IFMT_WR_PSR_VARS \
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/* Instruction fields. */ \
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UINT f_rs2; \
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INT f_res_asi; \
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UINT f_i; \
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UINT f_rs1; \
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UINT f_op3; \
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UINT f_rd; \
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UINT f_op; \
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unsigned int length;
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#define EXTRACT_IFMT_WR_PSR_CODE \
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length = 4; \
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f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
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f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
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f_i = EXTRACT_UINT (insn, 32, 13, 1); \
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f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
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f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
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f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
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f_op = EXTRACT_UINT (insn, 32, 31, 2); \
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#define EXTRACT_IFMT_WR_PSR_IMM_VARS \
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/* Instruction fields. */ \
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INT f_simm13; \
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UINT f_i; \
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UINT f_rs1; \
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UINT f_op3; \
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UINT f_rd; \
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UINT f_op; \
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unsigned int length;
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#define EXTRACT_IFMT_WR_PSR_IMM_CODE \
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length = 4; \
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f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
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f_i = EXTRACT_UINT (insn, 32, 13, 1); \
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f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
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f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
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f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
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f_op = EXTRACT_UINT (insn, 32, 31, 2); \
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#define EXTRACT_IFMT_LDSTUB_REG_REG_VARS \
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/* Instruction fields. */ \
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UINT f_rs2; \
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INT f_res_asi; \
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UINT f_i; \
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UINT f_rs1; \
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UINT f_op3; \
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UINT f_rd; \
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UINT f_op; \
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unsigned int length;
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#define EXTRACT_IFMT_LDSTUB_REG_REG_CODE \
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length = 4; \
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f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
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f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
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f_i = EXTRACT_UINT (insn, 32, 13, 1); \
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f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
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f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
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f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
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f_op = EXTRACT_UINT (insn, 32, 31, 2); \
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#define EXTRACT_IFMT_LDSTUB_REG_IMM_VARS \
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/* Instruction fields. */ \
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INT f_simm13; \
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UINT f_i; \
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UINT f_rs1; \
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UINT f_op3; \
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UINT f_rd; \
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UINT f_op; \
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unsigned int length;
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#define EXTRACT_IFMT_LDSTUB_REG_IMM_CODE \
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length = 4; \
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f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
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f_i = EXTRACT_UINT (insn, 32, 13, 1); \
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f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
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f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
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f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
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f_op = EXTRACT_UINT (insn, 32, 31, 2); \
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#define EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS \
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/* Instruction fields. */ \
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UINT f_rs2; \
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UINT f_asi; \
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UINT f_i; \
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UINT f_rs1; \
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UINT f_op3; \
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UINT f_rd; \
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UINT f_op; \
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unsigned int length;
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#define EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE \
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length = 4; \
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f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
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f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
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f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_LDD_REG_REG_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
INT f_res_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LDD_REG_REG_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_LDD_REG_IMM_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_simm13; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LDD_REG_IMM_CODE \
|
|
length = 4; \
|
|
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_LDD_REG_REG_ASI_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
UINT f_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LDD_REG_REG_ASI_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_FP_LD_REG_REG_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
INT f_res_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_FP_LD_REG_REG_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_FP_LD_REG_IMM_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_simm13; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_FP_LD_REG_IMM_CODE \
|
|
length = 4; \
|
|
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
UINT f_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_SETHI_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_hi22; \
|
|
UINT f_op2; \
|
|
UINT f_rd; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_SETHI_CODE \
|
|
length = 4; \
|
|
f_hi22 = EXTRACT_INT (insn, 32, 21, 22); \
|
|
f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
|
|
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_UNIMP_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_imm22; \
|
|
UINT f_op2; \
|
|
UINT f_rd_res; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_UNIMP_CODE \
|
|
length = 4; \
|
|
f_imm22 = EXTRACT_INT (insn, 32, 21, 22); \
|
|
f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
|
|
f_rd_res = EXTRACT_UINT (insn, 32, 29, 5); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_CALL_VARS \
|
|
/* Instruction fields. */ \
|
|
SI f_disp30; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_CALL_CODE \
|
|
length = 4; \
|
|
f_disp30 = ((((EXTRACT_INT (insn, 32, 29, 30)) << (2))) + (pc)); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_BA_VARS \
|
|
/* Instruction fields. */ \
|
|
SI f_disp22; \
|
|
UINT f_op2; \
|
|
UINT f_fmt2_cond; \
|
|
UINT f_a; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_BA_CODE \
|
|
length = 4; \
|
|
f_disp22 = ((((EXTRACT_INT (insn, 32, 21, 22)) << (2))) + (pc)); \
|
|
f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
|
|
f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
|
|
f_a = EXTRACT_UINT (insn, 32, 29, 1); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_TA_VARS \
|
|
/* Instruction fields. */ \
|
|
UINT f_rs2; \
|
|
INT f_res_asi; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_fmt2_cond; \
|
|
UINT f_a; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_TA_CODE \
|
|
length = 4; \
|
|
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
|
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
|
|
f_a = EXTRACT_UINT (insn, 32, 29, 1); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
#define EXTRACT_IFMT_TA_IMM_VARS \
|
|
/* Instruction fields. */ \
|
|
INT f_simm13; \
|
|
UINT f_i; \
|
|
UINT f_rs1; \
|
|
UINT f_op3; \
|
|
UINT f_fmt2_cond; \
|
|
UINT f_a; \
|
|
UINT f_op; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_TA_IMM_CODE \
|
|
length = 4; \
|
|
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
|
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
|
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
|
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
|
f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
|
|
f_a = EXTRACT_UINT (insn, 32, 29, 1); \
|
|
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
|
|
|
/* Collection of various things for the trace handler to use. */
|
|
|
|
typedef struct trace_record {
|
|
IADDR pc;
|
|
/* FIXME:wip */
|
|
} TRACE_RECORD;
|
|
|
|
#endif /* CPU_SPARC32_H */
|