5437a02abc
Just like their LD1RQ{H,W,D} counterparts, as per the specification the
index registers get scaled by element size.
45 lines
1.1 KiB
Plaintext
45 lines
1.1 KiB
Plaintext
2020-01-03 Jan Beulich <jbeulich@suse.com>
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* aarch64-tbl.h (aarch64_opcode_table): Use
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SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
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forms of SUDOT and USDOT.
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
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uzip{1,2}.
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* opcodes/aarch64-dis-2.c: Re-generate.
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
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FMMLA encoding.
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* opcodes/aarch64-dis-2.c: Re-generate.
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2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
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* z80-dis.c: Add support for eZ80 and Z80 instructions.
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2020-01-01 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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For older changes see ChangeLog-2019
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Copyright (C) 2020 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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