Commit Graph

1195 Commits

Author SHA1 Message Date
Terry Guo
c4694f172b Enable support to Intel Keylocker instructions
gas/
	* NEWS: Add Key Locker.
	* config/tc-i386.c (cpu_arch): Add .kl and .wide_kl.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document kl and wide_kl.
	* testsuite/gas/i386/i386.exp: Run keylocker tests.
	* testsuite/gas/i386/keylocker-intel.d: New test.
	* testsuite/gas/i386/keylocker.d: Likewise.
	* testsuite/gas/i386/keylocker.s: Likewise.
	* testsuite/gas/i386/x86-64-keylocker-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-keylocker.d: Likewise.
	* testsuite/gas/i386/x86-64-keylocker.s: Likewise.
	* testsuite/gas/i386/x86-64-property-10.d: Likewise.
	* testsuite/gas/i386/property-10.d: Likewise.
	* testsuite/gas/i386/property-10.s: Likewise.

opcodes/
	* i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
	MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
	MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
	MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
	PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
	(reg_table): New instructions (see prefixes above).
	(prefix_table): Likewise.
	(three_byte_table): Likewise.
	(mod_table): Likewise
	* i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
	CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
	(cpu_flags): Likewise.
	(operand_type_init): Likewise.
	* i386-opc.h (enum): Add CpuKL and CpuWide_KL.
	(i386_cpu_flags): Add cpukl and cpuwide_kl.
	* i386-opc.tbl: Add KL and WIDE_KL insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
2020-09-23 10:47:44 +08:00
Nick Clifton
b1766e7ce8 Add a new ".nop" directive to the assembler to allow the creation of no-op instructions in an architeture neutral manner.
* read.c (s_nop): New function.  Handles the .nop directive.
	(potable): Add entry for "nop".
	(s_nops): Code tidy.
	* read.h (s_nop): Add prototype.
	* config/tc-bpf.h (md_single_noop_insn): Define.
	* config/tc-mmix.h (md_single_noop_insn): Define.
	* config/tc-or1k.h (md_single_noop_insn): Define.
	* config/tc-s12z.c (md_assemble): Preserve the input line pointer,
	rather than corrupting it.
	* write.c (relax_segment): Update error message regarding
	non-absolute values passed to .fill and .nops.
	* NEWS: Mention the new directive.
	* doc/as.texi: Document the new directive.
	* doc/internals.texi: Document the new internal macros used to
	implement the new directive.
	* testsuite/gas/all/nop.s: New test.
	* testsuite/gas/all/nop.d: New test control file.
	* testsuite/gas/all/gas.exp: Run the new test.
	* testsuite/gas/elf/dwarf-5-nop-for-line-table.s: New test.
	* testsuite/gas/elf/dwarf-5-nop-for-line-table.d: New test
	control file.
	* testsuite/gas/elf/elf.exp: Run the new test.
	* testsuite/gas/i386/space1.l: Adjust expected output.
2020-09-14 16:14:24 +01:00
Mark Wielaard
edc7a80a9c gas: Don't error when .debug_line already exists, unless .loc was used
When -g was used to generate DWARF gas would error out when a .debug_line
already exists. But when a .debug_info section already exists it would
simply skip generating one without warning or error. Do the same for
.debug_line. It is only an error when the user explicitly uses .loc
directives and also generates the .debug_line table itself.

The tests are unfortunately arch specific because the line table is only
generated when actual instructions have been emitted. Use i386 because
that is probably the most used architecture. Before this patch the new
dwarf-line-2 testcase would fail, with this patch it succeeds (and doesn't
try to add its own line table).

gas/ChangeLog:

    * as.texi (-g): Explicitly mention when .debug_info and .debug_line
    are generated for the DWARF format.
    (Loc): Add that it is an error to both use a .loc directive and
    generate a .debug_line yourself.
    * dwarf2dbg.c (dwarf2_any_loc_directive_seen): New static variable.
    (dwarf2_directive_loc): Set dwarf2_any_loc_directive_seen to TRUE.
    (dwarf2_finish): Check dwarf2_any_loc_directive_seen before emitting
    an error. Only create .debug_line if it is empty (or doesn't exist).
    * testsuite/gas/i386/i386.exp: Add dwarf2-line-{1,2,3,4} when testing
    an elf target.
    * testsuite/gas/i386/dwarf2-line-{1,2,3,4}.{s,d,l}: New test files.
2020-09-11 19:18:44 +02:00
Alex Coplan
f1363b0fb4 aarch64: Add -mcpu option for Cortex-R82
This adds support for the Arm Cortex-R82 CPU in AArch64 GAS. For more
information about this processor, see [0].

[0] : https://developer.arm.com/ip-products/processors/cortex-r/cortex-r82

gas/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* config/tc-aarch64.c (aarch64_cpus): Add Cortex-R82.
	* doc/c-aarch64.texi: Document -mcpu=cortex-r82.
2020-09-08 14:22:59 +01:00
Alex Coplan
95830c988a aarch64: Add base support for Armv8-R
This patch adds the basic infrastructure needed to support Armv8-R in
AArch64 binutils: new command-line flags, new feature bits, a new BFD
architecture, and support for differentiating between architecture
variants in the disassembler.

The new command-line options added by this patch are -march=armv8-r in
GAS and -m aarch64:armv8-r in objdump.

The disassembler support is necessary since Armv8-R AArch64 introduces a
system register (VSCTLR_EL2) which shares an encoding with a different
system register (TTBR0_EL2) in Armv8-A. This also allows us to use the
correct preferred disassembly for the new DFB alias introduced in
Armv8-R.

bfd/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* archures.c (bfd_mach_aarch64_8R): New.
	* bfd-in2.h: Regenerate.
	* cpu-aarch64.c (bfd_aarch64_arch_v8_r): New.
	(bfd_aarch64_arch_ilp32): Update tail pointer.

gas/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* config/tc-aarch64.c (aarch64_archs): Add armv8-r.
	* doc/c-aarch64.texi: Document -march=armv8-r.

include/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_V8_A): New.
	(AARCH64_FEATURE_V8_R): New.
	(AARCH64_ARCH_V8): Include new A-profile feature bit.
	(AARCH64_ARCH_V8_R): New.

opcodes/ChangeLog:

2020-09-08  Alex Coplan  <alex.coplan@arm.com>

	* aarch64-dis.c (arch_variant): New.
	(determine_disassembling_preference): Disassemble according to
	arch variant.
	(select_aarch64_variant): New.
	(print_insn_aarch64): Set feature set.
2020-09-08 14:14:11 +01:00
H.J. Lu
4c8584be76 ELF: Document the .tls_common directive
Document the .tls_common directive added by

commit b8871f357f
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Mon Feb 22 09:18:52 2016 -0800

    Properly implement STT_COMMON

	* doc/as.texi: Document the .tls_common directive.
2020-09-01 07:47:00 -07:00
Martin Liska
a0522545b6 Remove --reduce-memory-overheads and --hash-size arguments.
* NEWS: Mention --reduce-memory-overheads and --hash-size arguments
	options.
	* as.c: Remove the options from help.
	* doc/as.texi: Remove options.
	* doc/internals.texi: Remove hash from documentation.
	* hash.c (struct hash_entry): Remove.
	(struct hash_control): Likewise.
	(set_gas_hash_table_size): Likewise.
	(hash_new_sized): Likewise.
	(hash_new): Likewise.
	(hash_die): Likewise.
	(hash_lookup): Likewise.
	(hash_insert): Likewise.
	(hash_jam): Likewise.
	(hash_replace): Likewise.
	(hash_find): Likewise.
	(hash_find_n): Likewise.
	(hash_delete): Likewise.
	(hash_traverse): Likewise.
	(hash_print_statistics): Likewise.
	(TABLES): Likewise.
	(STATBUFSIZE): Likewise.
	(main): Likewise.
	(what): Likewise.
	(destroy): Likewise.
	(applicatee): Likewise.
	(whattable): Likewise.
	* hash.h (struct hash_control): Likewise.
	(set_gas_hash_table_size): Likewise.
	(hash_new): Likewise.
	(hash_new_sized): Likewise.
	(hash_die): Likewise.
	(hash_insert): Likewise.
	(hash_jam): Likewise.
	(hash_replace): Likewise.
	(hash_find): Likewise.
	(hash_find_n): Likewise.
	(hash_delete): Likewise.
	(hash_traverse): Likewise.
	(hash_print_statistics): Likewise.
2020-08-20 10:57:52 +09:30
Nick Clifton
369afd5008 The description for -mno-csr-check talks about "cheching" rather than "checking".
PR 26346
	* doc/c-riscv.texi (RISC-V-Options): Fix typo in the description
	of the -mno-csr-check option.
2020-08-12 13:47:04 +01:00
Mark Wielaard
25b1f10d9b gas: Fix as.texi typo infortmation
gas/ChangeLog:

	* doc/as.texi (--gdwarf-[345]): Fix typo.
2020-08-04 11:28:39 +02:00
H.J. Lu
41eb8e8885 x86: Add {disp16} pseudo prefix
Use Prefix_XXX for pseudo prefixes.  Add {disp16} pseudo prefix and
replace {disp32} pseudo prefix with {disp16} in 16-bit mode test.
Check invalid {disp16}/{disp32} pseudo prefixes.

gas/

	PR gas/26305
	* config/tc-i386.c (_i386_insn::disp_encoding): Add
	disp_encoding_16bit.
	(parse_insn): Check Prefix_XXX for pseudo prefixes.  Handle
	{disp16}.
	(build_modrm_byte): Handle {disp16}.
	(i386_index_check): Check invalid {disp16} and {disp32} pseudo
	prefixes.
	* doc/c-i386.texi: Update {disp32} documentation and document
	{disp16}.
	* testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo.
	* testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16}
	tests.
	* testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps
	tests with 128-byte displacement.  Add {disp16} tests.
	* testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32}
	vmovaps test.  Add (%r13)/(%r13d) tests.
	* testsuite/gas/i386/x86-64-inval-pseudo.l: New file.
	* testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise.
	* testsuite/gas/i386/inval-pseudo.l: Updated.
	* testsuite/gas/i386/pseudos.d: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.d: Likewise.

opcodes/

	PR gas/26305
	* i386-opc.h (Prefix_Disp8): New.
	(Prefix_Disp16): Likewise.
	(Prefix_Disp32): Likewise.
	(Prefix_Load): Likewise.
	(Prefix_Store): Likewise.
	(Prefix_VEX): Likewise.
	(Prefix_VEX3): Likewise.
	(Prefix_EVEX): Likewise.
	(Prefix_REX): Likewise.
	(Prefix_NoOptimize): Likewise.
	* i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
	* i386-tbl.h: Regenerated.
2020-07-30 16:13:17 -07:00
Rainer Orth
c8693053f8 Unify Solaris procfs and largefile handling
GDB currently doesn't build on 32-bit Solaris:

* On Solaris 11.4/x86:

In file included from /usr/include/sys/procfs.h:26,
                 from /vol/src/gnu/gdb/hg/master/dist/gdb/i386-sol2-nat.c:24:
/usr/include/sys/old_procfs.h:31:2: error: #error "Cannot use procfs in the large file compilation environment"
 #error "Cannot use procfs in the large file compilation environment"
  ^~~~~

* On Solaris 11.3/x86 there are several more instances of this.

The interaction between procfs and large-file support historically has
been a royal mess on Solaris:

* There are two versions of the procfs interface:

** The old ioctl-based /proc, deprecated and not used any longer in
   either gdb or binutils.

** The `new' (introduced in Solaris 2.6, 1997) structured /proc.

* There are two headers one can possibly include:

** <procfs.h> which only provides the structured /proc, definining
   _STRUCTURED_PROC=1 and then including ...

** <sys/procfs.h> which defaults to _STRUCTURED_PROC=0, the ioctl-based
   /proc, but provides structured /proc if _STRUCTURED_PROC == 1.

* procfs and the large-file environment didn't go well together:

** Until Solaris 11.3, <sys/procfs.h> would always #error in 32-bit
   compilations when the large-file environment was active
   (_FILE_OFFSET_BITS == 64).

** In both Solaris 11.4 and Illumos, this restriction was lifted for
   structured /proc.

So one has to be careful always to define _STRUCTURED_PROC=1 when
testing for or using <sys/procfs.h> on Solaris.  As the errors above
show, this isn't always the case in binutils-gdb right now.

Also one may need to disable large-file support for 32-bit compilations
on Solaris.  config/largefile.m4 meant to do this by wrapping the
AC_SYS_LARGEFILE autoconf macro with appropriate checks, yielding
ACX_LARGEFILE.  Unfortunately the macro doesn't always succeed because
it neglects the _STRUCTURED_PROC part.

To make things even worse, since GCC 9 g++ predefines
_FILE_OFFSET_BITS=64 on Solaris.  So even if largefile.m4 deciced not to
enable large-file support, this has no effect, breaking the gdb build.

This patch addresses all this as follows:

* All tests for the <sys/procfs.h> header are made with
  _STRUCTURED_PROC=1, the definition going into the various config.h
  files instead of having to make them (and sometimes failing) in the
  affected sources.

* To cope with the g++ predefine of _FILE_OFFSET_BITS=64,
  -U_FILE_OFFSET_BITS is added to various *_CPPFLAGS variables.  It had
  been far easier to have just

  #undef _FILE_OFFSET_BITS

  in config.h, but unfortunately such a construct in config.in is
  commented by config.status irrespective of indentation and whitespace
  if large-file support is disabled.  I found no way around this and
  putting the #undef in several global headers for bfd, binutils, ld,
  and gdb seemed way more invasive.

* Last, the applicability check in largefile.m4 was modified only to
  disable largefile support if really needed.  To do so, it checks if
  <sys/procfs.h> compiles with _FILE_OFFSET_BITS=64 defined.  If it
  doesn't, the disabling only happens if gdb exists in-tree and isn't
  disabled, otherwise (building binutils from a tarball), there's no
  conflict.

  What initially confused me was the check for $plugins here, which
  originally caused the disabling not to take place.  Since AC_PLUGINGS
  does enable plugin support if <dlfcn.h> exists (which it does on
  Solaris), the disabling never happened.

  I could find no explanation why the linker plugin needs large-file
  support but thought it would be enough if gld and GCC's lto-plugin
  agreed on the _FILE_OFFSET_BITS value.  Unfortunately, that's not
  enough: lto-plugin uses the simple-object interface from libiberty,
  which includes off_t arguments.  So to fully disable large-file
  support would mean also disabling it in libiberty and its users: gcc
  and libstdc++-v3.  This seems highly undesirable, so I decided to
  disable the linker plugin instead if large-file support won't work.

The patch allows binutils+gdb to build on i386-pc-solaris2.11 (both
Solaris 11.3 and 11.4, using GCC 9.3.0 which is the worst case due to
predefined _FILE_OFFSET_BITS=64).  Also regtested on
amd64-pc-solaris2.11 (again on Solaris 11.3 and 11.4),
x86_64-pc-linux-gnu and i686-pc-linux-gnu.

	config:
	* largefile.m4 (ACX_LARGEFILE) <sparc-*-solaris*|i?86-*-solaris*>:
	Check for <sys/procfs.h> incompatilibity with large-file support
	on Solaris.
	Only disable large-file support and perhaps plugins if needed.
	Set, substitute LARGEFILE_CPPFLAGS if so.

	bfd:
	* bfd.m4 (BFD_SYS_PROCFS_H): New macro.
	(BFD_HAVE_SYS_PROCFS_TYPE): Require BFD_SYS_PROCFS_H.
	Don't define _STRUCTURED_PROC.
	(BFD_HAVE_SYS_PROCFS_TYPE_MEMBER): Likewise.
	* elf.c [HAVE_SYS_PROCFS_H] (_STRUCTURED_PROC): Don't define.
	* configure.ac: Use BFD_SYS_PROCFS_H to check for <sys/procfs.h>.
	* configure, config.in: Regenerate.
	* Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* Makefile.in, doc/Makefile.in: Regenerate.

	binutils:
	* Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* Makefile.in, doc/Makefile.in: Regenerate.
	* configure: Regenerate.

	gas:
	* Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* Makefile.in, doc/Makefile.in: Regenerate.
	* configure: Regenerate.

	gdb:
	* proc-api.c (_STRUCTURED_PROC): Don't define.
	* proc-events.c: Likewise.
	* proc-flags.c: Likewise.
	* proc-why.c: Likewise.
	* procfs.c: Likewise.

	* Makefile.in (INTERNAL_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* configure, config.in: Regenerate.

	gdbserver:
	* configure, config.in: Regenerate.

	gdbsupport:
	* Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* common.m4 (GDB_AC_COMMON): Use BFD_SYS_PROCFS_H to check for
	<sys/procfs.h>.
	* Makefile.in: Regenerate.
	* configure, config.in: Regenerate.

	gnulib:
	* configure.ac: Run ACX_LARGEFILE before gl_EARLY.
	* configure: Regenerate.

	gprof:
	* Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

	ld:
	* Makefile.am (AM_CPPFLAGS): Add LARGEFILE_CPPFLAGS.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
2020-07-30 15:41:50 +02:00
H.J. Lu
1a02d6b0ff x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp)
Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use
disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}.

Note: Since there is no disp32 on 0(%bp), use disp16 instead.

	PR gas/26305
	* config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on
	(%bp)/(%ebp)/(%rbp) for {disp32}.
	* doc/c-i386.texi: Update {disp32} documentation.
	* testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests.
	* testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests.
	* testsuite/gas/i386/pseudos.d: Updated.
	* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
2020-07-28 03:55:53 -07:00
H.J. Lu
608d61c202 doc: Replace preceeded with preceded
binutils/

	* doc/binutils.texi: Replace preceeded with preceded.

gas/

	* doc/as.texi: Replace preceeded with preceded.
2020-07-27 05:52:14 -07:00
Lili Cui
260cd341da x86: Add support for Intel AMX instructions
gas/

	* doc/c-i386.texi: Document amx_int8, amx_bf16 and amx_tile.
	* config/tc-i386.c (i386_error): Add invalid_sib_address.
	(cpu_arch): Add .amx_int8, .amx_bf16 and .amx_tile.
	(cpu_noarch): Add noamx_int8, noamx_bf16 and noamx_tile.
	(match_simd_size): Add tmmword check.
	(operand_type_match): Add tmmword.
	(type_names): Add rTMM.
	(i386_error): Add invalid_tmm_register_set.
	(check_VecOperands): Handle invalid_sib_address and
	invalid_tmm_register_set.
	(match_template): Handle invalid_sib_address.
	(build_modrm_byte): Handle non-vector SIB and zmmword.
	(i386_index_check): Disallow RegIP for non-vector SIB.
	(check_register): Handle zmmword.
	* testsuite/gas/i386/i386.exp: Add AMX new tests.
	* testsuite/gas/i386/intel-regs.d: Add tmm.
	* testsuite/gas/i386/intel-regs.s: Add tmm.
	* testsuite/gas/i386/x86-64-amx-intel.d: New.
	* testsuite/gas/i386/x86-64-amx-inval.l: New.
	* testsuite/gas/i386/x86-64-amx-inval.s: New.
	* testsuite/gas/i386/x86-64-amx.d: New.
	* testsuite/gas/i386/x86-64-amx.s: New.
	* testsuite/gas/i386/x86-64-amx-bad.d: New.
	* testsuite/gas/i386/x86-64-amx-bad.s: New.

opcodes/

	* i386-dis.c (TMM): New.
	(EXtmm): Likewise.
	(VexTmm): Likewise.
	(MVexSIBMEM): Likewise.
	(tmm_mode): Likewise.
	(vex_sibmem_mode): Likewise.
	(REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
	(MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
	(MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
	(MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
	(MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
	(MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
	(MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
	(MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
	(MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
	(MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
	(MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
	(MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
	(RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
	(PREFIX_VEX_0F3849_X86_64): Likewise.
	(PREFIX_VEX_0F384B_X86_64): Likewise.
	(PREFIX_VEX_0F385C_X86_64): Likewise.
	(PREFIX_VEX_0F385E_X86_64): Likewise.
	(X86_64_VEX_0F3849): Likewise.
	(X86_64_VEX_0F384B): Likewise.
	(X86_64_VEX_0F385C): Likewise.
	(X86_64_VEX_0F385E): Likewise.
	(VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
	(VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
	(VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
	(VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
	(VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
	(VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
	(VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
	(VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
	(VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
	(VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
	(VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
	(VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
	(VEX_W_0F3849_X86_64_P_0): Likewise.
	(VEX_W_0F3849_X86_64_P_2): Likewise.
	(VEX_W_0F3849_X86_64_P_3): Likewise.
	(VEX_W_0F384B_X86_64_P_1): Likewise.
	(VEX_W_0F384B_X86_64_P_2): Likewise.
	(VEX_W_0F384B_X86_64_P_3): Likewise.
	(VEX_W_0F385C_X86_64_P_1): Likewise.
	(VEX_W_0F385E_X86_64_P_0): Likewise.
	(VEX_W_0F385E_X86_64_P_1): Likewise.
	(VEX_W_0F385E_X86_64_P_2): Likewise.
	(VEX_W_0F385E_X86_64_P_3): Likewise.
	(names_tmm): Likewise.
	(att_names_tmm): Likewise.
	(intel_operand_size): Handle void_mode.
	(OP_XMM): Handle tmm_mode.
	(OP_EX): Likewise.
	(OP_VEX): Likewise.
	* i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
	CpuAMX_BF16 and CpuAMX_TILE.
	(operand_type_shorthands): Add RegTMM.
	(operand_type_init): Likewise.
	(operand_types): Add Tmmword.
	(cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
	(cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
	* i386-opc.h (CpuAMX_INT8): New.
	(CpuAMX_BF16): Likewise.
	(CpuAMX_TILE): Likewise.
	(SIBMEM): Likewise.
	(Tmmword): Likewise.
	(i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
	(i386_opcode_modifier): Extend width of fields vexvvvv and sib.
	(i386_operand_type): Add tmmword.
	* i386-opc.tbl: Add AMX instructions.
	* i386-reg.tbl: Add AMX registers.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2020-07-10 05:18:34 -07:00
H.J. Lu
dbdba9b04d x86: Remove an incorrect AVX2 entry
The upper 16 vector registers were added by AVX512.

	PR gas/26212
	* doc/c-i386.texi: Remove an incorrect AVX2 entry.
2020-07-07 05:06:38 -07:00
Pat Bernardi
85f7484a3a m68k: tag floating-point ABI used
This patch adds GNU attribute support to m68k and utilises it to tag the
floating-point calling convention used (hard-float or soft-float). It enables
the linker to ensure linked objects use a consistent floating-point ABI and
allows tools like GDB to infer the ABI used from the ELF file. It is based on
similar work done for PowerPC.

bfd/
	* elf32-m68k.c (m68k_elf_merge_obj_attributes): New function.
	(elf32_m68k_merge_private_bfd_data): Merge GNU attributes.
binutils/
	* readelf.c (display_m68k_gnu_attribute): New function.
	(process_arch_specific): Call display_m68k_gnu_attribute for EM_68K.
gas/
	* config/tc-m68k.c (m68k_elf_gnu_attribute): New function.
	(md_pseudo_table): Handle "gnu_attribute".
	* doc/as.texi: Document GNU attribute for M68K.
include/
	* elf/m68k.h: Add enum for GNU object attribute with floating point
	tag name and values.
ld/
	* testsuite/ld-m68k/attr-gnu-4-0.s: New file.
	* testsuite/ld-m68k/attr-gnu-4-1.s: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-2.s: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-00.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-01.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-02.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-10.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-11.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-12.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-20.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-21.d: Likewise.
	* testsuite/ld-m68k/attr-gnu-4-22.d: Likewise.
	* testsuite/ld-m68k/m68k.exp: Run the new tests.
2020-06-26 14:42:19 +09:30
Cui,Lili
708a2ffff5 x86: Correct noavx512_vp2intersect
* config/tc-i386.c (cpu_arch): Correct noavx512_vp2intersect
	cpu_arch to CPU_ANY_VP2INTERSECT_FLAGS.
	* doc/c-i386.texi: Add avx512_vp2intersect.
2020-06-16 10:07:15 -07:00
Max Filippov
7a77f1ac2c xtensa: allow runtime ABI selection
2020-06-15  Max Filippov  <jcmvbkbc@gmail.com>
bfd/
	* elf32-xtensa.c (XSHAL_ABI, XTHAL_ABI_UNDEFINED)
	(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros.
	(elf32xtensa_abi): New global variable.
	(xtensa_abi_choice): New function.
	(elf_xtensa_create_plt_entry): Use xtensa_abi_choice instead of
	XSHAL_ABI to select PLT code.

gas/
	* config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
	macros.
	(elf32xtensa_abi): New declaration.
	(option_abi_windowed, option_abi_call0): New enum constants.
	(md_longopts): Add entries for --abi-windowed and --abi-call0.
	(md_parse_option): Add handlers for --abi-windowed and
	--abi-call0.
	(xtensa_add_config_info): Use xtensa_abi_choice instead of
	XSHAL_ABI to format ABI tag.
	* doc/as.texi (Target Xtensa options): Add --abi-windowed and
	--abi-call0 to the list of options.
	* doc/c-xtensa.texi: Add description for options --abi-windowed
	and --abi-call0.
	* testsuite/gas/xtensa/abi-call0.d: New test definition.
	* testsuite/gas/xtensa/abi-windowed.d: New test definition.
	* testsuite/gas/xtensa/abi.s: New test source.

include/
	* elf/xtensa.h (xtensa_abi_choice): New declaration.

ld/
	* emultempl/xtensaelf.em (XSHAL_ABI): Remove macro definition.
	(XTHAL_ABI_UNDEFINED, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
	macros.
	(elf32xtensa_abi): New declaration.
	(xt_config_info_unpack_and_check): Set elf32xtensa_abi if it is
	undefined.  Use xtensa_abi_choice instead of XSHAL_ABI to test
	ABI tag consistency.
	(xtensa_add_config_info): Use xtensa_abi_choice instead of
	XSHAL_ABI to format ABI tag.
	(PARSE_AND_LIST_PROLOGUE): Define OPTION_ABI_WINDOWED,
	OPTION_ABI_CALL0 and declare elf32xtensa_abi.
	(PARSE_AND_LIST_LONGOPTS): Add entries for --abi-windowed and
	--abi-call0.
	(PARSE_AND_LIST_OPTIONS): Add help text for --abi-windowed and
	--abi-call0.
	(PARSE_AND_LIST_ARGS_CASES): Add handlers for --abi-windowed and
	--abi-call0.
	* ld.texi: Add description for options --abi-windowed and
	--abi-call0.
2020-06-15 13:01:30 -07:00
Seth Girvan
18ca16bec8 [PATCH] gas/doc: improve AVR modifiers wording.
* doc/c-avr.texi: Improve wording.
2020-06-09 11:13:39 +01:00
Alan Modra
1424c35d07 Power10 tidies
binutils/
	* doc/binutils.texi (PowerPC -M option): Mention power10 and pwr10.
gas/
	* config/tc-ppc.c (md_show_usage): Mention -mpower10 and -mpwr10.
	* doc/c-ppc.texi: Likewise.
opcodes/
	* ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
2020-06-06 14:44:32 +09:30
Stephen Casner
338d56a848 * gas/doc/c-riscv.texi (RISC-V-Options): Fix non-ASCII apostrophe. 2020-06-03 13:42:54 -07:00
Jim Wilson
bb7322c671 RISC-V: Fix minor bugs in .insn docs.
This fixes some minor bugs in the docs for the .insn directive pointed out
by Frédéric Pétrot, and I added a few more cleanups since I was changing
the docs.

	gas/
	PR 26051
	* doc/c-riscv.texi (RISC-V-Formats): Add missing I format using
	simm12(rs1).  Correct S format to use simm12(rs1).  Drop SB and B
	formats using simm12(rs1).  Correct SB and B to use rs1 and rs2.
	Move B before SB.  Move J before UJ.
2020-06-02 18:37:09 -07:00
Nelson Chu
8f595e9b4f [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.

2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.

3. Spilt the patches to reduce the burdens of review.

[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.

[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.

4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.

include	* opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
	(enum riscv_isa_spec_class): New enum class.  All supported ISA spec
	belong to one of the class
	(struct riscv_ext_version): New structure holds version information
	for the specific ISA.
	* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
	define_version and abort_version.  The define_version means which
	privilege spec is started to define the CSR, and the abort_version
	means which privilege spec is started to abort the CSR.  If the CSR is
	valid for the newest spec, then the abort_version should be
	PRIV_SPEC_CLASS_DRAFT.
	(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
	* opcode/riscv.h (enum riscv_priv_spec_class): New enum class.  Define
	the current supported privilege spec versions.
	(struct riscv_csr_extra): Add new fields to store more information
	about the CSR.  We use these information to find the suitable CSR
	address when user choosing a specific privilege spec.

binutils * dwarf.c: Updated since DECLARE_CSR is changed.

opcodes	* riscv-opc.c (riscv_ext_version_table): The table used to store
	all information about the supported spec and the corresponding ISA
	versions.  Currently, only Zicsr is supported to verify the
	correctness of Z sub extension settings.  Others will be supported
	in the future patches.
	(struct isa_spec_t, isa_specs): List for all supported ISA spec
	classes and the corresponding strings.
	(riscv_get_isa_spec_class): New function.  Get the corresponding ISA
	spec class by giving a ISA spec string.
	* riscv-opc.c (struct priv_spec_t): New structure.
	(struct priv_spec_t priv_specs): List for all supported privilege spec
	classes and the corresponding strings.
	(riscv_get_priv_spec_class): New function.  Get the corresponding
	privilege spec class by giving a spec string.
	(riscv_get_priv_spec_name): New function.  Get the corresponding
	privilege spec string by giving a CSR version class.
	* riscv-dis.c: Updated since DECLARE_CSR is changed.
	* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
	according to the chosen version.  Build a hash table riscv_csr_hash to
	store the valid CSR for the chosen pirv verison.  Dump the direct
	CSR address rather than it's name if it is invalid.
	(parse_riscv_dis_option_without_args): New function.  Parse the options
	without arguments.
	(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
	parse the options without arguments first, and then handle the options
	with arguments.  Add the new option -Mpriv-spec, which has argument.
	* riscv-dis.c (print_riscv_disassembler_options): Add description
	about the new OBJDUMP option.

ld	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
        priv attributes according to the -mpriv-spec option.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.

bfd 	* elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
	get_default_version.  It is used to find the default version for
	the specific extension.
	* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
	default_major_version and default_minor_version.  Add new bfd_boolean
	parameter *use_default_version.  Set it to TRUE if we need to call
	the callback rps->get_default_version to find the default version.
	(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
	the default version in riscv_parsing_subset_version, and then call
	riscv_add_subset to add the subset into subset list.
	(riscv_parse_prefixed_ext): Likewise.
	(riscv_std_z_ext_strtab): Support Zicsr extensions.
	* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
	strings rather than characters.
	riscv_merge_arch_attr_info): The callback function get_default_version
	is only needed for assembler, so set it to NULL int the linker.
	* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
	* elfxx-riscv.h: Updated.

gas	* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
	* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
	Static variables which are used to set the ISA extensions. You can
	use -march (or ELF build attributes) and -misa-spec to set them,
	respectively.
	(ext_version_hash): The hash table used to handle the extensions
	with versions.
	(init_ext_version_hash): Initialize the ext_version_hash according
	to riscv_ext_version_table.
	(riscv_get_default_ext_version): The callback function of
	riscv_parse_subset_t.  According to the choosed ISA spec,
	get the default version for the specific extension.
	(riscv_set_arch): Set the callback function.
	(enum options, struct option md_longopts): Add new option -misa-spec.
	(md_parse_option): Do not call riscv_set_arch for -march.  We will
	call it later in riscv_after_parse_args.  Call riscv_get_isa_spec_class
	to set default_isa_spec class.
	(riscv_after_parse_args): Call init_ext_version_hash to initialize the
	ext_version_hash, and then call riscv_set_arch to set the architecture
	with versions according to default_arch_with_ext.
	* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
	x extensions.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: New testcase.  For i-ext, we
	already set it's version to 2p1 by march, so no need to use the default
	2p2 version.  For m-ext, we do not set the version by -march and ELF arch
	attribute, so set the default 2p0 to it.  For zicsr, it is not defined in
	ISA spec 2p2, so set 0p0 to it.
	* testsuite/gas/riscv/attribute-10.d: New testcase.  The version of
	zicsr is 2p0 according to ISA spec 20191213.
	* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
	(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
	You can set them by configure options --with-arch and
	--with-isa-spec, respectively.
	(riscv_set_default_isa_spec): New function used to set the
	default ISA spec.
	(md_parse_option): Call riscv_set_default_isa_spec rather than
	call riscv_get_isa_spec_class directly.
	(riscv_after_parse_args): If the -isa-spec is not set, then we
	set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
	calling riscv_set_default_isa_spec.
	* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
	the --with-isa-spec may be set to different ISA spec.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* configure.ac: Add configure options, --with-arch and
	--with-isa-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (default_priv_spec): Static variable which is
	used to check if the CSR is valid for the chosen privilege spec. You
	can use -mpriv-spec to set it.
	(enum reg_class): We now get the CSR address from csr_extra_hash rather
	than reg_names_hash.  Therefore, move RCLASS_CSR behind RCLASS_MAX.
	(riscv_init_csr_hashes): Only need to initialize one hash table
	csr_extra_hash.
	(riscv_csr_class_check): Change the return type to void.  Don't check
	the ISA dependency if -mcsr-check isn't set.
	(riscv_csr_version_check): New function.  Check and find the CSR address
	from csr_extra_hash, according to default_priv_spec.  Report warning
	for the invalid CSR if -mcsr-check is set.
	(reg_csr_lookup_internal): Updated.
	(reg_lookup_internal): Likewise.
	(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
	(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
	(md_parse_option): Call riscv_set_default_priv_version to set
	default_priv_spec.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
	privilege spec to the newest one.
	(enum riscv_csr_class, struct riscv_csr_extra): Move them to
	include/opcode/riscv.h.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
	to check the ISA dependency for CSR, so fix the spec version by adding
	-mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.  There are some
	version warnings for the test case.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
	Check whether the CSR is valid when privilege version 1.9 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
	Check whether the CSR is valid when privilege version 1.9.1 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
	Check whether the CSR is valid when privilege version 1.10 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
	Check whether the CSR is valid when privilege version 1.11 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
	setting.  You can set it by configure option --with-priv-spec.
	(riscv_set_default_priv_spec): New function used to set the default
	privilege spec.
	(md_parse_option): Call riscv_set_default_priv_spec rather than
	call riscv_get_priv_spec_class directly.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
	default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
	calling riscv_set_default_priv_spec.
	* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
	the --with-priv-spec may be set to different privilege spec.
	* testsuite/gas/riscv/priv-reg.d: Likewise.
	* configure.ac: Add configure option --with-priv-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
	explicit_attr.  Set it to TRUE if any ELF attribute is found.
	(riscv_set_default_priv_spec): Try to set the default_priv_spec if
	the priv attributes are set.
	(md_assemble): Set the default_priv_spec according to the priv
	attributes when we start to assemble instruction.
	(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
	riscv_write_out_attrs.  Update the arch and priv attributes.  If we
	don't set the corresponding ELF attributes, then try to output the
	default ones.
	(riscv_set_public_attributes): If any ELF attribute or -march-attr
	options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
	to update the arch and priv attributes.
	(s_riscv_attribute): Make sure all arch and priv attributes are set
	before any instruction.
	* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
	ELF attribute or -march-attr is set.  If the priv attributes are not
	set, then try to update them by the default setting (-mpriv-spec or
	--with-priv-spec).
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.  Also, the priv spec
	set by priv attributes must be supported.
	* testsuite/gas/riscv/attribute-05.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise.  Updated
	priv attributes according to the -mpriv-spec option.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg.d: Removed.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case.  Dump the
	CSR according to the priv spec 1.9.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case.  Dump the
	CSR according to the priv spec 1.9.1.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case.  Dump the
	CSR according to the priv spec 1.10.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case.  Dump the
	CSR according to the priv spec 1.11.
	* config/tc-riscv.c (md_show_usage): Add descriptions about
	the new GAS options.
	* doc/c-riscv.texi: Likewise.
2020-05-20 17:22:48 +01:00
Nick Clifton
6ef719c016 Section "3.1 Preprocessing" of the online GAS manual has a wrong reference to "Using GNU CC". This fixes that link.
PR 25927
	* doc/as.texi (Preprocessing): Replace cross reference to not
	existant document with a URL to the equivalent page in the GCC
	manual.
2020-05-06 13:21:02 +01:00
Tamar Christina
251dae9107 x86: Add i386 PE big-object support
The 64-bit version of binutils got support for the PE COFF BIG OBJ format a
couple of years ago.   The BIG OBJ format is a slightly different COFF format
which extends the size of the number of section field in the header from a
uint16_t to a uint32_t and so greatly increases the number of sections allowed.

However the 32-bit version of bfd never got support for this.  The GHC Haskell
compiler generates a great deal of symbols due to it's use of
-ffunction-sections and -fdata-sections.

This meant that we could not build the 32-bit version of the GHC Compiler for
many releases now as binutils didn't have this support.

This patch adds the support to the 32-bit port of binutils as well and also does
come cleanup in the code.

bfd/ChangeLog:

	* coff-i386.c (COFF_WITH_PE_BIGOBJ): New.
	* coff-x86_64.c (COFF_WITH_PE_BIGOBJ): New.
	* config.bfd (targ_selvecs): Rename x86_64_pe_be_vec
	to x86_64_pe_big_vec as it not a big-endian format.
	(vec i386_pe_big_vec): New.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* configure: Regenerate.
	* pe-i386.c (TARGET_SYM_BIG, TARGET_NAME_BIG,
	COFF_WITH_PE_BIGOBJ): New.
	* pe-x86_64.c (TARGET_SYM_BIG, TARGET_NAME_BIG):
	New.
	(x86_64_pe_be_vec): Moved.

gas/ChangeLog:

	* NEWS: Add news entry for big-obj.
	* config/tc-i386.c (i386_target_format): Support new format.
	* doc/c-i386.texi: Add i386 support.
	* testsuite/gas/pe/big-obj.d: Rename test to not be x64 specific.
	* testsuite/gas/pe/pe.exp (big-obj): Make test run on i386 as well.

ld/ChangeLog:

	* pe-dll.c (pe_detail_list):  Add pe-bigobj-i386.
2020-04-27 17:41:39 +01:00
liuhongt
a09f656b26 Improve -mlfence-after-load
1.Implict load for POP/POPF/POPA/XLATB, no load for Anysize insns
  2. Add -mlfence-before-ret=shl/yes, adjust operand size of
  or/not/shl according to ret's.
  3. Issue warning for REP CMPS/SCAS since they would affect control
  flow behavior.
  4. Adjust testcases and documents.

gas/Changelog:
	* config/tc-i386.c (lfence_before_ret_shl): New member.
	(load_insn_p): implict load for POP/POPA/POPF/XLATB, no load
	for Anysize insns.
	(insert_after_load): Issue warning for REP CMPS/SCAS.
	(insert_before_before): Handle iret, Handle
	-mlfence-before-ret=shl, Adjust operand size of or/not/shl to ret's,
	(md_parse_option): Change -mlfence-before-ret=[none|not|or] to
	-mlfence-before-ret=[none/not/or/shl/yes].
	Enable -mlfence-before-ret=shl when
	-mlfence-beofre-indirect-branch=all and no explict -mlfence-before-ret option.
	(md_show_usage): Ditto.
	* doc/c-i386.texi: Ditto.
	* testsuite/gas/i386/i386.exp: Add new testcases.
	* testsuite/gas/i386/lfence-load-b.d: New.
	* testsuite/gas/i386/lfence-load-b.e: New.
	* testsuite/gas/i386/lfence-load.d: Modified.
	* testsuite/gas/i386/lfence-load.e: New.
	* testsuite/gas/i386/lfence-load.s: Modified.
	* testsuite/gas/i386/lfence-ret-a.d: Modified.
	* testsuite/gas/i386/lfence-ret-b.d: Modified.
	* testsuite/gas/i386/lfence-ret-c.d: New.
	* testsuite/gas/i386/lfence-ret-d.d: New.
	* testsuite/gas/i386/lfence-ret.s: Modified.
	* testsuite/gas/i386/x86-64-lfence-load-b.d: New.
	* testsuite/gas/i386/x86-64-lfence-load.d: Modified.
	* testsuite/gas/i386/x86-64-lfence-load.s: Modified.
	* testsuite/gas/i386/x86-64-lfence-ret-a.d: Modified.
	* testsuite/gas/i386/x86-64-lfence-ret-b.d: Modified.
	* testsuite/gas/i386/x86-64-lfence-ret-c.d: New.
	* testsuite/gas/i386/x86-64-lfence-ret-d.d: New
	* testsuite/gas/i386/x86-64-lfence-ret-e.d: New.
	* testsuite/gas/i386/x86-64-lfence-ret.e: New.
	* testsuite/gas/i386/x86-64-lfence-ret.s: New.
2020-04-26 14:26:24 +08:00
Alan Modra
31c89d6038 .symver fixes
* config/obj-elf.c (elf_frob_symbol): Unconditionally remove
	symbol for ".symver .. remove".
	* doc/as.texi (.symver): Update.
	* testsuite/gas/symver/symver11.s: Make foo weak.
	* testsuite/gas/symver/symver11.d: Expect an error.
	* testsuite/gas/symver/symver7.d: Allow other random symbols.
2020-04-22 22:24:03 +09:30
H.J. Lu
6914be53bd gas: Extend .symver directive
Extend .symver directive to update visibility of the original symbol and
assign one original symbol to different versioned symbols:

  .symver foo, foo@VERS_1, local    # Change foo to a local symbol.
  .symver foo, foo@VERS_2, hidden   # Change foo to a hidden symbol.
  .symver foo, foo@@VERS_3, remove  # Remove foo from symbol table.
  .symver foo, bar@V1               # Assign foo to bar@V1 and baz@V2.
  .symver foo, baz@V2

	PR gas/23840
	PR gas/25295
	* NEWS: Mention .symver extension.
	* config/obj-elf.c (obj_elf_find_and_add_versioned_name): New
	function.
	(obj_elf_symver): Call obj_elf_find_and_add_versioned_name to
	add a version name.  Add local, hidden and remove visibility
	support.
	(elf_frob_symbol): Handle the list of version names.  Update the
	original symbol to local, hidden or remove it from the symbol
	table.
	(elf_frob_file_before_adjust): Handle the list of version names.
	* config/obj-elf.h (elf_visibility): New.
	(elf_versioned_name_list): Likewise.
	(elf_obj_sy): Change local to bitfield. Add rename, bad_version
	and visibility.  Change versioned_name pointer to struct
	elf_versioned_name_list.
	* doc/as.texi: Update .symver directive.
	* testsuite/gas/symver/symver.exp: Run all *.d tests.  Add more
	error checking tests.
	* testsuite/gas/symver/symver6.d: New file.
	* testsuite/gas/symver/symver7.d: Likewise.
	* testsuite/gas/symver/symver7.s: Likewise.
	* testsuite/gas/symver/symver8.d: Likewise.
	* testsuite/gas/symver/symver8.s: Likewise.
	* testsuite/gas/symver/symver9.s: Likewise.
	* testsuite/gas/symver/symver9a.d: Likewise.
	* testsuite/gas/symver/symver9b.d: Likewise.
	* testsuite/gas/symver/symver10.s: Likewise.
	* testsuite/gas/symver/symver10a.d: Likewise.
	* testsuite/gas/symver/symver10b.d: Likewise.
	* testsuite/gas/symver/symver11.d: Likewise.
	* testsuite/gas/symver/symver11.s: Likewise.
	* testsuite/gas/symver/symver12.d: Likewise.
	* testsuite/gas/symver/symver12.s: Likewise.
	* testsuite/gas/symver/symver13.d: Likewise.
	* testsuite/gas/symver/symver13.s: Likewise.
	* testsuite/gas/symver/symver14.d: Likewise.
	* testsuite/gas/symver/symver14.l: Likewise.
	* testsuite/gas/symver/symver15.d: Likewise.
	* testsuite/gas/symver/symver15.l: Likewise.
	* testsuite/gas/symver/symver6.l: Removed.
	* testsuite/gas/symver/symver6.s: Updated.
2020-04-21 05:33:17 -07:00
H.J. Lu
3071b197da x86: Correct -mlfence-before-indirect-branch= documentation
Replace "after indirect near branch" with "before indirect near branch".

	* doc/c-i386.texi: Correct -mlfence-before-indirect-branch=
	documentation.
2020-04-08 19:31:45 -07:00
H.J. Lu
266803a291 gas/doc/c-z80.texi: Fix @xref warnings
Fix

gas/doc/c-z80.texi:244: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:278: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:284: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:291: warning: `.' or `,' must follow @xref, not )
gas/doc/c-z80.texi:295: warning: `.' or `,' must follow @xref, not )

	* doc/c-z80.texi: Fix @xref warnings.
2020-04-07 04:21:41 -07:00
Cui,Lili
bb651e8b7f Add support for intel TSXLDTRK instructions$
gas/

	* config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document TSXLDTRK.
	* testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
	* testsuite/gas/i386/tsxldtrk.d: Likewise.
	* testsuite/gas/i386/tsxldtrk.s: Likewise.
	* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
	(prefix_table): New instructions (see prefixes above).
	(rm_table): Likewise.
	* i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
	CPU_ANY_TSXLDTRK_FLAGS.
	(cpu_flags): Add CpuTSXLDTRK.
	* i386-opc.h (enum): Add CpuTSXLDTRK.
	(i386_cpu_flags): Add cputsxldtrk.
	* i386-opc.tbl: Add XSUSPLDTRK insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
2020-04-07 13:59:50 +08:00
LiliCui
4b27d27c07 Add support for intel SERIALIZE instruction
gas/

	* config/tc-i386.c (cpu_arch): Add .serialize.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document serialize.
	* testsuite/gas/i386/i386.exp: Run serialize tests
	* testsuite/gas/i386/serialize.d: Likewise.
	* testsuite/gas/i386/x86-64-serialize.d: Likewise.
	* testsuite/gas/i386/serialize.s: Likewise.

opcodes/

	* i386-dis.c (prefix_table): New instructions serialize.
	* i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
	CPU_ANY_SERIALIZE_FLAGS.
	(cpu_flags): Add CpuSERIALIZE.
	* i386-opc.h (enum): Add CpuSERIALIZE.
	(i386_cpu_flags): Add cpuserialize.
	* i386-opc.tbl: Add SERIALIZE insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
2020-04-02 05:48:36 -07:00
Sergey Belyashov
0d832e7f5e Add support for the xdef and xref pseudo-ops to the Z80 assembler.
PR 25690
	* config/tc-z80.c (md_pseudo_table): Add xdef anf xref pseudo ops.
	* doc/c-z80.texi: Update documentation.
2020-03-20 13:53:02 +00:00
H.J. Lu
ae531041c7 i386: Generate lfence with load/indirect branch/ret [CVE-2020-0551]
Add 3 command-line options to generate lfence for load, indirect near
branch and ret to help mitigate:

https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00334.html
http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-0551

1. -mlfence-after-load=[no|yes]:
  -mlfence-after-load=yes generates lfence after load instructions.
2. -mlfence-before-indirect-branch=[none|all|memory|register]:
  a. -mlfence-before-indirect-branch=all generates lfence before indirect
  near branches via register and a warning before indirect near branches
  via memory.
  b. -mlfence-before-indirect-branch=memory issue a warning before
  indirect near branches via memory.
  c. -mlfence-before-indirect-branch=register generates lfence before
  indirect near branches via register.
Note that lfence won't be generated before indirect near branches via
register with -mlfence-after-load=yes since lfence will be generated
after loading branch target register.
3. -mlfence-before-ret=[none|or|not]
  a. -mlfence-before-ret=or generates or with lfence before ret.
  b. -mlfence-before-ret=not generates not with lfence before ret.

A warning will be issued and lfence won't be generated before indirect
near branch and ret if the previous item is a prefix or a constant
directive, which may be used to hardcode an instruction, since there
is no clear instruction boundary.

	* config/tc-i386.c (lfence_after_load): New.
	(lfence_before_indirect_branch_kind): New.
	(lfence_before_indirect_branch): New.
	(lfence_before_ret_kind): New.
	(lfence_before_ret): New.
	(last_insn): New.
	(load_insn_p): New.
	(insert_lfence_after): New.
	(insert_lfence_before): New.
	(md_assemble): Call insert_lfence_before and insert_lfence_after.
	Set last_insn.
	(OPTION_MLFENCE_AFTER_LOAD): New.
	(OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH): New.
	(OPTION_MLFENCE_BEFORE_RET): New.
	(md_longopts): Add -mlfence-after-load=,
	-mlfence-before-indirect-branch= and -mlfence-before-ret=.
	(md_parse_option): Handle -mlfence-after-load=,
	-mlfence-before-indirect-branch= and -mlfence-before-ret=.
	(md_show_usage): Display -mlfence-after-load=,
	-mlfence-before-indirect-branch= and -mlfence-before-ret=.
	(i386_cons_align): New.
	* config/tc-i386.h (i386_cons_align): New.
	(md_cons_align): New.
	* doc/c-i386.texi: Document -mlfence-after-load=,
	-mlfence-before-indirect-branch= and -mlfence-before-ret=.
2020-03-11 09:46:19 -07:00
Nick Clifton
5496f3c635 Add support for generating DWARF-5 format directory and file name tables from the assembler.
PR 25611
	PR 25614
	* dwarf.h (DWARF2_Internal_LineInfo): Add li_address_size and
	li_segment_size fields.
	* dwarf.c (read_debug_line_header): Record the address size and
	segment selector size values (if present) in the lineinfo
	structure.
	(display_formatted_table): Warn if the format count is empty but
	the table itself is not empty.
	Display the format count and entry count at the start of the table
	dump.
	(display_debug_lines_raw): Display the address size and segement
	selector size fields, if present.
	* testsuite/binutils-all/dw5.W: Update expected output.

gas	* dwarf2dbg.c (DWARF2_FILE_TIME_NAME): Default to -1.
	(DWARF2_FILE_SIZE_NAME): Default to -1.
	(DWARF2_LINE_VERSION): Default to the current dwarf level or 3,
	whichever is higher.
	(DWARF2_LINE_MAX_OPS_PER_INSN): Provide a default value of 1.
	(NUM_MD5_BYTES): Define.
	(struct file entry): Add md5 field.
	(get_filenum): Delete and replace with...
	(get_basename): New function.
	(get_directory_table_entry): New function.
	(allocate_filenum): New function.
	(allocate_filename_to_slot): New function.
	(dwarf2_where): Use new functions.
	(dwarf2_directive_filename): Add support for extended .file
	pseudo-op.
	(dwarf2_directive_loc): Allow the use of file number zero with
	DWARF 5 or higher.
	(out_file_list): Rename to...
	(out_dir_and_file_list): Add DWARF 5 support.
	(out_debug_line): Emit extra values into the section header for
	DWARF 5.
	(out_debug_str): Allow for file 0 to be used with DWARF 5.
	* doc/as.texi (.file): Update the description of this pseudo-op.
	* testsuite/gas/elf-dwarf-5-file0.s: Add more lines.
	* testsuite/gas/elf-dwarf-5-file0.d: Update expected dump output.
	* testsuite/gas/lns/lns-diag-1.l: Update expected error message.
	* NEWS: Mention the new feature.
2020-03-11 10:17:14 +00:00
Nick Clifton
84d9ab33f3 Add support for a ".file 0" directive if supporting DWARF 5 or higher.
PR 25614
	* dwarf2dbg.c (dwarf2_directive_filename): Allow a file number of
	0 if the dwarf_level is 5 or more.  Complain if a filename follows
	a file 0.
	* testsuite/gas/elf/dwarf-5-file0.s: New test.
	* testsuite/gas/elf/dwarf-5-file0.d: New test driver.
	* testsuite/gas/elf/elf.exp: Run the new test.

	PR 25612
	* config/tc-ia64.h (DWARF2_VERISION): Fix typo.
	* doc/as.texi: Fix another typo.
2020-03-06 17:13:22 +00:00
Nick Clifton
31bf18645d Add support for --dwarf-[3|4|5] to assembler command line.
PR 25612
	* as.c (dwarf_level): Define.
	(show_usage): Add --gdwarf-3, --gdwarf-4 and --gdwarf-5.
	(parse_args): Add support for the new options.
	as.h (dwarf_level): Prototype.
	* dwarf2dbg.c (DWARF2_VERSION): Use dwarf_level as default version
	value.
	* config/tc-ia64.h (DWARF2_VERISION): Update definition.
	(DWARF2_LINE_VERSION): Remove definition.
	* doc/as.texi: Document the new options.
2020-03-06 14:52:14 +00:00
Nelson Chu
dee35d026c RISC-V: Support assembler modifier %got_pcrel_hi.
gas/
	* config/tc-riscv.c: Support the modifier %got_pcrel_hi.
	* doc/c-riscv.texi: Add documentation.
	* testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
	modifier %got_pcrel_hi.
	* testsuite/gas/riscv/no-relax-reloc.s: Likewise.
	* testsuite/gas/riscv/relax-reloc.d: Likewise.
	* testsuite/gas/riscv/relax-reloc.s: Likewise.
2020-03-04 17:11:37 -08:00
Nelson Chu
de48783e2f RISC-V: Add description for RISC-V Modifiers to as doc.
gas/
	* doc/c-riscv.texi (relocation modifiers): Add documentation.
	(RISC-V-Formats): Update the section name from "Instruction Formats"
	to "RISC-V Instruction Formats".
2020-03-04 17:11:37 -08:00
Jan Beulich
a847e32224 x86: support VMGEXIT
It has been publicly documented for quite some time, albeit not in the
"General-Purpose and System Instructions" volume:
https://www.amd.com/system/files/TechDocs/24593.pdf.
2020-03-04 08:58:13 +01:00
Nelson Chu
2ca89224b1 RISC-V: Disable the CSR checking by default.
Add new .option `csr-check/no-csr-check` and GAS option `-mcsr-check
/-mno-csr-check` to enbale/disable the CSR checking.  Disable the CSR
checking by default.

	gas/
	* config/tc-riscv.c: Add new .option and GAS options to enbale/disable
	the CSR checking.  We disable the CSR checking by default.
	(reg_lookup_internal): Check the `riscv_opts.csr_check`
	before we doing the CSR checking.

	* doc/c-riscv.texi: Add description for the new .option and assembler
	options.

	* testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable
	the CSR checking.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
2020-02-20 16:49:09 -08:00
Nelson Chu
bd3380bcdd RISC-V: Add description for -march-attr/-mno-arch-attr options in gas doc.
gas/
	* doc/c-riscv.texi: Add the doc entries for -march-attr/
	-mno-arch-attr command line options.
2020-02-19 17:18:25 -08:00
Sergey Belyashov
fcaaac0a0d Various fixes for the Z80 support.
PR 25537
ld	* emultempl/z80.em: Remove machine compatability checking.

	PR 25517
	* testsuite/ld-z80/arch_ez80_adl.d: Update command line.
	* testsuite/ld-z80/arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/arch_r800.d: Likewise.
	* testsuite/ld-z80/arch_z180.d: Likewise.
	* testsuite/ld-z80/arch_z80n.d: Likewise.
	* testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z180_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z80_ez80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z80_z180.d: Likewise.
	* testsuite/ld-z80/comb_arch_z80_z80n.d: Likewise.
	* testsuite/ld-z80/relocs_b_ez80.d: Likewise.
	* testsuite/ld-z80/relocs_b_z80.d: Likewise.
	* testsuite/ld-z80/relocs_f_ez80.d: Likewise.
	* testsuite/ld-z80/relocs_f_z80.d: Likewise.
	* testsuite/ld-z80/relocs_f_z80n.d: Likewise.

bfd
	* cpu-z80.c: Add machine type compatibility checking.

gas
	* config/tc-z80.c (md_parse_option): Do not use an underscore
	prefix for local labels in SDCC compatability mode.
	(z80_start_line_hook): Remove SDCC dollar label support.
	* testsuite/gas/z80/sdcc.d: Update expected disassembly.
	* testsuite/gas/z80/sdcc.s: Likewise.

	* config/tc-z80.c: Add -march option.
	* doc/as.texi: Update Z80 documentation.
	* doc/c-z80.texi: Likewise.
	* testsuite/gas/z80/ez80_adl_all.d: Update command line.
	* testsuite/gas/z80/ez80_adl_suf.d: Likewise.
	* testsuite/gas/z80/ez80_pref_dis.d: Likewise.
	* testsuite/gas/z80/ez80_z80_all.d: Likewise.
	* testsuite/gas/z80/ez80_z80_suf.d: Likewise.
	* testsuite/gas/z80/gbz80_all.d: Likewise.
	* testsuite/gas/z80/r800_extra.d: Likewise.
	* testsuite/gas/z80/r800_ii8.d: Likewise.
	* testsuite/gas/z80/r800_z80_doc.d: Likewise.
	* testsuite/gas/z80/sdcc.d: Likewise.
	* testsuite/gas/z80/z180.d: Likewise.
	* testsuite/gas/z80/z180_z80_doc.d: Likewise.
	* testsuite/gas/z80/z80_doc.d: Likewise.
	* testsuite/gas/z80/z80_ii8.d: Likewise.
	* testsuite/gas/z80/z80_in_f_c.d: Likewise.
	* testsuite/gas/z80/z80_op_ii_ld.d: Likewise.
	* testsuite/gas/z80/z80_out_c_0.d: Likewise.
	* testsuite/gas/z80/z80_sli.d: Likewise.
	* testsuite/gas/z80/z80n_all.d: Likewise.
	* testsuite/gas/z80/z80n_reloc.d: Likewise.
2020-02-19 17:46:10 +00:00
H.J. Lu
272a84b120 x86: Remove CpuABM and add CpuPOPCNT
AMD ABM has 2 instructions: popcnt and lzcnt.  ABM CPUID feature bit has
been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt
which used to be the part of SSE4.2.  This patch removes CpuABM and adds
CpuPOPCNT.  It changes ABM to enable both lzcnt and popcnt, changes SSE4.2
to also enable popcnt.

gas/

	* config/tc-i386.c (cpu_arch): Add .popcnt.
	* doc/c-i386.texi: Remove abm and .abm.  Add popcnt and .popcnt.
	Add a tab before @samp{.sse4a}.

opcodes/

	* i386-gen.c (cpu_flag_init): Replace CpuABM with
	CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
	CPU_POPCNT_FLAGS.
	(cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
	* i386-opc.h (CpuABM): Removed.
	(CpuPOPCNT): New.
	(i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
	* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
	popcnt.  Remove CpuABM from lzcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2020-02-17 07:31:28 -08:00
H.J. Lu
af5c13b01e x86: Don't disable SSE4a when disabling SSE4
commit 7deea9aad8 changed nosse4 to include CpuSSE4a.  But AMD SSE4a is
a superset of SSE3 and Intel SSE4 is a superset of SSSE3.  Disable Intel
SSE4 shouldn't disable AMD SSE4a.  This patch restores nosse4.  It also
adds .sse4a and nosse4a.

gas/

	* config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a.  Restore
	nosse4.
	* doc/c-i386.texi: Document sse4a and nosse4a.

opcodes/

	* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
	CPU_ANY_SSE4_FLAGS.
2020-02-16 08:45:34 -08:00
H.J. Lu
07d9838745 Remove the old movsx and movzx documentation for AT&T syntax
* doc/c-i386.texi: Remove the old movsx and movzx documentation
	for AT&T syntax.
2020-02-14 06:09:28 -08:00
H.J. Lu
0e6724dee4 x86: Document movsx/movsxd/movzx for AT&T syntax
Document different mnemonics of movsx, movsxd and movzx in AT&T syntax.

	PR gas/25438
	* doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T
	syntax.
2020-02-14 04:57:16 -08:00
Jan Beulich
5990e377e5 x86-64: Intel64 adjustments for insns dealing with far pointers
AMD and Intel differ in their handling of far indirect branches as well
as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
how the latter three were hybrids so far, while far branches were fully
AMD-like.)
2020-02-12 16:19:03 +01:00
Matthew Malcomson
4934a27c8c [binutils][arm] arm support for ARMv8.m Custom Datapath Extension
This patch is part of a series that adds support for the Armv8.m
ARMv8.m Custom Datapath Extension to binutils.

This patch introduces the Custom Instructions Class 1/2/3 (Single/
Dual, Accumulator/Non-accumulator varianats) to the arm backend.

The following Custom Instructions are added: cx1, cx1a,
cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da.

Specification can be found at
https://developer.arm.com/docs/ddi0607/latest

This patch distinguishes between enabling CDE for different coprocessor
numbers by defining multiple architecture flags.  This means that the
parsing of the architecture extension flags is kept entirely in the
existing code path.

We introduce a new IT block state to indicate the behaviour of these
instructions.  This new state allows being used in an IT block or
outside an IT block, but does not allow the instruction to be used
inside a VPT block.
We need this since the CX*A instruction versions can be used in IT
blocks, but they aren't to have the conditional suffixes on them.  Hence
we need to mark an instruction as allowed in either position.

We also need a new flag to objdump, in order to determine whether to
disassemble an instruction as CDE related or not.

Successfully regression tested on arm-none-eabi, and arm-wince-pe.

gas/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-arm.c (arm_ext_cde*): New feature sets for each
	CDE coprocessor that can be enabled.
	(enum pred_instruction_type): New pred type.
	(BAD_NO_VPT): New error message.
	(BAD_CDE): New error message.
	(BAD_CDE_COPROC): New error message.
	(enum operand_parse_code): Add new immediate operands.
	(parse_operands): Account for new immediate operands.
	(check_cde_operand): New.
	(cde_coproc_enabled): New.
	(cde_coproc_pos): New.
	(cde_handle_coproc): New.
	(cxn_handle_predication): New.
	(do_custom_instruction_1): New.
	(do_custom_instruction_2): New.
	(do_custom_instruction_3): New.
	(do_cx1): New.
	(do_cx1a): New.
	(do_cx1d): New.
	(do_cx1da): New.
	(do_cx2): New.
	(do_cx2a): New.
	(do_cx2d): New.
	(do_cx2da): New.
	(do_cx3): New.
	(do_cx3a): New.
	(do_cx3d): New.
	(do_cx3da): New.
	(handle_pred_state): Define new IT block behaviour.
	(insns): Add newn CX*{,d}{,a} instructions.
	(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
	Define new cdecp extension strings.
	* doc/c-arm.texi: Document new cdecp extension arguments.
	* testsuite/gas/arm/cde-scalar.d: New test.
	* testsuite/gas/arm/cde-scalar.s: New test.
	* testsuite/gas/arm/cde-warnings.d: New test.
	* testsuite/gas/arm/cde-warnings.l: New test.
	* testsuite/gas/arm/cde-warnings.s: New test.
	* testsuite/gas/arm/cde.d: New test.
	* testsuite/gas/arm/cde.s: New test.

include/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/arm.h (ARM_EXT2_CDE): New extension macro.
	(ARM_EXT2_CDE0): New extension macro.
	(ARM_EXT2_CDE1): New extension macro.
	(ARM_EXT2_CDE2): New extension macro.
	(ARM_EXT2_CDE3): New extension macro.
	(ARM_EXT2_CDE4): New extension macro.
	(ARM_EXT2_CDE5): New extension macro.
	(ARM_EXT2_CDE6): New extension macro.
	(ARM_EXT2_CDE7): New extension macro.

opcodes/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (struct cdeopcode32): New.
	(CDE_OPCODE): New macro.
	(cde_opcodes): New disassembly table.
	(regnames): New option to table.
	(cde_coprocs): New global variable.
	(print_insn_cde): New
	(print_insn_thumb32): Use print_insn_cde.
	(parse_arm_disassembler_options): Parse coprocN args.
2020-02-10 16:50:14 +00:00
H.J. Lu
4b5aaf5f69 x86: Accept Intel64 only instruction by default
Commit d835a58baa disabled sysenter/sysenter in 64-bit mode by
default.  By default, assembler should accept common, Intel64 only
and AMD64 ISAs since there are no conflicts.

gas/

	PR gas/25516
	* config/tc-i386.c (intel64): Renamed to ...
	(isa64): This.
	(match_template): Accept Intel64 only instruction by default.
	(i386_displacement): Updated.
	(md_parse_option): Updated.
	* c-i386.texi: Update -mamd64/-mintel64 documentation.
	* testsuite/gas/i386/i386.exp: Run x86-64-sysenter.  Pass
	-mamd64 to x86-64-sysenter-amd.
	* testsuite/gas/i386/x86-64-sysenter.d: New file.

opcodes/

	PR gas/25516
	* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
	with ISA64.
	* i386-opc.h (AMD64): Removed.
	(Intel64): Likewose.
	(AMD64): New.
	(INTEL64): Likewise.
	(INTEL64ONLY): Likewise.
	(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
	* i386-opc.tbl (Amd64): New.
	(Intel64): Likewise.
	(Intel64Only): Likewise.
	Replace AMD64 with Amd64.  Update sysenter/sysenter with
	Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
	* i386-tbl.h: Regenerated.
2020-02-10 08:37:36 -08:00