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1214 Commits

Author SHA1 Message Date
Matthew Malcomson
3bd82c86f0 [binutils][aarch64] New iclass sve_size_hsd2. 
Add "sve_size_hsd2" iclass decode that uses the new FLD_SVE_size field
value to determine the variant of an instruction.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_hsd2 iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_hsd2 iclass decode.
	* aarch64-opc.c (fields): Handle SVE_size field.
	* aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 2019-05-09 10:29:16 +01:00
Matthew Malcomson
adccc50753 [binutils][aarch64] Introduce SVE_IMM_ROT3 operand. 
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate
operand encoded at bit position 10.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_IMM_ROT3.
	(aarch64_print_operand): Add printing for SVE_IMM_ROT3.
	(fields): Handle SVE_rot3 field.
	* aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 2019-05-09 10:29:15 +01:00
Matthew Malcomson
7ce2460a77 [binutils][aarch64] SVE2 feature extension flags. 
Include all feature flag macros.

The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.

Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.

Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c: Add command line architecture feature flags
	"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
	* doc/c-aarch64.texi: Document new architecture feature flags.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_SVE2
	AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
	AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
	feature macros.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-tbl.h
	(aarch64_feature_sve2, aarch64_feature_sve2aes,
	aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
	aarch64_feature_sve2bitperm): New feature sets.
	(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
	for feature set addresses.
	(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
	SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 2019-05-09 10:29:12 +01:00
Faraz Shahbazker
41cee0897b Add load-link, store-conditional paired EVA instructions 
Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1].  These instructions are optional within
the EVA ASE.  Their presence is indicated by the XNP bit in the
Config5 register.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
     Instruction Set Manual", Imagination Technologies Ltd., Document
     Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
     "Alphabetical List of Instructions", pp. 230-231, pp. 357-360.

gas/
	* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
	(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
	(mips_after_parse_args): Translate EVA to EVA_R6.
	* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
	* testsuite/gas/mips/eva.s: Likewise.
	* testsuite/gas/mips/ase-errors-1.l: Check errors for
	 new instructions.
	* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.

include/
	* opcode/mips.h (ASE_EVA_R6): New macro.
	(M_LLWPE_AB, M_SCWPE_AB): New enum values.

opcodes/
	* mips-dis.c (mips_calculate_combination_ases): Add ISA
	argument and set ASE_EVA_R6 appropriately.
	(set_default_mips_dis_options): Pass ISA to above.
	(parse_mips_dis_option): Likewise.
	* mips-opc.c (EVAR6): New macro.
	(mips_builtin_opcodes): Add llwpe, scwpe.

Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
 2019-05-06 06:43:32 -07:00
Sudakshina Das
b83b4b1382 [BINUTILS, AArch64] Enable Transactional Memory Extension 
This patch enables the new Transactional Memory Extension added recently
as part of Arm's new architecture technologies.

We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
   * tstart <Xt>
   * ttest <Xt>
   * tcommit
   * tcancel #<imm>
The ISA for the above can be found here:
https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order

*** gas/ChangeLog ***

2019-05-01  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_operands): Add case for
	AARCH64_OPND_TME_UIMM16.
	(aarch64_features): Add "tme".
	* doc/c-aarch64.texi: Document the same.
	* testsuite/gas/aarch64/tme-invalid.d: New test.
	* testsuite/gas/aarch64/tme-invalid.l: New test.
	* testsuite/gas/aarch64/tme-invalid.s: New test.
	* testsuite/gas/aarch64/tme.d: New test.
	* testsuite/gas/aarch64/tme.s: New test.

*** include/ChangeLog ***

2019-05-01  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_TME): New.
	(enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.

*** opcodes/ChangeLog ***

2019-05-01  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-opc.c (operand_general_constraint_met_p): Add case for
	AARCH64_OPND_TME_UIMM16.
	(aarch64_print_operand): Likewise.
	* aarch64-tbl.h (QL_IMM_NIL): New.
	(TME): New.
	(_TME_INSN): New.
	(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 2019-05-01 17:14:01 +01:00
Andrew Bennett
a45328b93b [MIPS] Add load-link, store-conditional paired instructions 
Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions
that were omitted from the initial spec.  These instructions
are optional in implementations but not associated with any
ASE or pseudo-ASE.  Their presence is indicated by the XNP bit
in the Config5 register.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
     Instruction Set Manual", Imagination Technologies Ltd., Document
     Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
     "Alphabetical List of Instructions", pp. 228-229, pp. 354-357.

[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
     Instruction Set Manual", Imagination Technologies Ltd., Document
     Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
     "Alphabetical List of Instructions", pp. 289-290 and pp. 458-460.

gas/
	* config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
	M_SCDP_AB>: New cases and expansions for paired instructions.
	* testsuite/gas/mips/llpscp-32.s: New test source.
	* testsuite/gas/mips/llpscp-64.s: Likewise.
	* testsuite/gas/mips/llpscp-32.d: New test.
	* testsuite/gas/mips/llpscp-64.d: Likewise.
	* testsuite/gas/mips/mips.exp: Run the new tests.
	* testsuite/gas/mips/r6.s: Add new instructions to test source.
	* testsuite/gas/mips/r6-64.s: Likewise.
	* testsuite/gas/mips/r6-64-n32.d: Check new instructions.
	* testsuite/gas/mips/r6-64-n64.d: Likewise.
	* testsuite/gas/mips/r6-n32.d: Likewise.
	* testsuite/gas/mips/r6-n64.d: Likwwise.
	* testsuite/gas/mips/r6.d: Likewise.

include/
	* opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
	(M_SCWP_AB, M_SCDP_AB): Likewise.

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 2019-04-26 18:28:05 -07:00
Maciej W. Rozycki
cd0923370b MIPS/include: opcode/mips.h: Update stale comment for CODE20 operand 
Complement commit 1586d91e32 ("/ 0 should send SIGFPE not SIGTRAP..."),
<https://sourceware.org/ml/binutils/2004-07/msg00260.html>, and update a
stale comment referring the 20-bit code field of the BREAK and SDBBP
instructions, by making it explicit that where permitted by choosing the
MIPS32 or a later ISA the whole field can now be set with a single
operand for the SDBBP instruction only.

	include/
	* opcode/mips.h: Update comment for MIPS32 CODE20 operand.
 2019-04-25 01:28:49 +01:00
Andre Vieira
1889da7048 [binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12 
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the BFCSEL instructions which is one of the first
instructions in Arm that have more than one relocations in them.

This adds a new relocation R_ARM_THM_BF12.

The inconsistency between external R_ARM_THM_BF12 and internal
BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the
immediate and we don't externally.

ChangeLog entries are as follows :

ChangeLog entries are as follows :

*** bfd/ChnageLog ***

2019-04-04  Sudakshina Das  <sudi.das@arm.com>

	* reloc.c (BFD_RELOC_ARM_THUMB_BF13): New.
	* bfd-in2.h: Regenerated.
	* libbfd.h: Regenerated.
	* elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13.
	(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13
	and R_ARM_THM_BF12 together.
	(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13.

*** elfcpp/ChangeLog ***

2019-04-04  Sudakshina Das  <sudi.das@arm.com>

	* arm.h (R_ARM_THM_BF12): New relocation code.

*** gas/ChangeLog ***

2019-04-04  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-arm.c (md_pcrel_from_section): New switch case for
	BFD_RELOC_ARM_THUMB_BF13.
	(md_appdy_fix): Likewise.
	(tc_gen_reloc): Likewise.

*** include/ChangeLog ***

2019-04-04  Sudakshina Das  <sudi.das@arm.com>

	* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.

*** opcodes/ChangeLog ***

2019-04-04  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 2019-04-15 12:31:34 +01:00
Andre Vieira
1caf72a584 [binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them.

This adds a new relocation R_ARM_THM_BF18.

The inconsistency between external R_ARM_THM_BF18 and internal
BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally.

ChangeLog entries are as follows :

*** bfd/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* reloc.c (BFD_RELOC_ARM_THUMB_BF19): New
	* libbfd.h: Regenerated.
	* bfd-in2.h: Regenerated.
	* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18.
	(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19
	and R_ARM_THM_BF18 together.
	(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19.

*** elfcpp/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm.h (R_ARM_THM_BF18): New relocation code.

*** gas/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-arm.c (md_pcrel_from_section): New switch case for
	BFD_RELOC_ARM_THUMB_BF19.
	(md_appdy_fix): Likewise.
	(tc_gen_reloc): Likewise.

*** include/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.

*** opcodes/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 2019-04-15 12:30:33 +01:00
Andre Vieira
e5d6e09ee6 [binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16 
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them.

This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16.

The inconsistency between external R_ARM_THM_BF16 and internal
BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally.

ChangeLog entries are as follows :

*** bfd/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
	* bfd-in2.h: Regenerated.
	* libbfd.h: Regenerated.
	* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16.
	(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17
	and R_ARM_THM_BF16 together.
	(get_value_helper): New reloc helper.
	(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16.

*** elfcpp/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm.h (R_ARM_THM_BF16): New relocation code.

*** gas/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-arm.c (md_pcrel_from_section): New switch case for
	BFD_RELOC_ARM_THUMB_BF17.
	(md_appdy_fix): Likewise.
	(tc_gen_reloc): Likewise.

*** include/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.

*** opcodes/ChangeLog ***

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 2019-04-15 12:30:33 +01:00
Andre Vieira
031254f211 [binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI 
The patch is straightforward, it does the following:

- support the new Tag_CPU_arch build attribute value, ie.:
   + declare the new value
   + update all the asserts forcing logic to be reviewed for new
     architectures
   + create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and
     add mapping from Tag_CPU_arch to it
   + teach readelf about new Tag_CPU_arch value
- declare armv8.1-m.main as a supported architecture value
- define Armv8.1-M Mainline in terms of feature bits available
- tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature
   bits available
- update architecture-specific logic in gas and bfd guarded by the
   asserts mentioned above.
- tests for all the above

ChangeLog entries are as follows:

*** bfd/ChangeLog ***

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* archures.c (bfd_mach_arm_8_1M_MAIN): Define.
	* bfd-in2.h: Regenerate.
	* cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline.
	* elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline
	and update assert.
	(using_thumb2): Likewise.
	(using_thumb2_bl): Update assert.
	(arch_has_arm_nop): Likewise.
	(bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline.
	(tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging.

*** binutils/ChangeLog ***

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline.

*** gas/ChangeLog ***

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
	Tag_CPU_arch build attribute value.  Reindent.
	(get_aeabi_cpu_arch_from_fset): Update assert.
	(aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
	* testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.

*** include/ChangeLog ***

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
	(MAX_TAG_CPU_ARCH): Set value to above macro.
	* opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
	(ARM_AEXT_V8_1M_MAIN): Likewise.
	(ARM_AEXT2_V8_1M_MAIN): Likewise.
	(ARM_ARCH_V8_1M_MAIN): Likewise.

*** ld/ChangeLog ***

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* testsuite/ld-arm/attr-merge-13.attr: New test.
	* testsuite/ld-arm/attr-merge-13a.s: New test.
	* testsuite/ld-arm/attr-merge-13b.s: New test.

*** opcodes/ChangeLog ***

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 2019-04-15 10:54:42 +01:00
Sudakshina Das
bd7ceb8d26 [BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions 
This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release

All of these instructions have an updated register operand (Xt -> <Xt|SP>)

- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>

In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has
the same field as FLD_Rt but follows other semantics of Rn_SP.

*** gas/ChangeLog ***

2019-04-11  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (process_omitted_operand): Add case for
	AARCH64_OPND_Rt_SP.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** include/ChangeLog ***

2019-04-11  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.

*** opcodes/ChangeLog ***

2019-04-11  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Add case for
	AARCH64_OPND_Rt_SP.
	(verify_constraints): Likewise.
	* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
	(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
	to accept Rt|SP as first operand.
	(AARCH64_OPERANDS): Add new Rt_SP.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
 2019-04-11 10:19:37 +01:00
H.J. Lu
462cac5884 x86: Define GNU_PROPERTY_X86_ISA_1_AVX512_BF16 
Update assembler and readelf to support

 #define GNU_PROPERTY_X86_ISA_1_AVX512_BF16  (1U << 24)

for AVX512_BF16.

binutils/

	* readelf.c (decode_x86_isa): Handle
	GNU_PROPERTY_X86_ISA_1_AVX512_BF16.
	* testsuite/binutils-all/i386/pr21231b.d: Updated.
	* testsuite/binutils-all/x86-64/pr21231b.d: Likewise.

gas/

	* config/tc-i386.c (output_insn): Support
	GNU_PROPERTY_X86_ISA_1_AVX512_BF16.
	* testsuite/gas/i386/property-2.s: Add AVX512_BF16 test.
	* testsuite/gas/i386/property-2.d: Updated.
	* testsuite/gas/i386/x86-64-property-2.d: Likewise.

include/

	* elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
 2019-04-08 17:04:16 -07:00
Alan Modra
07ffcfecac Merge libiberty from gcc 2019-04-07 20:49:49 +09:30
H.J. Lu
5b9c07b278 x86: Move x86-specific linker options to elf_linker_x86_params 
Remove x86-specific linker options from bfd_link_info and put them in
elf_linker_x86_params.  Add _bfd_elf_linker_x86_set_options to pass
x86-specific linker options from ld to bfd.

bfd/

	* elf-linker-x86.h: New file.
	* elf32-i386.c (elf_i386_convert_load_reloc): Use htab->params
	to get x86-specific linker options.
	* elf64-x86-64.c (elf_x86_64_convert_load_reloc): Likewise.
	(elf_x86_64_check_relocs): Likewise.
	(elf_x86_64_relocate_section): Likewise.
	(elf_x86_64_link_setup_gnu_properties): Likewise.
	* elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Likewise.
	(_bfd_x86_elf_link_setup_gnu_properties): Likewise.
	(_bfd_elf_linker_x86_set_options): New function.
	* elfxx-x86.h: Include "elf-linker-x86.h".
	(elf_x86_link_hash_table): Add params.

include/

	* bfdlink.h (bfd_link_info): Remove x86-specific linker options.

ld/

	* Makefile.am (ELF_X86_DEPS): Add $(srcdir)/emultempl/elf-x86.em.
	(eelf_i386_sol2.c): Also depend on
	$(srcdir)/emultempl/solaris2-x86.em.
	(eelf_x86_64_sol2.c): Likewise.
	* Makefile.in: Regenerated.
	* emulparams/call_nop.sh: Set x86-specific linker options via
	params.
	* emulparams/cet.sh: Likewise.
	* emulparams/reloc_overflow.sh: Likewise.
	* emulparams/elf32_x86_64.sh (EXTRA_EM_FILE): New.  Set to
	"elf-x86".
	* emulparams/elf_i386.sh: Likewise.
	* emulparams/elf_i386_be.sh: Likewise.
	* emulparams/elf_i386_chaos.sh: Likewise.
	* emulparams/elf_i386_ldso.sh: Likewise.
	* emulparams/elf_i386_vxworks.sh: Likewise.
	* emulparams/elf_iamcu.sh: Likewise.
	* emulparams/elf_k1om.sh: Likewise.
	* emulparams/elf_l1om.sh: Likewise.
	* emulparams/elf_x86_64.sh: Likewise.
	* emulparams/elf_i386_sol2.sh (EXTRA_EM_FILE): Changed to
	"solaris2-x86".
	* emulparams/elf_x86_64_sol2.sh: Likewise.
	* emultempl/elf-x86.em: New file.
	* emultempl/solaris2-x86.em: Likewise.
	* emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Don't
	set link_info.call_nop_byte.
 2019-04-06 07:25:31 -07:00
Andre Vieira
34ef62f465 [GAS, Arm] CLI with architecture sensitive extensions 
This patch adds a new framework to add architecture sensitive extensions, like
GCC does.  This patch also implements all architecture extensions currently
available in GCC.

This framework works as follows.  To enable architecture sensitive extensions
for a particular architecture, that architecture must contain an ARM_ARCH_OPT2
entry in the 'arm_archs' table.  All fields here are the same as previous, with
the addition of a new extra field at the end to <name> it's extension table.
This <name>, corresponds to a <name>_ext_table of type 'struct arm_ext_table'.
This struct can be filled with three types of entries:

  ARM_ADD (string <ext>, arm_feature_set <enable_bits>), which means +<ext> will
      enable <enable_bits>
  ARM_REMOVE (string <ext>, arm_feature_set <disable_bits>), which means
      +no<ext> will disable <disable_bits>
  ARM_EXT (string <ext>, arm_feature_set <enable_bits>, arm_feature_set
      <disable_bits>), which means +<ext> will enable <enable_bits> and +no<ext>
      will disable <disable_bits> (this is to be used instead of adding an
      ARM_ADD and ARM_REMOVE for the same <ext>)

This patch does not disable the use of the old extensions, even if some of them
are duplicated in the new tables.  This is a "in-between-step" as we may want to
deprecate the old table of extensions in later patches.  For now, GAS will first
look for the +<ext> or +no<ext> in the new table and if no entry is found it
will continue searching in the old table, following old behaviour.  If only an
ARM_ADD or an ARM_REMOVE is defined for <ext> and +no<ext> or +<ext> resp. is
used then it also continues to search the old table for it.

A couple of caveats:
- This patch does not enable the use of these architecture extensions with the
'.arch_extension' directive.  This is future work that I will tend to later.
- This patch does not enable the use of these architecture extensions with the
-mcpu option.  This is future work that I will tend to later.
- This patch does not change the current behaviour when combining an
architecture extension and using -mfpu on the command-line.  The current
behaviour of GAS is to stage the union of feature bits enabled by both -march
and -mfpu.  GCC behaves differently here, so this is something we may want to
revisit on a later date.
 2019-04-01 10:43:32 +01:00
Alan Modra
96a86c01d1 PR24390, Don't decode mtfsb field as a cr field 
"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately
glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit.
So for backwards compatibility accept cr field expressions when
assembling mtfsb operands, but disassemble to a plain number.

	PR 24390
include/
	* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
opcodes/
	* ppc-opc.c (BTF): Define.
	(powerpc_opcodes): Use for mtfsb*.
	* ppc-dis.c (print_insn_powerpc): Print fields with both
	PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
gas/
	* testsuite/gas/ppc/476.d: Update mtfsb*.
	* testsuite/gas/ppc/a2.d: Likewise.
 2019-03-28 15:21:05 +10:30
Tamar Christina
53b2f36bf6 AArch64: Fix disassembler bug with out-of-order sections 
The AArch64 disassembler has an optimization that it uses to reduce the amount
it has to search for mapping symbols during disassembly.  This optimization
assumes that sections are listed in the section header in monotonic increasing
VMAs.  However this is not a requirement for the ELF specification.

Because of this when such "out of order" sections occur the disassembler would
pick the wrong mapping symbol to disassemble the section with.

This fixes it by explicitly passing along the stop offset for the current
disassembly glob and when this changes compared to the previous one we've seen
the optimization won't be performed.  In effect this restarts the search from
a well defined starting point.  Usually the symbol's address.

The existing stop_vma can't be used for this as it is allowed to be unset and
setting this unconditionally would change the semantics of this field.

binutils/ChangeLog:

	* objdump.c (disassemble_bytes): Pass stop_offset.
	* testsuite/binutils-all/aarch64/out-of-order.T: New test.
	* testsuite/binutils-all/aarch64/out-of-order.d: New test.
	* testsuite/binutils-all/aarch64/out-of-order.s: New test.

include/ChangeLog:

	* dis-asm.h (struct disassemble_info): Add stop_offset.

opcodes/ChangeLog:

	* aarch64-dis.c (last_stop_offset): New.
	(print_insn_aarch64): Use stop_offset.
 2019-03-25 15:05:53 +00:00
Sudakshina Das
1dbade7441 [BFD, LD, AArch64, 3/3] Add --pac-plt to enable PLTs protected with PAC. 
This is part of the patch series to add support for BTI and
PAC in AArch64 linker.

1) This patch adds new definitions of PAC enabled PLTs
and both BTI and PAC enabled PLTs.
2) It also defines the new dynamic tag DT_AARCH64_PAC_PLT
for the PAC enabled PLTs.
3) This patch adds a new ld command line option: --pac-plt.
In the presence of this option, the linker uses the PAC
enabled PLTs and marks with DT_AARCH64_PAC_PLT.
4) In case both BTI and PAC are enabled the linker should
pick PLTs enabled with both and also use dynamic tags for both.
All these are made according to the new AArch64 ELF ABI
https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4

*** bfd/ChangeLog ***

2019-03-13  Sudakshina Das  <sudi.das@arm.com>

	* elfnn-aarch64.c (PLT_PAC_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): New.
	(PLT_BTI_PAC_ENTRY_SIZE, PLT_BTI_PAC_SMALL_ENTRY_SIZE): New.
	(setup_plt_values): Account for PAC or PAC and BTI enabled PLTs.
	(elfNN_aarch64_size_dynamic_sections): Add checks for PLT_BTI_PAC
	and PLT_PAC_PLT.
	(elfNN_aarch64_finish_dynamic_sections): Account for PLT_BTI_PAC.
	(get_plt_type): Add case for DT_AARCH64_PAC_PLT.
	(elfNN_aarch64_plt_sym_val): Add cases for PLT_BTI_PAC and PLT_PAC.

*** binutils/ChangeLog ***

2019-03-13  Sudakshina Das  <sudi.das@arm.com>

	* readelf.c (get_aarch64_dynamic_type): Add case for
	DT_AARCH64_PAC_PLT.
	(dynamic_section_aarch64_val): Likewise.

*** include/ChangeLog ***

2019-03-13  Sudakshina Das  <sudi.das@arm.com>

	* elf/aarch64.h (DT_AARCH64_PAC_PLT): New.

*** ld/ChangeLog ***

2019-03-13  Sudakshina Das  <sudi.das@arm.com>

	* NEWS: Document --pac-plt.
	* emultempl/aarch64elf.em (OPTION_PAC_PLT): New.
	(PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS): Add pac-plt.
	(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_PAC_PLT.
	* testsuite/ld-aarch64/aarch64-elf.exp: Add the following tests.
	* testsuite/ld-aarch64/bti-pac-plt-1.d: New test.
	* testsuite/ld-aarch64/bti-pac-plt-2.d: New test.
	* testsuite/ld-aarch64/pac-plt-1.d: New test.
	* testsuite/ld-aarch64/pac-plt-2.d: New test.
	* testsuite/ld-aarch64/bti-plt-1.s: Add .ifndef directive.
 2019-03-13 11:47:33 +00:00
Sudakshina Das
37c18eedff [BFD, LD, AArch64, 2/3] Add --force-bti to enable BTI and to select BTI enabled PLTs 
This is part of the patch series to add support for BTI and
PAC in AArch64 linker.

1) This patch adds a new ld command line option: --force-bti.
In the presence of this option, the linker enables BTI with the
GNU_PROPERTY_AARCH64_FEATURE_1_BTI feature. This gives out warning
in case of missing gnu notes for BTI in inputs.
2) It also defines a new set of BTI enabled PLTs. These are used either
when all the inputs are marked with GNU_PROPERTY_AARCH64_FEATURE_1_BTI
or when the new --force-bti option is used. This required adding new
fields in elf_aarch64_link_hash_table so that we could make the PLT
related information more generic.
3) It also defines a dynamic tag DT_AARCH64_BTI_PLT. The linker uses
this whenever it picks BTI enabled PLTs.
All these are made according to the new AArch64 ELF ABI
https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4

*** bfd/ChangeLog ***

2019-03-13  Sudakshina Das  <sudi.das@arm.com>
	    Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* bfd-in.h (aarch64_plt_type, aarch64_enable_bti_type): New.
	(aarch64_bti_pac_info): New.
	(bfd_elf64_aarch64_set_options): Add aarch64_bti_pac_info argument.
	(bfd_elf32_aarch64_set_options): Likewise.
	* bfd-in2.h: Regenerate
	* elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): New.
	(PLT_BTI_SMALL_ENTRY_SIZE, PLT_BTI_TLSDESC_ENTRY_SIZE): New.
	(elfNN_aarch64_small_plt0_bti_entry): New.
	(elfNN_aarch64_small_plt_bti_entry): New.
	(elfNN_aarch64_tlsdesc_small_plt_bti_entry): New.
	(elf_aarch64_obj_tdata): Add no_bti_warn and plt_type fields.
	(elf_aarch64_link_hash_table): Add plt0_entry, plt_entry and
	tlsdesc_plt_entry_size fields.
	(elfNN_aarch64_link_hash_table_create): Initialise the new fields.
	(setup_plt_values): New helper function.
	(bfd_elfNN_aarch64_set_options): Use new bp_info to set plt sizes and
	bti enable type.
	(elfNN_aarch64_allocate_dynrelocs): Use new size members instead of
	fixed macros.
	(elfNN_aarch64_size_dynamic_sections): Likewise and add checks.
	(elfNN_aarch64_create_small_pltn_entry): Use new generic pointers
	to plt stubs instead of fixed ones and update filling them according
	to the need for bti.
	(elfNN_aarch64_init_small_plt0_entry): Likewise.
	(elfNN_aarch64_finish_dynamic_sections): Likewise.
	(get_plt_type, elfNN_aarch64_get_synthetic_symtab): New.
	(elfNN_aarch64_plt_sym_val): Update size accordingly.
	(elfNN_aarch64_link_setup_gnu_properties): Set up plts if BTI GNU NOTE
	is set.
	(bfd_elfNN_get_synthetic_symtab): Define.
	(elfNN_aarch64_merge_gnu_properties): Give out warning with --force-bti
	and mising BTI NOTE SECTION.

*** binutils/ChangeLog ***

2019-03-13  Sudakshina Das  <sudi.das@arm.com>
	    Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* readelf.c (get_aarch64_dynamic_type): New.
	(get_dynamic_type): Use above for EM_AARCH64.
	(dynamic_section_aarch64_val): New.
	(process_dynamic_section): Use above for EM_AARCH64.

*** include/ChangeLog ***

2019-03-13  Sudakshina Das  <sudi.das@arm.com>
	    Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* elf/aarch64.h (DT_AARCH64_BTI_PLT): New.

*** ld/ChangeLog ***

2019-03-13  Sudakshina Das  <sudi.das@arm.com>
	    Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* NEWS: Document --force-bti.
	* emultempl/aarch64elf.em (plt_type, bti_type, OPTION_FORCE_BTI): New.
	(PARSE_AND_LIST_SHORTOPTS, PARSE_AND_LIST_OPTIONS): Add force-bti.
	(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_FORCE_BTI.
	* testsuite/ld-aarch64/aarch64-elf.exp: Add all the tests below.
	* testsuite/ld-aarch64/bti-plt-1.d: New test.
	* testsuite/ld-aarch64/bti-plt-1.s: New test.
	* testsuite/ld-aarch64/bti-plt-2.s: New test.
	* testsuite/ld-aarch64/bti-plt-2.d: New test.
	* testsuite/ld-aarch64/bti-plt-3.d: New test.
	* testsuite/ld-aarch64/bti-plt-4.d: New test.
	* testsuite/ld-aarch64/bti-plt-5.d: New test.
	* testsuite/ld-aarch64/bti-plt-6.d: New test.
	* testsuite/ld-aarch64/bti-plt-7.d: New test.
	* testsuite/ld-aarch64/bti-plt-so.s: New test.
	* testsuite/ld-aarch64/bti-plt.ld: New test.
 2019-03-13 11:47:07 +00:00
Sudakshina Das
cd702818c6 [BFD, LD, AArch64, 1/3] Add support for GNU PROPERTIES in AArch64 for BTI and PAC 
This is part of the patch series to add support for BTI and
PAC in AArch64 linker.

This patch implements the following:
1) This extends in the gnu property support in the linker for
AArch64 by defining backend hooks for elf_backend_setup_gnu_properties,
elf_backend_merge_gnu_properties and elf_backend_parse_gnu_properties.
2) It defines AArch64 specific GNU property
GNU_PROPERTY_AARCH64_FEATURE_1_AND and 2 bit for BTI and PAC in it.
3) It also adds support in readelf.c to read and print these new
GNU properties in AArch64.
All these are made according to the new AArch64 ELF ABI
https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4

*** bfd/ChangeLog ***

2019-03-13  Sudakshina Das  <sudi.das@arm.com>

	* elf-properties.c (_bfd_elf_link_setup_gnu_properties): Exclude
	linker created inputs from merge.
	* elfnn-aarch64.c (struct elf_aarch64_obj_tdata): Add field for
	GNU_PROPERTY_AARCH64_FEATURE_1_AND properties.
	(elfNN_aarch64_link_setup_gnu_properties): New.
	(elfNN_aarch64_merge_gnu_properties): New.
	(elf_backend_setup_gnu_properties): Define for AArch64.
	(elf_backend_merge_gnu_properties): Likewise.
	* elfxx-aarch64.c (_bfd_aarch64_elf_link_setup_gnu_properties): Define.
	(_bfd_aarch64_elf_parse_gnu_properties): Define.
	(_bfd_aarch64_elf_merge_gnu_properties): Define.
	* elfxx-aarch64.h (_bfd_aarch64_elf_link_setup_gnu_properties): Declare.
	(_bfd_aarch64_elf_parse_gnu_properties): Declare.
	(_bfd_aarch64_elf_merge_gnu_properties): Declare.
	(elf_backend_parse_gnu_properties): Define for AArch64.

*** binutils/ChangeLog ***

2019-03-13  Sudakshina Das  <sudi.das@arm.com>

	* readelf.c (decode_aarch64_feature_1_and): New.
	(print_gnu_property_note): Add case for AArch64 gnu notes.

*** include/ChangeLog ***

2019-03-13  Sudakshina Das  <sudi.das@arm.com>

	* elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New.
	(GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New.
	(GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New.

*** ld/ChangeLog ***

2019-03-13  Sudakshina Das  <sudi.das@arm.com>

	* NEWS: Document GNU_PROPERTY_AARCH64_FEATURE_1_BTI and
	GNU_PROPERTY_AARCH64_FEATURE_1_PAC.
	* testsuite/ld-aarch64/aarch64-elf.exp: Add run commands for new tests.
	* testsuite/ld-aarch64/property-bti-pac1.d: New test.
	* testsuite/ld-aarch64/property-bti-pac1.s: New test.
	* testsuite/ld-aarch64/property-bti-pac2.d: New test.
	* testsuite/ld-aarch64/property-bti-pac2.s: New test.
	* testsuite/ld-aarch64/property-bti-pac3.d: New test.
 2019-03-13 11:47:00 +00:00
Alan Hayward
e6c3b5bfb4 AArch64: Add pauth core file section 
Used for the AArch64 pointer authentication code mask registers in Arm v8.3-a.

NT_ARM_PAC_MASK matches the value in Linux include/uapi/linux/elf.h

include/ChangeLog:

	* elf/common.h (NT_ARM_PAC_MASK): Add define.

bfd/ChangeLog:

	* elf-bfd.h (elfcore_write_aarch_pauth): Add declaration.
	* elf.c (elfcore_grok_aarch_pauth): New function.
	(elfcore_grok_note): Check for NT_ARM_PAC_MASK.
	(elfcore_write_aarch_pauth): New function.
	(elfcore_write_register_note): Check for AArch64 pauth section.
 2019-02-20 10:39:28 +00:00
Saagar Jha
91d78b8179 Use the correct name for various MACH-O based operating systems in comments. 
include	* mach-o/loader.h: Use new OS names in comments.
 2019-02-15 12:50:52 +00:00
tromey
e20773049f Fix splay tree KEY leak detected in GDB test gdb.base/macscp.exp 
When a node is removed from a splay tree, the splay tree was
not using the function splay_tree_delete_key_fn to release the key.
This was causing a leak, fixed by Tom Tromey.

This patch fixes another key leak, that happens when a key equal to
a key already present is inserted.  In such a case, we have to release
the old KEY.
Note that this is based on the assumption that the caller always
allocates a new KEY when doing an insert.

Also, clarify the documentation about when the release functions are
called.

2019-02-11  Philippe Waroquiers  <philippe.waroquiers@skynet.be>

	* splay-tree.h (splay_tree_delete_key_fn): Update comment.
	(splay_tree_delete_value_fn): Likewise.

libiberty/ChangeLog
2019-02-11  Philippe Waroquiers  <philippe.waroquiers@skynet.be>

	* splay-tree.c (splay_tree_insert): Also release old KEY in case
	of insertion of a key equal to an already present key.
	(splay_tree_new_typed_alloc): Update comment.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@268793 138bc75d-0d04-0410-961f-82ee72b054a4
 2019-02-12 06:06:19 -07:00
Andreas Krebbel
fc60b8c806 S/390: Implement instruction set extensions 
opcodes/ChangeLog:

2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	* s390-mkopc.c (main): Accept arch13 as cpu string.
	* s390-opc.c: Add new instruction formats and instruction opcode
	masks.
	* s390-opc.txt: Add new arch13 instructions.

include/ChangeLog:

2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	* opcode/s390.h (enum s390_opcode_cpu_val): Add
	S390_OPCODE_ARCH13.

gas/ChangeLog:

2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	* config/tc-s390.c (s390_parse_cpu): New entry for arch13.
	* doc/c-s390.texi: Document arch13 march option.
	* testsuite/gas/s390/s390.exp: Run the arch13 related tests.
	* testsuite/gas/s390/zarch-arch13.d: New test.
	* testsuite/gas/s390/zarch-arch13.s: New test.
	* testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics
	also for z13.
 2019-01-31 17:32:18 +01:00
Sudi Das
550fd7bf68 AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension. 
This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV
instructions. These instructions needed special infrastructure to support
[base]! style for addressing mode. That is also removed now.

Committed on behalf of Sudakshina Das.

*** gas/ChangeLog ***

	* config/tc-aarch64.c (parse_address_main): Remove support for
	[base]! address expression.
	(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
	(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
	and stgv.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** include/ChangeLog ***

	* opcode/aarch64.h (enum aarch64_opnd): Remove
	AARCH64_OPND_ADDR_SIMPLE_2.
	(enum aarch64_insn_class): Remove ldstgv_indexed.

*** opcodes/ChangeLog ***

	* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
	* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
	* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
	* aarch64-dis.h (ext_addr_simple_2): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Remove
	case for ldstgv_indexed.
	(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
	* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
	(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
 2019-01-25 14:49:51 +00:00
Tom Tromey
71ba91e1c0 Include coff/sym.h from coff/ecoff.h 
coff/ecoff.h refers to some names defined in coff/sym.h.  Include the
latter from the former, so that users of the header don't need to know
this detail.

2019-01-22  Tom Tromey  <tom@tromey.com>

	* coff/ecoff.h: Include coff/sym.h.
 2019-01-22 20:35:59 -07:00
Nick Clifton
f974f26cb1 Add markers for 2.32 branch to NEWS and ChangeLog files. 2019-01-19 15:55:50 +00:00
Jim Wilson
2dc8dd17cd RISC-V: Support ELF attribute for gas and readelf. 
2019-01-16  Kito Cheng  <kito@andestech.com>
		    Nelson Chu  <nelson@andestech.com>

	bfd/
	* elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New.
	(elf_backend_obj_attrs_vendor): Define.
	(elf_backend_obj_attrs_section_type): Likewise.
	(elf_backend_obj_attrs_section): Likewise.
	(elf_backend_obj_attrs_arg_type): Define as
	riscv_elf_obj_attrs_arg_type.
	* elfxx-riscv.c (riscv_estimate_digit): New.
	(riscv_estimate_arch_strlen1): Likewise.
	(riscv_estimate_arch_strlen): Likewise.
	(riscv_arch_str1): Likewise.
	(riscv_arch_str): Likewise.
	* elfxx-riscv.h (riscv_arch_str): Declare.
	binutils/
	* readelf.c (get_riscv_section_type_name): New function.
	(get_section_type_name): Add handler for RISC-V.
	(riscv_attr_tag_t): Declare.
	(riscv_attr_tag): New.
	(display_riscv_attribute): New function.
	(process_attributes): Add handler for RISC-V.
	* testsuite/binutils-all/strip-3.d: Remove .riscv.attribute
	section.
	gas/
	* config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined.
	(riscv_set_options): Add `arch_attr` field.
	(riscv_opts): Set default value for arch_attr.
	(riscv_write_out_arch_attr): New.
	(riscv_set_public_attributes): Likewise.
	(riscv_md_end): Likewise.
	(riscv_convert_symbolic_attribute): Likewise.
	(s_riscv_attribute): Likewise.
	(explicit_arch_attr): Likewise.
	(riscv_pseudo_table): Add .attribute to the table.
	(options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR
	enumeration constants.
	(md_longopts): Add `march-attr' and `mno-arch-attr' options.
	(md_parse_option): Handle the new options.
	(md_show_usage): Document the `march-attr' option.
	* config/tc-riscv.h (md_end): Define as riscv_md_end
	(riscv_md_end): Declare.
	(CONVERT_SYMBOLIC_ATTRIBUTE): Define as
	riscv_convert_symbolic_attribute.
	(riscv_convert_symbolic_attribute): Declare.
	(start_assemble): Declare.
	* testsuite/gas/elf/elf.exp: Adjust test case for section2.e.
	* testsuite/gas/elf/section2.e-riscv: New.
	* testsuite/gas/riscv/attribute-01.d: New test
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-04.s: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-05.s: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-06.s: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-07.s: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-08.s: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.s: Likewise.
	* testsuite/gas/riscv/empty.l: Likewise.
	* doc/c-riscv.texi (.attribute): Add documentation.
	* configure.ac (--enable-default-riscv-attribute): New options.
	* configure: Re-generate.
	* config.in: Re-generate.
	include/
	* elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define.
	(Tag_RISCV_arch): Likewise.
	(Tag_RISCV_priv_spec): Likewise.
	(Tag_RISCV_priv_spec_minor): Likewise.
	(Tag_RISCV_priv_spec_revision): Likewise.
	(Tag_RISCV_unaligned_access): Likewise.
	(Tag_RISCV_stack_align): Likewise.
 2019-01-16 13:14:59 -08:00
Павел Крюков
8f0a21480b Include <string.h> to dis-asm.h to get strchr declaration 
Include <string.h> to dis-asm.h to get strchr declaration

include/Changelog:
2019-01-11  Pavel I. Kryukov  <kryukov@frtk.ru>

        * dis-asm.h: include <string.h>
 2019-01-14 16:41:03 -05:00
Nick Clifton
1910070b29 Sync libiberty sources with gcc master versions. 
.	* libiberty: Sync with gcc.  Bring in:
	2019-01-09  Sandra Loosemore  <sandra@codesourcery.com>

	PR other/16615

	* cp-demangle.c: Mechanically replace "can not" with "cannot".
	* floatformat.c: Likewise.
	* strerror.c: Likewise.

	2018-12-22  Jason Merrill  <jason@redhat.com>

	Remove support for demangling GCC 2.x era mangling schemes.
	* cplus-dem.c: Remove cplus_mangle_opname, cplus_demangle_opname,
	internal_cplus_demangle, and all subroutines.
	(libiberty_demanglers): Remove entries for ancient GNU (pre-3.0),
	Lucid, ARM, HP, and EDG demangling styles.
	(cplus_demangle): Remove 'work' variable.  Don't call
	internal_cplus_demangle.

include	* Merge from GCC:
	2018-12-22  Jason Merrill  <jason@redhat.com>

	* demangle.h: Remove support for ancient GNU (pre-3.0), Lucid,
	ARM, HP, and EDG demangling styles.
 2019-01-10 09:44:13 +00:00
Sandra Loosemore
a08da33eb3 Merge from gcc: use "cannot" instead of "can not" in libiberty and include. 
2019-01-09  Sandra Loosemore  <sandra@codesourcery.com>

	Merge from GCC:

	2019-01-09  Sandra Loosemore  <sandra@codesourcery.com>

	PR other/16615 [2/5]

	include/
	* libiberty.h: Mechanically replace "can not" with "cannot".
	* plugin-api.h: Likewise.

	libiberty/
	* cp-demangle.c: Mechanically replace "can not" with "cannot".
	* floatformat.c: Likewise.
	* strerror.c: Likewise.
 2019-01-09 13:59:16 -08:00
Yoshinori Sato
59581069b4 RX: include - Add RXv3 support. 
* elf/rx.h (EF_RX_CPU_MASK): Update new bits.
	(E_FLAG_RX_V3): New RXv3 type.
	* opcode/rx.h (RX_Size): Add double size.
	(RX_Operand_Type): Add double FPU registers.
	(RX_Opcode_ID): Add new instuctions.
 2019-01-05 22:49:46 +09:00
Alan Modra
827041555a Update year range in copyright notice of binutils files 2019-01-01 22:06:53 +10:30
Alan Modra
d5c04e1bf8 ChangeLog rotation 2019-01-01 21:25:40 +10:30
Alan Modra
d1a3c973fa PR24028, PPC_INT_FMT 
PPC_INT_FMT is redundant now that bfd.h pulls in inttypes.h if
available.  Apparently MacOS Mojave defines int64_t as long long even
though long is also 64 bits, which confuses the logic selecting
PPC_INT_FMT (and BFD_PRI64 too).  Hopefully inttypes.h is available on
Mojave.

	PR 24028
include/
	* opcode/ppc.h (PPC_INT_FMT): Delete.
opcodes/
	* ppc-dis.c (print_insn_powerpc): Replace PPC_INT_FMT uses with
	PRId64/PRIx64.
 2018-12-28 15:02:04 +10:30
H.J. Lu
0a59decbb8 elf: Add PT_GNU_PROPERTY segment type 
Linkers group input note sections with the same name into one output
note section with the same name.  One output note section is placed in
one PT_NOTE segment.  New linkers merge all input .note.gnu.property
sections into one output .note.gnu.property section with a single
NT_GNU_PROPERTY_TYPE_0 note in a single PT_NOTE segment.  Since older
linkers treat input .note.gnu.property section as a generic note section
and just concatenate all input .note.gnu.property sections into one
output .note.gnu.property section without merging them, we may
see one or more NT_GNU_PROPERTY_TYPE_0 notes in PT_NOTE segment, which
are invalid.

GNU_PROPERTY_X86_UINT32_VALID was defined to address this issue such
that linker sets the bit for non-relocatable outputs.  But it isn't
sufficient:

1. It doesn't cover generic properties.
2. When -mx86-used-note=yes is passed to x86 assembler, the
GNU_PROPERTY_X86_UINT32_VALID bit is set in GNU_PROPERTY_X86_ISA_1_USED
property in object file and older linkers generate invalid
NT_GNU_PROPERTY_TYPE_0 notes with the GNU_PROPERTY_X86_UINT32_VALID bit
set.

I am proposing the following changes:

1. Add PT_GNU_PROPERTY segment type:

 # define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)

which covers .note.gnu.property section.
2. Remove GNU_PROPERTY_X86_UINT32_VALID.

bfd/

	PR ld/23900
	* elf.c (get_program_header_size): Add a PT_GNU_PROPERTY
	segment for NOTE_GNU_PROPERTY_SECTION_NAME.
	(_bfd_elf_map_sections_to_segments): Create a PT_GNU_PROPERTY
	segment for NOTE_GNU_PROPERTY_SECTION_NAME.
	* elfxx-x86.c (_bfd_elf_link_setup_gnu_properties): Don't set
	GNU_PROPERTY_X86_UINT32_VALID.

binutils/

	PR ld/23900
	* readelf.c (get_segment_type): Support PT_GNU_PROPERTY.
	(decode_x86_isa): Don't check GNU_PROPERTY_X86_UINT32_VALID.
	(decode_x86_feature_1): Likewise.
	(decode_x86_feature_2): Likewise.
	(print_gnu_property_note): Remove GNU_PROPERTY_X86_UINT32_VALID
	check.
	* testsuite/binutils-all/i386/empty.d: Updated.
	* testsuite/binutils-all/x86-64/empty-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/empty.d: Likewise.
	* testsuite/binutils-all/i386/pr21231b.s: Change
	GNU_PROPERTY_X86_ISA_1_USED bits to 0x7fffffff.
	* testsuite/binutils-all/x86-64/pr21231b.s: Likewise.

gas/

	PR ld/23900
	* config/tc-i386.c (x86_cleanup): Don't set
	GNU_PROPERTY_X86_UINT32_VALID.
	* testsuite/gas/i386/property-1.s: Change
	GNU_PROPERTY_X86_ISA_1_USED bits to 0.

include/

	PR ld/23900
	* elf/common.h (PT_GNU_PROPERTY): New.
	(GNU_PROPERTY_X86_UINT32_VALID): Removed.

ld/

	PR ld/23900
	* testsuite/ld-elf/elf.exp: Run PR ld/23900 test.
	* testsuite/ld-elf/pr23900-1-32.rd: New file.
	* testsuite/ld-elf/pr23900-1-64.rd: Likewise.
	* testsuite/ld-elf/pr23900-1.d: Likewise.
	* testsuite/ld-elf/pr23900-1.s: Likewise.
	* testsuite/ld-elf/pr23900-2.s: Likewise.
	* testsuite/ld-elf/pr23900-2a.d: Likewise.
	* testsuite/ld-elf/pr23900-2b.d: Likewise.
	* testsuite/ld-i386/ibt-plt-1.d: Adjusted.
	* testsuite/ld-i386/ibt-plt-2c.d: Likewise.
	* testsuite/ld-i386/ibt-plt-2d.d: Likewise.
	* testsuite/ld-i386/ibt-plt-3d.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-1.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2c.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2c.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3c.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3d.d: Likewise.
	* testsuite/ld-i386/pr23372c.d: Expect <None>
	for GNU_PROPERTY_X86_ISA_1_USED.
	* testsuite/ld-x86-64/pr23372c-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23372c.d: Likewise.
	* testsuite/ld-x86-64/pr23372d-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23372d.d: Likewise.
	* testsuite/ld-x86-64/property-x86-5a.s: Change
	GNU_PROPERTY_X86_ISA_1_USED bits to 0.
	* testsuite/ld-x86-64/property-x86-5b.s: Likewise.
 2018-12-14 04:55:34 -08:00
Nick Clifton
69799d67e8 Fix a failure in the libiberty testsuite by increasing the recursion limit to 2048. 
PR 88409
include	* demangle.h (DEMANGLE_RECURSION_LIMIT): Increase to 2048.

binutils* NEWS: Note that recursion limit has increased to 2048.
	* doc/binutils.texi: Likewise.
 2018-12-11 12:01:15 +00:00
H.J. Lu
d2ef37ebd9 elf: Report property change when merging properties 
With merging properties, report property change in linker map file, like

Merging program properties

Removed property 0xc0010000 to merge /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crt1.o (0x0) and /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crti.o (0x0)
Removed property 0xc0000002 to merge /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crt1.o (0x3) and x.o (not found)
Removed property 0xc0000000 to merge /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crt1.o (not found) and /usr/lib64/libc_nonshared.a(elf-init.oS) (0x0)
Removed property 0xc0000001 to merge /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crt1.o (not found) and /usr/lib64/libc_nonshared.a(elf-init.oS) (0x0)

bfd/

	* elf-properties.c (elf_find_and_remove_property): Add a
	bfd_boolean argument to indicate if the property should be
	removed.
	(elf_merge_gnu_property_list): Updated.  Report
	property change in linker map file.
	(elf_get_gnu_property_section_size): Skip property_remove
	properties.
	(elf_write_gnu_properties): Likewise.
	(_bfd_elf_link_setup_gnu_properties): Report property merge
	in linker map file.  Pass abfd to elf_merge_gnu_property_list.

include/

	* bfdlink.h (bfd_link_info): Add has_map_file.

ld/

	* NEWS: Updated for property change report.
	* ld.texi: Document property change report.
	* ldmain.c (main): Set link_info.has_map_file to TRUE when
	linker map file is used.
	* testsuite/ld-scripts/rgn-over1.d: Updated.
	* testsuite/ld-scripts/rgn-over2.d: Likewise.
	* testsuite/ld-scripts/rgn-over3.d: Likewise.
	* testsuite/ld-scripts/rgn-over4.d: Likewise.
	* testsuite/ld-scripts/rgn-over5.d: Likewise.
	* testsuite/ld-scripts/rgn-over6.d: Likewise.
	* testsuite/ld-scripts/rgn-over7.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Check linker map
	file.
	* testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1a.map: New file.
 2018-12-07 08:30:43 -08:00
Nick Clifton
af03af8f55 Synchronize libiberty with gcc and add --no-recruse-limit option to tools that support name demangling. 
This patch addresses the multitude of bug reports about resource exhaustion
in libiberty's name demangling code.  It adds a limit to the amount of
recursion that is allowed, before an error is triggered.  It also adds a
new demangling option to disable this limit.  (The limit is enabled by
default).

	PR 87681
	PR 87675
	PR 87636
	PR 87335
libiberty * cp-demangle.h (struct d_info): Add recursion_limit field.
	* cp-demangle.c (d_function_type): If the recursion limit is
	enabled and reached, return with a failure result.
        (d_demangle_callback): If the recursion limit is enabled, check
	for a mangled string that is so long that there is not enough
	stack space for the local arrays.
        * cplus-dem.c (struct work): Add recursion_level field.
	(demangle_nested_args): If the recursion limit is enabled and
	reached, return with a failure result.

include	* demangle.h (DMGL_RECURSE_LIMIT): Define.
        (DEMANGLE_RECURSION_LIMIT): Prototype.

binutuils * addr2line.c (demangle_flags): New static variable.
        (long_options): Add --recurse-limit and --no-recurse-limit.
        (translate_address): Pass demangle_flags to bfd_demangle.
        (main): Handle --recurse-limit and --no-recurse-limit options.
        * cxxfilt.c (flags): Add DMGL_RECURSE_LIMIT.
        (long_options): Add --recurse-limit and --no-recurse-limit.
        (main): Handle new options.
        * dlltool.c (gen_def_file): Include DMGL_RECURSE_LIMIT in flags
        passed to cplus_demangle.
        * nm.c (demangle_flags): New static variable.
        (long_options): Add --recurse-limit and --no-recurse-limit.
        (main): Handle new options.
        * objdump.c (demangle_flags): New static variable.
        (usage): Add --recurse-limit and --no-recurse-limit.
        (long_options): Likewise.
        (objdump_print_symname): Pass demangle_flags to bfd_demangle.
        (disassemble_section): Likewise.
        (dump_dymbols): Likewise.
        (main): Handle new options.
        * prdbg.c (demangle_flags): New static variable.
        (tg_variable): Pass demangle_flags to demangler.
        (tg_start_function): Likewise.
        * stabs.c (demangle_flags): New static variable.
        (stab_demangle_template): Pass demangle_flags to demangler.
        (stab_demangle_v3_argtypes): Likewise.
        (stab_demangle_v3_arg): Likewise.
	* doc/binutuls.texi: Document new command line options.
	* NEWS: Mention the new feature.
        * testsuite/config/default.exp (CXXFILT): Define if not already
        defined.
        (CXXFILTFLAGS): Likewise.
        * testsuite/binutils-all/cxxfilt.exp: New file.  Runs a few
        simple tests of the cxxfilt program.
 2018-12-07 11:32:55 +00:00
Alan Modra
bb6bf75e7a PowerPC @l, @h and @ha warnings, plus VLE e_li 
This patch started off just adding the warnings in tc-ppc.c about
incorrect usage of @l, @h and @ha in instructions that don't have
16-bit D-form fields.  That unfortunately showed up three warnings in
ld/testsuite/ld-powerpc/vle-multiseg.s on instructions like
	e_li r3, IV_table@l+0x00
which was being assembled to
   8:	70 60 00 00 	e_li    r3,0
			a: R_PPC_ADDR16_LO	IV_table
The ADDR16_LO reloc is of course completely bogus on e_li, which has
a split 20-bit signed integer field in bits 0x1f7fff, the low 11 bit
in 0x7ff, the next 5 bits in 0x1f0000, and the high 4 bits in 0x7800.
Applying an ADDR16_LO reloc to the instruction potentially changes
the e_li instruction to e_add2i., e_add2is, e_cmp16i, e_mull2i,
e_cmpl16i, e_cmph16i, e_cmphl16i, e_or2i, e_and2i., e_or2is, e_lis,
e_and2is, or some invalid encodings.

Now there is a relocation that suits e_li, R_PPC_VLE_ADDR20, which was
added 2017-09-05 but I can't see code in gas to generate the
relocation.  In any case, VLE_ADDR20 probably doesn't have the correct
semantics for @l since ideally you'd want an @l to pair with @h or @ha
to generate a 32-bit constant.  Thus @l should only produce a 16-bit
value, I think.  So we need some more relocations to handle e_li it
seems, or as I do in this patch, modify the behaviour of existing
relocations when applied to e_li instructions.

include/
	* opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define.
bfd/
	* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_VLE_ADDR20>): Correct
	mask and shift value.
	(ppc_elf_vle_split16): Use E_OPCODE_MASK.  Handle e_li
	specially.
gas/
	* config/tc-ppc.c (md_assemble): Adjust relocs for VLE before
	TLS tweaks.  Handle e_li.  Warn on unexpected operand field
	for lo16/hi16/ha16 relocs.
 2018-12-06 23:01:03 +10:30
Andrew Burgess
884b49e3a9 opcodes/riscv: Hide '.L0 ' fake symbols 
The RISC-V assembler generates fake labels with the name '.L0 ' as
part of the debug information (see
gas/config/tc-riscv.h:FAKE_LABEL_NAME).

The problem is that currently, when disassembling an object file, the
output looks like this (this is an example from the GDB testsuite, but
is pretty representative of anything with debug information):

  000000000000001e <main>:
    1e:   7179                    addi    sp,sp,-48
    20:   f406                    sd      ra,40(sp)
    22:   f022                    sd      s0,32(sp)
    24:   1800                    addi    s0,sp,48

  0000000000000026 <.L0 >:
    26:   87aa                    mv      a5,a0
    28:   feb43023                sd      a1,-32(s0)
    2c:   fcc43c23                sd      a2,-40(s0)
    30:   fef42623                sw      a5,-20(s0)

  0000000000000034 <.L0 >:
    34:   fec42783                lw      a5,-20(s0)
    38:   0007871b                sext.w  a4,a5
    3c:   678d                    lui     a5,0x3
    3e:   03978793                addi    a5,a5,57 # 3039 <.LASF30+0x2a9d>
    42:   02f71463                bne     a4,a5,6a <.L0 >

  0000000000000046 <.L0 >:
    46:   000007b7                lui     a5,0x0
    4a:   0007b783                ld      a5,0(a5) # 0 <need_malloc>
    4e:   6f9c                    ld      a5,24(a5)

  0000000000000050 <.L0 >:
    50:   86be                    mv      a3,a5
    52:   466d                    li      a2,27
    54:   4585                    li      a1,1
    56:   000007b7                lui     a5,0x0
    5a:   00078513                mv      a0,a5
    5e:   00000097                auipc   ra,0x0
    62:   000080e7                jalr    ra # 5e <.L0 +0xe>

  0000000000000066 <.L0 >:
    66:   4785                    li      a5,1
    68:   a869                    j       102 <.L0 >

  000000000000006a <.L0 >:
    6a:   000007b7                lui     a5,0x0
    6e:   00078513                mv      a0,a5
    72:   00000097                auipc   ra,0x0
    76:   000080e7                jalr    ra # 72 <.L0 +0x8>

The frequent repeated '.L0 ' labels are pointless, as they are
non-unique there's no way to match a use of '.L0 ' to its appearence
in the output, so we'd be better off just not printing it at all.
That's what this patch does by defining a 'symbol_is_valid' method for
RISC-V.  With this commit, the same disassembly now looks like this:

  000000000000001e <main>:
    1e:   7179                    addi    sp,sp,-48
    20:   f406                    sd      ra,40(sp)
    22:   f022                    sd      s0,32(sp)
    24:   1800                    addi    s0,sp,48
    26:   87aa                    mv      a5,a0
    28:   feb43023                sd      a1,-32(s0)
    2c:   fcc43c23                sd      a2,-40(s0)
    30:   fef42623                sw      a5,-20(s0)
    34:   fec42783                lw      a5,-20(s0)
    38:   0007871b                sext.w  a4,a5
    3c:   678d                    lui     a5,0x3
    3e:   03978793                addi    a5,a5,57 # 3039 <.LASF30+0x2a9d>
    42:   02f71463                bne     a4,a5,6a <.L4>
    46:   000007b7                lui     a5,0x0
    4a:   0007b783                ld      a5,0(a5) # 0 <need_malloc>
    4e:   6f9c                    ld      a5,24(a5)
    50:   86be                    mv      a3,a5
    52:   466d                    li      a2,27
    54:   4585                    li      a1,1
    56:   000007b7                lui     a5,0x0
    5a:   00078513                mv      a0,a5
    5e:   00000097                auipc   ra,0x0
    62:   000080e7                jalr    ra # 5e <main+0x40>
    66:   4785                    li      a5,1
    68:   a869                    j       102 <.L5>

  000000000000006a <.L4>:
    6a:   000007b7                lui     a5,0x0
    6e:   00078513                mv      a0,a5
    72:   00000097                auipc   ra,0x0
    76:   000080e7                jalr    ra # 72 <.L4+0x8>

In order to share the fake label between the assembler and the
libopcodes library, I've added some new defines RISCV_FAKE_LABEL_NAME
and RISCV_FAKE_LABEL_CHAR in include/opcode/riscv.h.  I could have
just moved FAKE_LABEL_NAME to the include file, however, I thnk this
would be confusing, someone working on the assembler would likely not
expect to find FAKE_LABEL_NAME defined outside of the assembler source
tree.  By introducing the RISCV_FAKE_LABEL_* defines I can leave the
assembler standard FAKE_LABEL_ defines in the assembler source, but
still share the RISCV_FAKE_LABEL_* with libopcodes.

gas/ChangeLog:

	* config/tc-riscv.h (FAKE_LABEL_NAME): Define as
	RISCV_FAKE_LABEL_NAME.
	(FAKE_LABEL_CHAR): Define as RISCV_FAKE_LABEL_CHAR.

include/ChangeLog:

	* dis-asm.h (riscv_symbol_is_valid): Declare.
	* opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define.
	(RISCV_FAKE_LABEL_CHAR): Define.

opcodes/ChangeLog:

        * disassembler.c (disassemble_init_for_target): Add RISC-V
        initialisation.
        * riscv-dis.c (riscv_symbol_is_valid): New function.
 2018-12-06 09:40:56 +00:00
Jim Wilson
1080bf78c0 RISC-V: Accept version, supervisor ext and more than one NSE for -march. 
This patch moves all -march parsing logic into bfd, because we will use this
code in ELF attributes.

	bfd/
	* elfxx-riscv.h (RISCV_DONT_CARE_VERSION): New macro.
	(struct riscv_subset_t): New structure.
	(riscv_subset_t): New typedef.
	(riscv_subset_list_t): New structure.
	(riscv_release_subset_list): New prototype.
	(riscv_add_subset): Likewise.
	(riscv_lookup_subset): Likewise.
	(riscv_lookup_subset_version): Likewise.
	(riscv_release_subset_list): Likewise.
	* elfxx-riscv.c: Include safe-ctype.h.
	(riscv_parsing_subset_version): New function.
	(riscv_supported_std_ext): Likewise.
	(riscv_parse_std_ext): Likewise.
	(riscv_parse_sv_or_non_std_ext): Likewise.
	(riscv_parse_subset): Likewise.
	(riscv_add_subset): Likewise.
	(riscv_lookup_subset): Likewise.
	(riscv_lookup_subset_version): Likewise.
	(riscv_release_subset_list): Likewise.
	gas/
	* config/tc-riscv.c: Include elfxx-riscv.h.
	(struct riscv_subset): Removed.
	(riscv_subsets): Change type to riscv_subset_list_t.
	(riscv_subset_supports): Removed argument: xlen_required and move
	logic into libbfd.
	(riscv_multi_subset_supports): Removed argument: xlen_required.
	(riscv_clear_subsets): Removed.
	(riscv_add_subset): Ditto.
	(riscv_set_arch): Extract parsing logic into libbfd.
	(riscv_ip): Update argument for riscv_multi_subset_supports and
	riscv_subset_supports. Update riscv_subsets due to struct definition
	changed.
	(riscv_after_parse_args): Update riscv_subsets due to struct
	definition changed, update and argument for riscv_subset_supports.
	* testsuite/gas/riscv/empty.s: New.
	* testsuite/gas/riscv/march-fail-rv32ef.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32i.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32i.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iam.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iam.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ic.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ic.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32icx2p.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32imc.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32imc.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64I.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64I.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64e.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64e.l: Likewise.
	* testsuite/gas/riscv/march-ok-g2.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
	* testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
	* testsuite/gas/riscv/march-ok-nse-with-version.: Likewise.d
	* testsuite/gas/riscv/march-ok-s-with-version.d: Likewise.
	* testsuite/gas/riscv/march-ok-s.d: Likewise.
	* testsuite/gas/riscv/march-ok-sx.d: Likewise.
	* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
	* testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
	include/
	* opcode/riscv.h (riscv_opcode): Change type of xlen_requirement to
	unsigned.
	opcodes/
	* riscv-opc.c: Change the type of xlen, because type of
	xlen_requirement changed.
 2018-12-03 14:05:17 -08:00
Jim Wilson
4765cd6119 RISC-V: Add .insn CA support. 
gas/
	* config/tc-riscv.c (validate_riscv_insn) <'F'>: Add support for CF6
	and CF2 operands.
	(riscv_ip) <'F'>: Likewise.
	* doc/c-riscv.texi (RISC-V-Formats): Add func6 abbreviation.  Use rs2
	instead of rs1 in CR description.  Add CA docs.
	* gas/testsuite/riscv/insn.s: Add use of .insn ca.
	* gas/testsuite/riscv/insn.d: Update to match.
	include/
	* opcode/riscv.h (OP_MASK_CFUNCT6, OP_SH_CFUNCT6): New.
	(OP_MASK_CFUNCT2, OP_SH_CFUNCT2): New.
	opcodes/
	* riscv-opc.c (ciw): Fix whitespace to align columns.
	(ca): New.
 2018-11-27 11:29:23 -08:00
Thomas Preud'homme
497d849d28 [ARM] Improve indentation of ARM architecture declarations 
This commit cleans up indentation of ARM architecture declaration,
namely entries of arm_archs and definition of macros ARM_EXT_*,
ARM_AEXT_*, ARM_AEXT2_*, FPU_EXT_*, FPU_ARCH_* and ARM_ARCH_*. It also
gets rid of unused ARM_ARCH_V6M-ONLY and merge AEM_AEXT_V6M_ONLY in
ARM_AEXT_V6M now sole user.

gas/
2018-11-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/tc-arm.c (arm_archs): Reindent.

include/
2018-11-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* opcode/arm.h (ARM_AEXT_V6M_ONLY): Merge into its use in ARM_AEXT_V6M.
	(ARM_ARCH_V6M_ONLY): Remove.
	(ARM_EXT_V1, ARM_EXT_V2, ARM_EXT_V2S, ARM_EXT_V3, ARM_EXT_V3M,
	ARM_EXT_V4, ARM_EXT_V4T, ARM_EXT_V5, ARM_EXT_V5T, ARM_EXT_V5ExP,
	ARM_EXT_V5E, ARM_EXT_V5J, ARM_EXT_V6, ARM_EXT_V6K, ARM_EXT_V8,
	ARM_EXT_V6T2, ARM_EXT_DIV, ARM_EXT_V5E_NOTM, ARM_EXT_V6_NOTM,
	ARM_EXT_V7, ARM_EXT_V7A, ARM_EXT_V7R, ARM_EXT_V7M, ARM_EXT_V6M,
	ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR, ARM_EXT_V6_DSP, ARM_EXT_MP,
	ARM_EXT_SEC, ARM_EXT_OS, ARM_EXT_ADIV, ARM_EXT_VIRT, ARM_EXT2_PAN,
	ARM_EXT2_V8_2A, ARM_EXT2_V8M, ARM_EXT2_ATOMICS, ARM_EXT2_V6T2_V8M,
	ARM_EXT2_FP16_INST, ARM_EXT2_V8M_MAIN, ARM_EXT2_RAS, ARM_EXT2_V8_3A,
	ARM_EXT2_V8A, ARM_EXT2_V8_4A, ARM_EXT2_FP16_FML, ARM_EXT2_V8_5A,
	ARM_EXT2_SB, ARM_EXT2_PREDRES, ARM_CEXT_XSCALE, ARM_CEXT_MAVERICK,
	ARM_CEXT_IWMMXT, ARM_CEXT_IWMMXT2, FPU_ENDIAN_PURE, FPU_ENDIAN_BIG,
	FPU_FPA_EXT_V1, FPU_FPA_EXT_V2, FPU_MAVERICK, FPU_VFP_EXT_V1xD,
	FPU_VFP_EXT_V1, FPU_VFP_EXT_V2, FPU_VFP_EXT_V3xD, FPU_VFP_EXT_V3,
	FPU_NEON_EXT_V1, FPU_VFP_EXT_D32, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
	FPU_VFP_EXT_FMA, FPU_VFP_EXT_ARMV8, FPU_NEON_EXT_ARMV8,
	FPU_CRYPTO_EXT_ARMV8, CRC_EXT_ARMV8, FPU_VFP_EXT_ARMV8xD,
	FPU_NEON_EXT_RDMA, FPU_NEON_EXT_DOTPROD, ARM_AEXT_V1, ARM_AEXT_V2,
	ARM_AEXT_V2S, ARM_AEXT_V3, ARM_AEXT_V3M, ARM_AEXT_V4xM, ARM_AEXT_V4,
	ARM_AEXT_V4TxM, ARM_AEXT_V4T, ARM_AEXT_V5xM, ARM_AEXT_V5,
	ARM_AEXT_V5TxM, ARM_AEXT_V5T, ARM_AEXT_V5TExP, ARM_AEXT_V5TE,
	ARM_AEXT_V5TEJ, ARM_AEXT_V6, ARM_AEXT_V6K, ARM_AEXT_V6Z, ARM_AEXT_V6KZ,
	ARM_AEXT_V6T2, ARM_AEXT_V6KT2, ARM_AEXT_V6ZT2, ARM_AEXT_V6KZT2,
	ARM_AEXT_V7_ARM, ARM_AEXT_V7A, ARM_AEXT_V7VE, ARM_AEXT_V7R,
	ARM_AEXT_NOTM, ARM_AEXT_V6M_ONLY, ARM_AEXT_V6M, ARM_AEXT_V6SM,
	ARM_AEXT_V7M, ARM_AEXT_V7, ARM_AEXT_V7EM, ARM_AEXT_V8A, ARM_AEXT2_V8A,
	ARM_AEXT2_V8_1A, ARM_AEXT2_V8_2A, ARM_AEXT2_V8_3A, ARM_AEXT2_V8_4A,
	ARM_AEXT2_V8_5A, ARM_AEXT_V8M_BASE, ARM_AEXT_V8M_MAIN,
	ARM_AEXT_V8M_MAIN_DSP, ARM_AEXT2_V8M, ARM_AEXT2_V8M_BASE,
	ARM_AEXT2_V8M_MAIN, ARM_AEXT2_V8M_MAIN_DSP, ARM_AEXT_V8R,
	ARM_AEXT2_V8R, FPU_VFP_V1xD, FPU_VFP_V1, FPU_VFP_V2, FPU_VFP_V3D16,
	FPU_VFP_V3, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4, FPU_VFP_V4_SP_D16,
	FPU_VFP_V5D16, FPU_VFP_ARMV8, FPU_NEON_ARMV8, FPU_CRYPTO_ARMV8,
	FPU_VFP_HARD, FPU_FPA, FPU_ARCH_VFP, FPU_ARCH_FPE, FPU_ARCH_FPA,
	FPU_ARCH_VFP_V1xD, FPU_ARCH_VFP_V1, FPU_ARCH_VFP_V2,
	FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_FP16,
	FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_NEON_V1, FPU_ARCH_VFP_V3_PLUS_NEON_V1,
	FPU_ARCH_NEON_FP16, FPU_ARCH_VFP_HARD, FPU_ARCH_VFP_V4,
	FPU_ARCH_VFP_V4D16, FPU_ARCH_VFP_V4_SP_D16, FPU_ARCH_VFP_V5D16,
	FPU_ARCH_VFP_V5_SP_D16, FPU_ARCH_NEON_VFP_V4, FPU_ARCH_VFP_ARMV8,
	FPU_ARCH_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
	FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD, ARCH_CRC_ARMV8,
	FPU_ARCH_NEON_VFP_ARMV8_1, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
	FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, ARM_ARCH_V1, ARM_ARCH_V2,
	ARM_ARCH_V2S, ARM_ARCH_V3, ARM_ARCH_V3M, ARM_ARCH_V4xM, ARM_ARCH_V4,
	ARM_ARCH_V4TxM, ARM_ARCH_V4T, ARM_ARCH_V5xM, ARM_ARCH_V5,
	ARM_ARCH_V5TxM, ARM_ARCH_V5T, ARM_ARCH_V5TExP, ARM_ARCH_V5TE,
	ARM_ARCH_V5TEJ, ARM_ARCH_V6, ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6KZ,
	ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, ARM_ARCH_V6KZT2,
	ARM_ARCH_V6M, ARM_ARCH_V6SM, ARM_ARCH_V7, ARM_ARCH_V7A, ARM_ARCH_V7VE,
	ARM_ARCH_V7R, ARM_ARCH_V7M, ARM_ARCH_V7EM, ARM_ARCH_V8A,
	ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A,
	ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8M_BASE, ARM_ARCH_V8M_MAIN,
	ARM_ARCH_V8M_MAIN_DSP, ARM_ARCH_V8R): Reindent.
 2018-11-13 12:19:28 +00:00
Sudakshina Das
503ba60025 [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension 
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch add support to the Bulk Allocation Tag instructions from
MTE. These are the following instructions added in this patch:
- LDGV <Xt>, [<Xn|SP>]!
- STGV <Xt>, [<Xn|SP>]!

This needed a new kind of operand for the new addressing [<Xn|SP>]!
since this has no offset and only takes a pre-indexed version.
Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced.
(AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does
not allow writeback). We also needed new encoding and decoding
functions to be able to do the same.

where
<Xt> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.

*** include/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
	(aarch64_insn_class): Add ldstgv_indexed.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm.c (aarch64_ins_addr_simple_2): New.
	* aarch64-asm.h (ins_addr_simple_2): Declare the above.
	* aarch64-dis.c (aarch64_ext_addr_simple_2): New.
	* aarch64-dis.h (ext_addr_simple_2): Declare the above.
	* aarch64-opc.c (operand_general_constraint_met_p): Add case for
	AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
	(aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
	* aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
	(AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_operands): Add switch case for
	AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
	(warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
 2018-11-12 13:20:58 +00:00
Sudakshina Das
fb3265b371 [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension 
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>

where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.

*** include/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
	and AARCH64_OPND_ADDR_SIMM13.
	(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
	for AARCH64_OPND_QLF_imm_tag.
	(operand_general_constraint_met_p): Add case for
	AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
	(aarch64_print_operand): Likewise.
	* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
	(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
	for both offset and pre/post indexed versions.
	(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_operands): Add switch case for
	AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
	(fix_insn): Likewise.
	(warn_unpredictable_ldst): Exempt STGP.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
	stzg, stz2g and stgp.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
 2018-11-12 13:09:55 +00:00
Sudakshina Das
193614f2b9 [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Extension 
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch add support to the Tag generation instructions from
MTE. These are the following instructions added in this patch:
- IRG <Xd|SP>, <Xn|SP>{, Xm}
- ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- GMI <Xd>, <Xn|SP>, <Xm>

where
<Xd|SP> : Is the 64-bit destination GPR or Stack pointer.
<Xn|SP> : Is the 64-bit source GPR or Stack pointer.
<uimm6> : Is the unsigned immediate, a multiple of 16
in the range 0 to 1008.
<uimm4> : Is the unsigned immediate, in the range 0 to 15.

*** include/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (aarch64_opnd): Add
	AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
	(OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
	* aarch64-opc.c (fields): Add entry for imm4_3.
	(operand_general_constraint_met_p): Add cases for
	AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
	(aarch64_print_operand): Likewise.
	* aarch64-tbl.h (QL_ADDG): New.
	(aarch64_opcode_table): Add addg, subg, irg and gmi.
	(AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
	* aarch64-asm.c (aarch64_ins_imm): Add case for
	operand_need_shift_by_four.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_operands): Add switch case for
	AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.d: Likewise.
 2018-11-12 12:59:22 +00:00
Sudakshina Das
73b605ec3f [BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A 
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions. Memory Tagging Extension is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds the new command line option and the new feature macros.

*** include/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (aarch64_feature_memtag): New.
	(MEMTAG, MEMTAG_INSN): New.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "memtag"
	as a new option.
	* doc/c-aarch64.texi: Document the same.
 2018-11-12 12:45:30 +00:00
Roman Bolshakov
fc7b364aba Add support for new load commands added by Apple to the MACH-O file format. 
bfd	* mach-o.h: Add new enums for BFD_MACH_O_PLATFORM_MACOS,
	BFD_MACH_O_PLATFORM_IOS, BFD_MACH_O_PLATFORM_TVOS,
	BFD_MACH_O_PLATFORM_WATCHOS, BFD_MACH_O_PLATFORM_BRIDGEOS,
	BFD_MACH_O_TOOL_CLANG, BFD_MACH_O_TOOL_SWIFT, BFD_MACH_O_TOOL_LD.
	(struct bfd_mach_o_note_command): New.
	(struct bfd_mach_o_build_version_tool): New.
	(struct bfd_mach_o_build_version_command): New.
	(bfd_mach_o_read_version_min): Don't split version into
	a few fields. Rename reserved to sdk.
	* mach-o.c (bfd_mach_o_read_version_min): Don't split version into a
	few fields. Rename reserved to sdk.
	(bfd_mach_o_read_command): Handle LC_VERSION_MIN_TVOS, LC_NOTE,
	LC_BUILD_VERSION.
	(bfd_mach_o_read_note): New.
	(bfd_mach_o_read_build_version): New.

	PR 23728
binutils* od-macho.c (printf_version): New.
	(dump_load_command): Use it to print version. Print sdk version. Print
	version info for watchOS and tvOS. Print LC_NOTE, LC_BUILD_VERSION.
	(dump_buld_version): New.
	(bfd_mach_o_platform_name): New
	(bfd_mach_o_tool_name): New

	* mach-o/external.h (mach_o_nversion_min_command_external): Rename
	reserved to sdk.
	(mach_o_note_command_external): New.
	(mach_o_build_version_command_external): New.
	* mach-o/loader.h (BFD_MACH_O_LC_VERSION_MIN_TVOS): Define.
	(BFD_MACH_O_LC_NOTE): Define.
 2018-11-07 15:20:22 +00:00
Nick Clifton
ddea148b3d Add support for a couple of new Mach-O commands. 
PR 23742
	* mach-o.c (bfd_mach_o_read_command): Accept and ignore
	BFD_MACH_O_LC_LINKER_OPTIONS and BFD_MACH_O_LC_BUILD_VERSION
	commands.

	* mach-o/loader.h: Add BFD_MACH_O_LC_BUILD_VERSION.
 2018-11-06 17:17:43 +00:00
Sudakshina Das
0632eeea6e [BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros. 
This patch addresses the following
1) Adding ARMv8.5-A in select_arm_features.
2) Updating the feature macro so that the new ARM_EXT2_* features for
Armv8.5-A are moved to ARM_AEXT2_V8_5A.

*** opcodes/ChangeLog ***

2018-11-06  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (select_arm_features): Update bfd_mach_arm_8
	with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.

*** include/ChangeLog ***

2018-11-06  Sudakshina Das  <sudi.das@arm.com>

	* opcode/arm.h (ARM_ARCH_V8_5A): Move ARM_EXT2_PREDRES and
	ARM_EXT2_SB to ...
	(ARM_AEXT2_V8_5A): Here.
 2018-11-06 12:13:45 +00:00
John Baldwin
d7ded98f4c Support AT_HWCAP2 on FreeBSD. 
include/ChangeLog:

	* elf/common.h (AT_FREEBSD_HWCAP2): Define.

gdb/ChangeLog:

	* fbsd-tdep.c (fbsd_print_auxv_entry): Handle AT_FREEBSD_HWCAP2.
 2018-10-26 10:20:56 -07:00
Sudakshina Das
104fefeebb [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.

This patch adds support for the mitigation for Spectre Variant 4 by
adding the PSTATE bit SSBS which are accessible using MSR and MRS
instructions. Although this is a mandatory addition to the ARMv8.5-A,
it is permitted to be added to any version of the ARMv8 architecture.
This is enabled using the command line option of +ssbs for older
versions.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (operand_general_constraint_met_p): Add
	SSBS in the check for one-bit immediate.
	(aarch64_sys_regs): New entry for SSBS.
	(aarch64_sys_reg_supported_p): New check for above.
	(aarch64_pstatefields): New entry for SSBS.
	(aarch64_pstatefield_supported_p): New check for above.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add new "ssbs".
	* doc/c-aarch64.texi: Document the same.
	* testsuite/gas/aarch64/ssbs-illegal1.d: New test.
	* testsuite/gas/aarch64/ssbs-illegal1.l: New test.
	* testsuite/gas/aarch64/ssbs-illegal2.d: New test.
	* testsuite/gas/aarch64/ssbs-illegal2.l: New test.
	* testsuite/gas/aarch64/ssbs.s: New test.
	* testsuite/gas/aarch64/ssbs1.d: Test with +ssbs
	* testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
 2018-10-09 15:39:29 +01:00
Sudakshina Das
a97330e723 [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.

This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
	(AARCH64_FEATURE_ID_PFR2): New.
	(AARCH64_ARCH_V8_5): Add both by default.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): New entries for
	scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
	(aarch64_sys_reg_supported_p): New checks for above.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/sysreg-4.s: Test registers
	scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
	* testsuite/gas/aarch64/sysreg-4.d: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
 2018-10-09 15:39:29 +01:00
Sudakshina Das
ff6054520c [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification)

The Branch Target Identification instructions (BTI) are allocated to
existing HINT space, using HINT numbers 32, 34, 36, 38, such that
bits[7:6] of the instruction identify the compatibility of the BTI
instruction to different branches.

	BTI {<targets>}

where <targets> one of the following, specifying which type of
indirection is allowed:

	j : Can be a target of any BR Xn isntruction.
	c : Can be a target of any BLR Xn and BR {X16|X17}.
	jc: Can be a target of any free branch.

A BTI instruction without any <targets> is the strictest of all and
can not be a target of nay free branch.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
	(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
	(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
	define HINT #imm values.
	(HINT_OPD_JC, HINT_OPD_NULL): Likewise.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
	(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
	with the hint immediate.
	* aarch64-opc.c (aarch64_hint_options): New entries for
	c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
	(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
	while checking for HINT_OPD_F_NOPRINT flag.
	* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
	extract value.
	* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
	(aarch64_opcode_table): Add entry for BTI.
	(AARCH64_OPERANDS): Add new description for BTI targets.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_bti_operand): New.
	(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/system.d: Update for BTI.
	* testsuite/gas/aarch64/bti.s: New.
	* testsuite/gas/aarch64/bti.d: New.
	* testsuite/gas/aarch64/illegal-bti.d: New.
	* testsuite/gas/aarch64/illegal-bti.l: New.
 2018-10-09 15:39:35 +01:00
Sudakshina Das
af4bcb4ce6 [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.

This patch adds the following:
MSR Xn, RNDR
MSR Xn, RNDRRS

These are optional instructions in ARMv8.5-A and hence the new
+rng is added.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_RNG): New.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): New entries for
	rndr and rndrrs.
	(aarch64_sys_reg_supported_p): New check for above.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (aarch64_features): New "rng" option.
	* doc/c-aarch64.texi: Document the same.
	* testsuite/gas/aarch64/sysreg-4.s: Test both instructions.
	* testsuite/gas/aarch64/sysreg-4.d: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
 2018-10-09 15:39:29 +01:00
Sudakshina Das
3fd229a447 [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys)

This patch adds the DC CVADP instruction. Since this has a separate
identification mechanism a new feature bit is added.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
	(aarch64_sys_ins_reg_supported_p): New check for above.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/sysreg-4.s: Test instruction.
	* testsuite/gas/aarch64/sysreg-4.d: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
 2018-10-09 15:39:29 +01:00
Sudakshina Das
2ac435d466 [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)

This patch adds the prediction restriction instructions (that is, cfp,
dvp, cpp). These instructions are retrospectively made optional for
all versions of the architecture from ARMv8.0 to ARMv8.4 and is
mandatory from ARMv8.5. Hence adding a new +predres which can be used
by the older architectures.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
	(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
	(aarch64_sys_regs_sr): Declare new table.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
	AARCH64_OPND_SYSREG_SR.
	* aarch64-opc.c (aarch64_print_operand): Likewise.
	(aarch64_sys_regs_sr): Define table.
	(aarch64_sys_ins_reg_supported_p): Check for RCTX with
	AARCH64_FEATURE_PREDRES.
	* aarch64-tbl.h (aarch64_feature_predres): New.
	(PREDRES, PREDRES_INSN): New.
	(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
	(AARCH64_OPERANDS): Add new description for SYSREG_SR.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
	(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
	(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
	with aarch64_sys_regs_sr.
	(aarch64_features): Add new "predres" option for older
	architectures.
	* doc/c-aarch64.texi: Document the same.
	* testsuite/gas/aarch64/sysreg-4.s: New.
	* testsuite/gas/aarch64/sysreg-4.d: New.
	* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
	* testsuite/gas/aarch64/predres.s: New.
	* testsuite/gas/aarch64/predres.d: New.
 2018-10-09 15:17:10 +01:00
Sudakshina Das
68dfbb92ef [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)

This instruction is retrospectively made optional for all versions of
the architecture from ARMv8.0 to ARMv8.4 and is mandatory from
ARMv8.5.  Hence a new command line option of "+sb" is added for older
architectures.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_SB): New.
	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (aarch64_feature_sb): New.
	(SB, SB_INSN): New.
	(aarch64_opcode_table): Add entry for sb.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add new "sb" option
	for older architectures.
	* doc/c-aarch64.texi: Document the same.
	* testsuite/gas/aarch64/sb.s: New.
	* testsuite/gas/aarch64/sb.d: New.
 2018-10-09 15:11:27 +01:00
Sudakshina Das
13c60ad7e1 [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)

This patch adds the data processing instructions that are new to
ARMv8.5-A.

1) There are 2 instructions: xaflag, axflag, that are added to
manipulate the states of the flag and are used to convert between the
Arm representation and the fcmp representation.

2) The other instructions are rounding instructions which have 8
versions based on whether the floating-point number is a
Single-Precision or Double-Precision number, whether the target
integer is a 32-bit or 64-bit integer and whether the rounding mode is
the ambient rounding mode or to zero. Each of these instruction is
available in both Scalar and Vector forms.

Since both 1) and 2) have separate identification mechanism and it is
permissible that a ARMv8.4 compliant implementation may include any
arbitrary subset of the ARMv8.5 features unless otherwise specified,
new feature bits are added.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New.
	(AARCH64_FEATURE_FRINTTS): New.
	(AARCH64_ARCH_V8_5): Add both by default.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (aarch64_feature_flagmanip): New.
	(aarch64_feature_frintts): New.
	(FLAGMANIP, FRINTTS): New.
	(aarch64_opcode_table): Add entries for xaflag, axflag
	and frint[32,64][x,z] instructions.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/armv8_5-a-dp.s: New.
	* testsuite/gas/aarch64/armv8_5-a-dp.d: New.
 2018-10-09 15:06:52 +01:00
Sudakshina Das
70d561813c [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal feature macros 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)

This is the first of the patch series and adds -march=armv8.5-a and
other internal feature marcos needed for it.

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

    * config/tc-aarch64.c (aarch64_archs): New entry for armv8.5-a.
    * doc/c-aarch64.texi: Add documentation for the same.

*** include/ChnageLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

    * opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
    (AARCH64_ARCH_V8_5): New.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

    * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
    (ARMV8_5, V8_5_INSN): New.
 2018-10-09 15:02:52 +01:00
Alan Modra
64029e9368 Separate header PT_LOAD for -z separate-code 
This patch, along with previous patches in the series, supports
putting the ELF file header and program headers in a PT_LOAD without
sections.

Logic governing whether headers a loaded has changed a little:  The
primary reason to include headers is now the presence of
SIZEOF_HEADERS in a linker script.  However, to support scripts that
may have reserved space for headers by hand, we continue to add
headers whenever the first section address is past the end of headers
modulo page size.

include/
	* bfdlink.h (struct bfd_link_info): Add load_phdrs field.
bfd/
	* elf-nacl.c (nacl_modify_segment_map): Cope with header PT_LOAD
	lacking sections.
	* elf.c (_bfd_elf_map_sections_to_segments): Assume file and
	program headers are required when info->load_phdrs.  Reorganize
	code handling program headers.  Generate a mapping without
	sections just for file and program headers when -z separate-code
	would indicate they should be on a different page to the first
	section.
ld/
	* ldexp.c (fold_name <SIZEOF_HEADERS>): Set link_info.load_phdrs.
	* testsuite/ld-elf/loadaddr1.d: Pass -z noseparate-code.
	* testsuite/ld-elf/loadaddr2.d: Likewise.
	* testsuite/ld-i386/vxworks2.sd: Adjust expected output.
	* testsuite/ld-powerpc/vxworks2.sd: Likewise.
	* testsuite/ld-elf/overlay.d: Remove spu xfail.
	* testsuite/ld-spu/ovl.lnk: Don't use SIZEOF_HEADERS.
	* testsuite/ld-tic6x/dsbt-be.ld: Likewise.
	* testsuite/ld-tic6x/dsbt-inrange.ld: Likewise.
	* testsuite/ld-tic6x/dsbt-overflow.ld: Likewise.
	* testsuite/ld-tic6x/dsbt.ld: Likewise.
 2018-10-08 20:26:08 +10:30
Sudakshina Das
dad0c3bfb5 [Arm, 3/3] Add Execution and Data Prediction instructions for AArch32 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.

(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)

This patch adds the Execution and Data Prediction Restriction
instructions (that is, cfprctx, dvprxtc, cpprctx). These are all
aliases to MCR and are disassembled as such.

This instruction is retrospectively made optional for all versions of
the architecture from ARMv8.0 to ARMv8.4 and is mandatory from
ARMv8.5.  Hence adding a new +predres for older versions of the
architecture.

*** include/ChangeLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* opcode/arm.h (ARM_EXT2_PREDRES): New.
	(ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default.

*** gas/ChangeLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-arm.c (arm_ext_predres): New.
	(insns): Add new cfprctx, dvprctx and cpprctx instructions.
	(arm_extensions): Add "predres".
	* doc/c-arm.texi: Document the above.
	* testsuite/gas/arm/predres-bad.d: New test.
	* testsuite/gas/arm/predres-bad.l: New test.
	* testsuite/gas/arm/predres.s: New test.
	* testsuite/gas/arm/predres1.d: New test.
	* testsuite/gas/arm/predres2.d: New test.
 2018-10-05 11:31:21 +01:00
Sudakshina Das
7fadb25d6f [Arm, 2/3] Add instruction SB for AArch32 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.

(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)

This patch adds the instruction SB. This instruction is
retrospectively made optional for all versions of the architecture
from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a
new "+sb" for older archtectures.

*** include/ChangeLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* opcode/arm.h (ARM_EXT2_SB): New.
	(ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.

*** opcodes/ChangeLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (arm_opcodes): Add sb.
	(thumb32_opcodes): Likewise.

*** gas/ChangeLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-arm.c (arm_ext_sb): New.
	(insns): Add new sb instruction.
	(arm_extensions): Add "sb".
	* doc/c-arm.texi: Document the above.
	* testsuite/gas/arm/sb-bad.d: New test.
	* testsuite/gas/arm/sb-bad.l: New test.
	* testsuite/gas/arm/sb-thumb1.d: New test.
	* testsuite/gas/arm/sb-thumb2.d: New test.
	* testsuite/gas/arm/sb.s: New test.
	* testsuite/gas/arm/sb1.d: New test.
	* testsuite/gas/arm/sb2.d: New test.
 2018-10-05 11:31:19 +01:00
Sudakshina Das
23f233a595 [Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.

(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)

This is the first of the patch series and adds -march=armv8.5-a and
other internal feature marcos needed for it.

*** gas/ChangeLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-arm.c (arm_archs): New entry for armv8.5-a.
	(cpu_arch_ver): Likewise.
	* doc/c-arm.texi: Add documentation for the same.
	* testsuite/gas/arm/attr-march-armv8_5-a.d: New.

*** include/ChnageLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* opcode/arm.h (ARM_EXT2_V8_5A): New.
	(ARM_AEXT2_V8_5A, ARM_ARCH_V8_5A): New.
 2018-10-05 11:31:14 +01:00
Stafford Horne
c8e98e3692 or1k: Add the l.adrp insn and supporting relocations 
This patch adds the new instruction and relocation as per proposal:
   https://openrisc.io/proposals/ladrp

This is to be added to the spec in an upcoming revision.  The new instruction
l.adrp loads the page offset of the current instruction offset by
a 21-bit immediate shifted left 13-bits.  This is meant to be used with
a 13-bit lower bit page offset.  This allows us to free up the got
register r16.

  l.adrp  r3, foo
  l.ori   r4, r3, po(foo)
  l.lbz   r5, po(foo)(r3)
  l.sb    po(foo)(r3), r6

The relocations we add are:

 - BFD_RELOC_OR1K_PLTA26	For PLT jump relocation with PLT entry
   asm: plta()			implemented using l.ardp, meaning
				no need for r16 (the GOT reg)

 - BFD_RELOC_OR1K_GOT_PG21	Upper 21-bit Page offset got address
   asm: got()
 - BFD_RELOC_OR1K_TLS_GD_PG21	Upper 21-bit Page offset with TLS General
   asm: tlsgd()			Dynamic calculation
 - BFD_RELOC_OR1K_TLS_LDM_PG21	Upper 21-bit Page offset with TLS local
   asm: tlsldm()		dynamic calculation
 - BFD_RELOC_OR1K_TLS_IE_PG21	Upper 21-bit Page offset with TLS Initial
   asm: gottp() 		Executable calculation
 - BFD_RELOC_OR1K_PCREL_PG21	Default relocation for disp21 (l.adrp
				instructions)

 - BFD_RELOC_OR1K_LO13		low 13-bit page offset relocation
   asm: po()			i.e. mem loads, addi etc
 - BFD_RELOC_OR1K_SLO13		low 13-bit page offset relocation
   asm: po()			i.e. mem stores, with split immediate
 - BFD_RELOC_OR1K_GOT_LO13,	low 13-bit page offset with GOT calcs
   asm: gotpo()
 - BFD_RELOC_OR1K_TLS_GD_LO13	Lower 13-bit offset with TLS GD calcs
   asm: tlsgdpo()
 - BFD_RELOC_OR1K_TLS_LDM_LO13	Lower 13-bit offset with TLS LD calcs
   asm: tlsldmpo()
 - BFD_RELOC_OR1K_TLS_IE_LO13	Lower 13-bit offset with TLS IE calcs
   asm: gottppo()

bfd/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* bfd-in2.h: Regenerated.
	* elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for
	R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21,
	R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21,
	R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13,
	R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26.
	(or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21,
	BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21,
	BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21,
	BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13,
	BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13,
	BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13,
	BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26.
	(elf_or1k_link_hash_table): Add field saw_plta.
	(or1k_final_link_relocate): Add value calculations for new relocations.
	(or1k_elf_relocate_section): Add section relocations for new
	relocations.
	(or1k_write_plt_entry): New function.
	(or1k_elf_finish_dynamic_sections): Add support for PLTA relocations
	using new l.adrp instruction.  Cleanup PLT relocation code generation.
	* libbfd.h: Regenerated.
	* reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13,
	BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13,
	BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21,
	BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
	BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
	BFD_RELOC_OR1K_TLS_IE_LO13.

cpu/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* or1k.opc (parse_disp26): Add support for plta() relocations.
	(parse_disp21): New function.
	(or1k_rclass): New enum.
	(or1k_rtype): New enum.
	(or1k_imm16_relocs): Define new PO and SPO relocation mappings.
	(parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
	(parse_imm16): Add support for the new 21bit and 13bit relocations.
	* or1korbis.cpu (f-disp26): Don't assume SI.
	(f-disp21): New pc-relative 21-bit 13 shifted to right.
	(insn-opcode): Add ADRP.
	(l-adrp): New instruction.

gas/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21,
	BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
	BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
	BFD_RELOC_OR1K_TLS_IE_LO13.
	* testsuite/gas/or1k/allinsn.s: Add test for l.adrp.
	* testsuite/gas/or1k/allinsn.d: Add test results for new
	instructions.
	* testsuite/gas/or1k/reloc-1.s: Add tests to generate
	R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
	R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13,
	R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13
	relocations.
	* testsuite/gas/or1k/reloc-1.d: Add relocation results for
	tests.
	* testsuite/gas/or1k/reloc-2.s: Add negative tests for store to
	gotpo().
	* testsuite/gas/or1k/reloc-2.l: Add expected error test results.

ld/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* testsuite/ld-or1k/or1k.exp: Add test cases for plt generation.
	* testsuite/ld-or1k/plt1.dd: New file.
	* testsuite/ld-or1k/plt1.s: New file.
	* testsuite/ld-or1k/plt1.x.dd: New file.
	* testsuite/ld-or1k/plta1.dd: New file.
	* testsuite/ld-or1k/plta1.s: New file.
	* testsuite/ld-or1k/pltlib.s: New file.

include/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
	R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
	R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
	R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
	R_OR1K_SLO13, R_OR1K_PLTA26.

opcodes/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* or1k-asm.c: Regenerated.
	* or1k-desc.c: Regenerated.
	* or1k-desc.h: Regenerated.
	* or1k-dis.c: Regenerated.
	* or1k-ibld.c: Regenerated.
	* or1k-opc.c: Regenerated.
	* or1k-opc.h: Regenerated.
	* or1k-opinst.c: Regenerated.
 2018-10-05 11:41:41 +09:00
Richard Henderson
1c4f3780f7 or1k: Add relocations for high-signed and low-stores 
This patch adds the following target relocations:

 - BFD_RELOC_HI16_S		High 16-bit relocation, for used with signed
   asm: ha()			lower.
 - BFD_RELOC_HI16_S_GOTOFF	High 16-bit GOT offset relocation for local
   asm: gotoffha()		symbols, for use with signed lower.
 - BFD_RELOC_OR1K_TLS_IE_AHI16	High 16-bit TLS relocation with initial
   asm: gottpoffha()		executable calculation, for use with signed
				lower.
 - BFD_RELOC_OR1K_TLS_LE_AHI16	High 16-bit TLS relocation for local executable
   asm: tpoffha()		variables, for use with signed lower.

 - BFD_RELOC_OR1K_SLO16		Split lower 16-bit relocation, used with
   asm: lo()			OpenRISC store instructions.
 - BFD_RELOC_OR1K_GOTOFF_SLO16	Split lower 16-bit GOT offset relocation for
   asm: gotofflo()		local symbols, used with OpenRISC store
				instructions.
 - BFD_RELOC_OR1K_TLS_LE_SLO16	Split lower 16-bit relocation for TLS local
   asm: tpofflo()		executable variables, used with OpenRISC store
				instructions.

bfd/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>
	    Stafford Horne  <shorne@gmail.com>

	* bfd-in2.h: Regenerated.
	* elf32-or1k.c (N_ONES): New macro.
	(or1k_elf_howto_table): Fix R_OR1K_PLT26 to complain on overflow.
	Add definitions for R_OR1K_TLS_TPOFF, R_OR1K_TLS_DTPOFF,
	R_OR1K_TLS_DTPMOD, R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16,
	R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16,
	R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
	(or1k_reloc_map): Add entries for BFD_RELOC_HI16_S,
	BFD_RELOC_LO16_GOTOFF, BFD_RELOC_HI16_GOTOFF, BFD_RELOC_HI16_S_GOTOFF,
	BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
	BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16,
	BFD_RELOC_OR1K_TLS_LE_SLO16.
	(or1k_reloc_type_lookup): Change search loop to start ad index 0 and
	also check results before returning.
	(or1k_reloc_name_lookup): Simplify loop to use R_OR1K_max as index
	limit.
	(or1k_final_link_relocate): New function.
	(or1k_elf_relocate_section): Add support for new AHI and SLO
	relocations.  Use or1k_final_link_relocate instead of generic
	_bfd_final_link_relocate.
	(or1k_elf_check_relocs): Add support for new AHI and SLO relocations.
	* reloc.c: Add new enums for BFD_RELOC_OR1K_SLO16,
	BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_IE_AHI16,
	BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
	BFD_RELOC_OR1K_TLS_LE_SLO16.  Remove unused BFD_RELOC_OR1K_GOTOFF_HI16
	and BFD_RELOC_OR1K_GOTOFF_LO16.
	* libbfd.h: Regenerated.

cpu/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* or1k.opc: Add RTYPE_ enum.
	(INVALID_STORE_RELOC): New string.
	(or1k_imm16_relocs): New array array.
	(parse_reloc): New static function that just does the parsing.
	(parse_imm16): New static function for generic parsing.
	(parse_simm16): Change to just call parse_imm16.
	(parse_simm16_split): New function.
	(parse_uimm16): Change to call parse_imm16.
	(parse_uimm16_split): New function.
	* or1korbis.cpu (simm16-split): Change to use new simm16_split.
	(uimm16-split): Change to use new uimm16_split.

gas/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* testsuite/gas/or1k/allinsn.d (l_ha): Add result for ha() relocation.
	* testsuite/gas/or1k/allinsn.s (l_ha): Add test for ha() relocations.
	* testsuite/gas/or1k/allinsn.exp: Renamed to or1k.exp.
	* testsuite/gas/or1k/or1k.exp: Add reloc-2 list test.
	* testsuite/gas/or1k/reloc-1.d: New file.
	* testsuite/gas/or1k/reloc-1.s: New file.
	* testsuite/gas/or1k/reloc-2.l: New file.
	* testsuite/gas/or1k/reloc-2.s: New file.

include/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
	R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
	R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.

ld/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* testsuite/ld-or1k/offsets1.d: New file.
	* testsuite/ld-or1k/offsets1.s: New file.
	* testsuite/ld-or1k/or1k.exp: New file.

opcodes/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* or1k-asm.c: Regenerate.
 2018-10-05 11:41:40 +09:00
Tamar Christina
a68f4cd235 AArch64: Add SVE constraints verifier. 
This patch adds the verification rules for move prefix constraints.

The Arm SVE instruction MOVPRFX introduces[1] constraints on the instruction at
PC+4. Particularly the following constraints are handled by this patch

* MOVPRFX must be followed by an instruction.
* MOVPRFX can only be followed by non-layout altering directives.
* MOVPRFX destination register MUST be used as the destination register in the
  instruction at PC+4, and is not allowed to be used in any other position other than
  destructive input.  This includes registers that architecturally overlap. e.g. x1
  should be treated as z1.
* MOVPRFX must be followed by a restricted set of SVE instructions.
* The size of the destination register of MOVPRFX must be equal to that of
  the operation at PC+4.
* The predicate register and operation of MOVPRFX must match that of the instruction
  at PC+4
* The predicated instruction at PC+4 must use the merging predicate.
* Architectural aliases and pseudo-instructions need to be supported as well.
* MOVPRFX cannot be the last instruction in a sequence

Any failure to adhere to any of these constrains will emit an assembly warning
and a disassembly note.

[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a

include/

	* opcode/aarch64.h (aarch64_inst): Remove.
	(enum err_type): Add ERR_VFI.
	(aarch64_is_destructive_by_operands): New.
	(init_insn_sequence): New.
	(aarch64_decode_insn): Remove param name.

opcodes/

	* aarch64-opc.c (init_insn_block): New.
	(verify_constraints, aarch64_is_destructive_by_operands): New.
	* aarch64-opc.h (verify_constraints): New.

gas/

        * config/tc-aarch64.c (output_operand_error_report): Order warnings.
 2018-10-03 18:49:37 +01:00
Tamar Christina
755b748fd9 AArch64: Refactor verifiers to make more general. 
The current verifiers only take an instruction description and encoded value as
arguments.  This was enough when the verifiers only needed to do simple checking
but it's insufficient for the purposes of validating instruction sequences.

This patch adds the required arguments and also a flag to allow a verifier to
distinguish between whether it's being run during encoding or decoding.  It also
allows for errors and warnings to be returned by a verifier instead of a simple
pass/fail.

include/

	* opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take
	more arguments.

opcodes/

	* aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
	* aarch64-opc.c (verify_ldpsw): Update arguments.
 2018-10-03 18:40:48 +01:00
Tamar Christina
1d4823943d AArch64: Refactor err_type. 
Previously the ERR_ values were defined as different constants, to make this a
bit more type safe and so they can be more easily re-used I'm changing them into
an actual enum and updating any usages.

include/

	* opcode/aarch64.h (enum err_type): New.
	(aarch64_decode_insn): Use it.

opcodes/

	* aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
	(aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 2018-10-03 18:36:30 +01:00
Tamar Christina
7e84b55d8f AArch64: Wire through instr_sequence 
This patch introduces aarch64_instr_sequence which is a structure similar to IT
blocks on Arm in order to track instructions that introduce a constraint or
dependency on instruction 1..N positions away from the instruction that opened
the block.

The struct is also wired through to the locations that require it.

gas/

	* config/tc-aarch64.c (now_instr_sequence):
	(*insn_sequence, now_instr_sequence): New.
	(output_operand_error_record, do_encode): Add insn_sequence.
	(md_assemble): Update insn_sequence.
	(try_to_encode_as_unscaled_ldst, fix_mov_imm_insn, fix_insn):
	Pass insn_sequence.
	* config/tc-aarch64.h (struct aarch64_segment_info_type):
	Add insn_sequence.

include/

	* opcode/aarch64.h (struct aarch64_instr_sequence): New.
	(aarch64_opcode_encode): Use it.

opcodes/

	* aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
	* aarch64-dis.c (insn_sequence): New.
 2018-10-03 18:33:33 +01:00
Tamar Christina
eae424aef0 AArch64: Mark sve instructions that require MOVPRFX constraints 
This patch series is to allow certain instructions such as the SVE MOVPRFX
instruction to apply a constraint/dependency on the instruction at PC+4.

This patch starts this off by marking which instructions impose the constraint
and which instructions must adhere to the constraint.  This is done in a
generic way by extending the verifiers.

* The constraint F_SCAN indicates that an instruction opens a sequence and imposes
a constraint on an instructions following it.  The length of the sequence depends
on the instruction itself and it handled in the verifier code.

* The C_SCAN_MOVPRFX flag is used to indicate which constrain the instruction is
checked against.  An instruction with both F_SCAN and C_SCAN_MOVPRFX starts a
block for the C_SCAN_MOVPRFX instruction, and one with only C_SCAN_MOVPRFX must
adhere to a previous block constraint is applicable.

The SVE instructions in this list have been marked according to the SVE
specification[1].

[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a

include/

	* opcode/aarch64.h (struct aarch64_opcode): Add constraints,
	extend flags field size.
	(F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.

opcodes/

	* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
	_LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
	_SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
	V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
	constraints.
	(_SVE_INSNC): New.
	(struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
	constraints.
	(movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
	F_SCAN flags.
	(msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
	sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
	sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
	sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
	uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
	uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
	C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 2018-10-03 18:24:17 +01:00
John Darrington
007d2fe43e Make print_insn_s12z public. 
Gdb can use this function in its stack unwinder.

* include/dis-asm.h (print_insn_s12z): Add declaration.
 2018-10-03 10:43:02 +02:00
Palmer Dabbelt
64a336ac13
RISC-V: Add fence.tso instruction 
The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso".  This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.

I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets.  I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.

gas/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * testsuite/gas/riscv/fence-tso.d: New file.
        * testsuite/gas/riscv/fence-tso.s: Likewise.

include/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
        (MASK_FENCE_TSO): Likewise.

opcodes/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 2018-10-02 08:26:32 -07:00
Cupertino Miranda
eb528ad18b [ARC] Entries to Changelog for previous commits. 2018-10-02 09:20:11 +01:00
H.J. Lu
95475e5d6b ELF: Don't include zero size sections at start of PT_NOTE segment 
We shouldn't include zero size sections at start of PT_NOTE segment,
similar to PT_DYNAMIC segment.

	PR binutils/23694
	* include/elf/internal.h (ELF_SECTION_IN_SEGMENT_1): Don't
	include zero size sections at start of PT_NOTE segment.
 2018-09-21 04:08:01 -07:00
Nick Clifton
fbaf61ad52 Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream! 
We have not only removed all unsupported and obsolete code, but also supported lost of new features,
including better link-time relaxations and TLS implementations. Besides, the files generated by the
newly assembler and linker usually get higher performance and more optimized code size.

ld	* emultempl/nds32elf.em (hyper_relax): New variable.
	(nds32_elf_create_output_section_statements):
	the parameters of bfd_elf32_nds32_set_target_option
	(PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
	PARSE_AND_LIST_ARGS_CASES): Add new option --mhyper-relax.
	* emultempl/nds32elf.em (nds32_elf_after_open): Updated.
	* emultempl/nds32elf.em (tls_desc_trampoline): New variable.
	* (nds32_elf_create_output_section_statements): Updated.
	* (nds32_elf_after_parse): Disable relaxations when PIC is enable.
	* (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
	PARSE_AND_LIST_ARGS_CASES): Add new option --m[no-]tlsdesc-trampoline.

include	* elf/nds32.h: Remove the unused target features.
	* dis-asm.h (disassemble_init_nds32): Declared.
	* elf/nds32.h (E_NDS32_NULL): Removed.
	(E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
	* opcode/nds32.h: Ident.
	(N32_SUB6, INSN_LW): New macros.
	(enum n32_opcodes): Updated.
	* elf/nds32.h: Doc fixes.
	* elf/nds32.h: Add R_NDS32_LSI.
	* elf/nds32.h: Add new relocations for TLS.

gas 	* config/tc-nds32.c: Remove the unused target features.
	(nds32_relax_relocs, md_pseudo_table, nds32_elf_record_fixup_exp,
	nds32_set_elf_flags_by_insn, nds32_insert_relax_entry,
	nds32_apply_fix): Likewise.
	(nds32_no_ex9_begin): Removed.
	* config/tc-nds32.c (add_mapping_symbol_for_align,
	make_mapping_symbol, add_mapping_symbol): New functions.
	* config/tc-nds32.h (enum mstate): New.
	(nds32_segment_info_type): Likewise.
	* configure.ac (--enable-dsp-ext, --enable-zol-ext): New options.
	* config.in: Regenerated.
	* configure: Regenerated.
	* config/tc-nds32.c (nds32_dx_regs):
	Set the value according to the configuration.
	(nds32_perf_ext, nds32_perf_ext2, nds32_string_ext, nds32_audio_ext):
	Likewise.
	(nds32_dsp_ext): New variable. Set the value according to the
	configuration.
	(nds32_zol_ext): Likewise.
	(asm_desc, nds32_pseudo_opcode_table): Make them static.
	(nds32_set_elf_flags_by_insn): Updated.
	(nds32_check_insn_available): Updated.
	(nds32_str_tolower): New function.
	* config/tc-nds32.c (relax_table): Updated.
	(md_begin): Updated.
	(md_assemble): Use XNEW macro to allocate space for `insn.info',
	and then remember to free it.
	(md_section_align): Cast (-1) to ValueT.
	(nds32_get_align): Cast (~0U) to addressT.
	(nds32_relax_branch_instructions): Updated.
	(md_convert_frag): Add new local variable `final_r_type'.
	(invalid_prev_frag): Add new bfd_boolean parameter `relax'.
	All callers changed.
	* config/tc-nds32.c (struct nds32_relocs_pattern): Add `insn' field.
	(struct nds32_hint_map): Add `option_list' field.
	(struct suffix_name, suffix_table): Remove the unused `pic' field.
	(do_pseudo_b, do_pseudo_bal): Remove the suffix checking.
	(do_pseudo_la_internal, do_pseudo_pushpopm): Indent.
	(relax_hint_bias, relax_hint_id_current): New static variables.
	(reset_bias, relax_hint_begin): New variables.
	(nds_itoa): New function.
	(CLEAN_REG, GET_OPCODE): New macros.
	(struct relax_hint_id): New.
	(nds32_relax_hint): For .relax_hint directive, we can use `begin'
	and `end' to mark the relax pattern without giving exactly id number.
	(nds32_elf_append_relax_relocs): Handle the case that the .relax_hint
	directives are attached to pseudo instruction.
	(nds32_elf_save_pseudo_pattern): Change the second parameter from
	instruction's opcode to byte code.
	(nds32_elf_build_relax_relation): Add new bfd_boolean parameter
	`pseudo_hint'.
	(nds32_lookup_pseudo_opcode): Fix the overflow issue.
	(enum nds32_insn_type): Add N32_RELAX_ALU1 and N32_RELAX_16BIT.
	(nds32_elf_record_fixup_exp, relax_ls_table, hint_map,
	nds32_find_reloc_table, nds32_match_hint_insn, nds32_parse_name):
	Updated.
	* config/tc-nds32.h (MAX_RELAX_NUM): Extend it to 6.
	(enum nds32_relax_hint_type): Merge NDS32_RELAX_HINT_LA and
	NDS32_RELAX_HINT_LS into NDS32_RELAX_HINT_LALS. Add
	NDS32_RELAX_HINT_LA_PLT, NDS32_RELAX_HINT_LA_GOT and
	NDS32_RELAX_HINT_LA_GOTOFF.
	* config/tc-nds32.h (relax_ls_table): Add floating load/store
	to gp relax pattern.
	(hint_map, nds32_find_reloc_table): Likewise.
	* configure.ac: Define NDS32_LINUX_TOOLCHAIN.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-nds32.h (enum nds32_ramp): Updated.
	(enum nds32_relax_hint_type): Likewise.
	* config/tc-nds32.c: Include "errno.h" and "limits.h".
	(relax_ls_table): Add TLS relax patterns.
	(nds32_elf_append_relax_relocs): Attach BFD_RELOC_NDS32_GROUP on
	each instructions of TLS patterns.
	(nds32_elf_record_fixup_exp): Updated.
	(nds32_apply_fix): Likewise.
	(suffix_table): Add TLSDESC suffix.

binutils* testsuite/binutils-all/objcopy.exp: Set the unsupported reloc number
	from 215 to 255 for NDS32.

bfd	* elf32-nds32.c (nds32_elf_relax_loadstore):
	Remove the unused target features.
	(bfd_elf32_nds32_set_target_option): Remove the unused parameters.
	(nds32_elf_relax_piclo12, nds32_elf_relax_letlslo12,
	nds32_elf_relax_letlsadd, nds32_elf_relax_letlsls,
	nds32_elf_relax_pltgot_suff, nds32_elf_relax_got_suff
	nds32_elf_relax_gotoff_suff, calculate_plt_memory_address,
	calculate_plt_offset, calculate_got_memory_address,
	nds32_elf_check_dup_relocs): Removed.
	All callers changed.
	* elf32-nds32.h: Remove the unused macros and defines.
	(elf_nds32_link_hash_table): Remove the unused variable.
	(bfd_elf32_nds32_set_target_option): Update prototype.
	(nds32_elf_ex9_init): Removed.
	* elf32-nds32.c (nds32_convert_32_to_16): Updated.
	* elf32-nds32.c (HOWTO2, HOWTO3): Define new HOWTO macros
	to initialize array nds32_elf_howto_table in any order
	without lots of EMPTY_HOWTO.
	(nds32_reloc_map): Updated.
	* reloc.c: Add BFD_RELOC_NDS32_LSI.
	* bfd-in2.h: Regenerated.
	* bfd/libbfd.h: Regenerated.
	* elf32-nds32.c (nds32_elf_relax_howto_table): Add R_NDS32_LSI.
	(nds32_reloc_map): Likewise.
	(nds32_elf_relax_flsi): New function.
	(nds32_elf_relax_section): Support floating load/store relaxation.
	* elf32-nds32.c (NDS32_GUARD_SEC_P, elf32_nds32_local_gp_offset):
	New macro.
	(struct elf_nds32_link_hash_entry): New `offset_to_gp' field.
	(struct elf_nds32_obj_tdata): New `offset_to_gp' and `hdr_size' fields.
	(elf32_nds32_allocate_local_sym_info, nds32_elf_relax_guard,
	nds32_elf_is_target_special_symbol, nds32_elf_maybe_function_sym):
	New functions.
	(nds32_info_to_howto_rel): Add BFD_ASSERT.
	(bfd_elf32_bfd_reloc_type_table_lookup, nds32_elf_link_hash_newfunc,
	nds32_elf_link_hash_table_create, nds32_elf_relocate_section,
	nds32_elf_relax_loadstore, nds32_elf_relax_lo12, nds32_relax_adjust_label,
	bfd_elf32_nds32_set_target_option, nds32_fag_mark_relax): Updated.
	(nds32_elf_final_sda_base): Improve it to find the better gp value.
	(insert_nds32_elf_blank): Must consider `len' when inserting blanks.
	* elf32-nds32.h (bfd_elf32_nds32_set_target_option): Update prototype.
	(struct elf_nds32_link_hash_table): Add new variable `hyper_relax'.
	* elf32-nds32.c (elf32_nds32_allocate_dynrelocs): New function.
	(create_got_section): Likewise.
	(allocate_dynrelocs, nds32_elf_size_dynamic_sections,
	nds32_elf_relocate_section, nds32_elf_finish_dynamic_symbol): Updated.
	(nds32_elf_check_relocs): Fix the issue that the shared library may
	has TEXTREL entry in the dynamic section.
	(nds32_elf_create_dynamic_sections): Enable to call readonly_dynrelocs
	since the TEXTREL issue is fixed in the nds32_elf_check_relocs.
	(nds32_elf_finish_dynamic_sections): Update and add DT_RELASZ
	dynamic entry.
	(calculate_offset): Remove the unused parameter `pic_ext_target' and
	related codes.
	All callers changed.
	(elf_backend_dtrel_excludes_plt): Disable it temporarily since it
	will cause some errors for our test cases.
	* elf32-nds32.c (nds32_elf_merge_private_bfd_data): Allow to link the
	generic object.
	* reloc.c: Add TLS relocations.
	* libbfd.h: Regenerated.
	* bfd-in2.h: Regenerated.
	* elf32-nds32.h (struct section_id_list_t): New.
	(elf32_nds32_lookup_section_id, elf32_nds32_check_relax_group,
	elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model):
	New prototypes.
	(elf32_nds32_compute_jump_table_size, elf32_nds32_local_tlsdesc_gotent):
	New macro.
	(nds32_insertion_sort, bfd_elf32_nds32_set_target_option,
	elf_nds32_link_hash_table): Updated.
	* elf32-nds32.c (enum elf_nds32_tls_type): New.
	(struct elf32_nds32_relax_group_t, struct relax_group_list_t): New.
	(elf32_nds32_add_dynreloc, patch_tls_desc_to_ie, get_tls_type,
	fls, ones32, list_insert, list_insert_sibling, dump_chain,
	elf32_nds32_check_relax_group, elf32_nds32_lookup_section_id,
	elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New functions.
	(elf_nds32_obj_tdata): Add new fields.
	(elf32_nds32_relax_group_ptr, nds32_elf_local_tlsdesc_gotent): New macros.
	(nds32_elf_howto_table): Add TLS relocations.
	(nds32_reloc_map): Likewise.
	(nds32_elf_copy_indirect_symbol, nds32_elf_size_dynamic_sections,
	nds32_elf_finish_dynamic_symbol, elf32_nds32_allocate_local_sym_info,
	nds32_elf_relocate_section, bfd_elf32_nds32_set_target_option,
	nds32_elf_check_relocs, allocate_dynrelocs): Updated.
	(nds32_elf_relax_section): Call nds32_elf_unify_tls_model.
	(dtpoff_base): Rename it to `gottpof' and then update it.

opcodes	* nds32-asm.c (operand_fields): Remove the unused fields.
	(nds32_opcodes): Remove the unused instructions.
	* nds32-dis.c (nds32_ex9_info): Removed.
	(nds32_parse_opcode): Updated.
	(print_insn_nds32): Likewise.
	* nds32-asm.c (config.h, stdlib.h, string.h): New includes.
	(LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
	(nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
	build_opcode_hash_table): New functions.
	(nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
	nds32_opcode_table): New.
	(hw_ktabs): Declare it to a pointer rather than an array.
	(build_hash_table): Removed.
	* nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
	SYN_ROPT and upadte HW_GPR and HW_INT.
	* nds32-dis.c (keywords): Remove const.
	(match_field): New function.
	(nds32_parse_opcode): Updated.
	* disassemble.c (disassemble_init_for_target):
	Add disassemble_init_nds32.
	* nds32-dis.c (eum map_type): New.
	(nds32_private_data): Likewise.
	(get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
	nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
	(print_insn_nds32): Updated.
	* nds32-asm.c (parse_aext_reg): Add new parameter.
	(parse_re, parse_re2, parse_aext_reg): Only reduced registers
	are allowed to use.
	All callers changed.
	* nds32-asm.c (keyword_usr, keyword_sr): Updated.
	(operand_fields): Add new fields.
	(nds32_opcodes): Add new instructions.
	(keyword_aridxi_mx): New keyword.
	* nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
	and NASM_ATTR_ZOL.
	(ALU2_1, ALU2_2, ALU2_3): New macros.
	* nds32-dis.c (nds32_filter_unknown_insn): Updated.
 2018-09-20 13:32:58 +01:00
Rainer Orth
3d282ac370 Handle missing Solaris auxv entries 
Currently, three tests FAIL on Solaris 11.4+ (amd64-pc-solaris2.11 and
sparcv9-sun-solaris2.11):

info auxv
[...]
2009 AT_SUN_HWCAP         Machine-dependent CPU capability hints 0x3f5ff7
2023 ???                                                 0x0
0    AT_NULL              End of vector                  0x0
(gdb) WARNING: Unrecognized tag value: 2023 ???  0x0

FAIL: gdb.base/auxv.exp: info auxv on live process

info auxv
4294969310 ???                                                 0x7fffbfffe410
9225589753816 ???                                                 0x7fffbfffe45c
[...]
WARNING: Unrecognized tag value: 4294969310 ???  0x7fffbfffe410

WARNING: Unrecognized tag value: 9225589753816 ???  0x7fffbfffe45c

WARNING: Unrecognized tag value: 140733193388037 ???  0x6
[...]
2009 AT_SUN_HWCAP         Machine-dependent CPU capability hints 0x3f5ff7
2023 ???                                                 0x0
0    AT_NULL              End of vector                  0x0
(gdb) WARNING: Unrecognized tag value: 2023 ???  0x0

UNRESOLVED: gdb.base/auxv.exp: info auxv on native core dump

info auxv
[...]
2009 AT_SUN_HWCAP         Machine-dependent CPU capability hints 0x3f5ff7
2023 ???                                                 0x0
0    AT_NULL              End of vector                  0x0
(gdb) WARNING: Unrecognized tag value: 2023 ???  0x0

FAIL: gdb.base/auxv.exp: info auxv on gcore-created dump

The following patch fixes this by introducing the missing AT_SUN_*
values from Solaris 11.4+ <sys/auxv.h>.  This lets the live and
gcore-created dump tests PASS.

I don't know yet what's the reason for those weird 'Unrecognized tag
value' warnings with native core dumps is; elfdump -n certainly doesn't
show them.  However, native core dumps still need quite some work
(mostly in bfd) in this and other areas.

Tested on amd64-pc-solaris2.11.

	gdb:
	* auxv.c (default_print_auxv_entry): Reflect AT_SUN_CAP_HW1
	renaming.
	Handle AT_SUN_EMULATOR, AT_SUN_BRANDNAME, AT_SUN_BRAND_AUX1,
	AT_SUN_BRAND_AUX2, AT_SUN_BRAND_AUX3, AT_SUN_CAP_HW2.

	include:
	* elf/common.h (AT_SUN_HWCAP): Rename to ...
	(AT_SUN_CAP_HW1): ... this.  Retain old name for backward
	compatibility.
	(AT_SUN_EMULATOR, AT_SUN_BRANDNAME, AT_SUN_BRAND_AUX1)
	(AT_SUN_BRAND_AUX2, AT_SUN_BRAND_AUX3, AT_SUN_CAP_HW2): Define.
 2018-09-20 10:23:46 +02:00
Simon Marchi
af39b1c216 Disable -Wformat-nonliteral in parts of printcmd.c 
commit 3322c5d9a1 ("Remove unneeded explicit .o targets") broke the
build with clang, because -Wno-format-nonliteral was in fact needed.
This patch fixes the problem by introducing
DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL and using it in printcmd.c.  This
seems preferable to reverting the patch because now the warning
suppression is more targeted.

gdb/ChangeLog
2018-09-05  Simon Marchi  <simon.marchi@ericsson.com>

	* printcmd.c (printf_c_string): Use
	DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL.
	(printf_wide_c_string, printf_pointer, ui_printf): Likewise.

include/ChangeLog
2018-09-05  Simon Marchi  <simon.marchi@ericsson.com>

	* diagnostics.h (DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL): New macro.
 2018-09-05 21:47:33 -06:00
Alan Modra
4a9699735b PowerPC64 higher REL16 relocations 
There are occasions where someone might want to build a 64-bit
pc-relative offset from 16-bit pieces.  This adds the necessary REL16
relocs corresponding to existing ADDR16 relocs that can be used to
build 64-bit absolute values.

include/
	* elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
	(R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
	(R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
	(R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
bfd/
	* reloc.c (BFD_RELOC_PPC64_REL16_HIGH, BFD_RELOC_PPC64_REL16_HIGHA),
	(BFD_RELOC_PPC64_REL16_HIGHER, BFD_RELOC_PPC64_REL16_HIGHERA),
	(BFD_RELOC_PPC64_REL16_HIGHEST, BFD_RELOC_PPC64_REL16_HIGHESTA):
	Define.
	* elf64-ppc.c (ppc64_elf_howto_raw): Add new REL16 howtos.
	(ppc64_elf_reloc_type_lookup): Translate new REL16 relocs.
	(ppc64_elf_check_relocs, ppc64_elf_relocate_section): Handle them.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
gas/
	* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Allow ADDR16
	HIGH, HIGHA, HIGHER, HIGHERA, HIGHEST, and HIGHESTA relocs.
	Group 16-bit relocs.
	* config/tc-ppc.c (md_apply_fix): Translate those ADDR16 relocs
	to REL16 when pcrel.  Sort relocs.
 2018-08-31 22:15:05 +09:30
Jim Wilson
43135d3b15 RISC-V: Allow instruction require more than one extension 
2018-08-29  Kito Cheng  <kito@andestech.com>

gas/
	* config/tc-riscv.c (riscv_subset_supports): New argument:
	xlen_required.
	(riscv_multi_subset_supports): New function, able to check more
	than one extension.
	(riscv_ip): Use riscv_multi_subset_supports instead of
	riscv_subset_supports.
	(riscv_set_arch): Update call-site for riscv_subset_supports.
	(riscv_after_parse_args): Likewise.

include/
	*opcode/riscv.h (MAX_SUBSET_NUM): New.
	(riscv_opcode): Add xlen_requirement field and change type of
	subset.

opcodes/
	* riscv-dis.c (riscv_disassemble_insn): Check XLEN by
	riscv_opcode.xlen_requirement.
	* riscv-opc.c (riscv_opcodes): Update for struct change.
 2018-08-30 13:23:12 -07:00
Chenghua Xu
9108bc33b1 [MIPS] Add Loongson 2K1000 proccessor support. 
bfd/
	* archures.c (bfd_architecture): New machine
	bfd_mach_mips_gs264e.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle
	E_MIPS_MACH_GS264E.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Map bfd_mach_mips_gs264e to
	bfd_mach_mips_gs464e extension.

binutils/
	* NEWS: Mention Loongson 2K1000 proccessor support.
	* readelf.c (get_machine_flags): Handle gs264e.

elfcpp/
	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
	(mips_cpu_info_table): Add gs264e descriptors.
	* doc/as.texi (march table): Add gs264e.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
	* opcode/mips.h (CPU_XXX): New CPU_GS264E.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
	gs264e and gs464e.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 2018-08-29 20:55:25 +08:00
Chenghua Xu
bd782c07b9 [MIPS] Add Loongson 3A2000/3A3000 proccessor support. 
bfd/
	* archures.c (bfd_architecture): New machine
	bfd_mach_mips_gs464e.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle
	E_MIPS_MACH_GS464E.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Map bfd_mach_mips_gs464e to
	bfd_mach_mips_gs464 extension.

binutils/
	* NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
	* readelf.c (get_machine_flags): Handle gs464e.

elfcpp/
	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
	(mips_cpu_info_table): Add gs464e descriptors.
	* doc/as.texi (march table): Add gs464e.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
	* opcode/mips.h (CPU_XXX): New CPU_GS464E.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
	gs464e and gs464.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 2018-08-29 20:43:19 +08:00
Chenghua Xu
ac8cb70f36 [MIPS] Add Loongson 3A1000 proccessor support. 
bfd/
	* archures.c (bfd_architecture): Rename
	bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Likewise.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Likewise.
	(bfd_mips_isa_ext_mach): Likewise.
	(bfd_mips_isa_ext): Likewise.
	(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.

binutils/
	* NEWS: Mention Loongson 3A1000 proccessor support.
	* readelf.c (get_machine_flags): Rename loongson-3a to gs464.
	(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.

elfcpp/
	* mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to
	E_MIPS_MACH_GS464.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename
	CPU_LOONGSON_3A to CPU_GS464.
	(mips_cpu_info_table): Add gs464 descriptors, Keep
	loongson3a as an alias of gs464 for compatibility.
	* doc/as.texi (march table): Rename loongson3a to gs464.
	* testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension"
	flag to None.

gold/
	* mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach):
	Rename loongson3a to gs464.
	(mips_isa_ext_mach, mips_isa_ext): Delete loongson3a.
	(infer_abiflags): Use ases instead of isa_ext for infer ABI
flags.
	(elf_mips_mach_name): Rename loongson3a to gs464.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
	E_MIPS_MACH_GS464.
	(AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
	* opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
	(CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
	* opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a
	to gs464.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
	loongson3a as an alias of gs464 for compatibility.
	* mips-opc.c (mips_opcodes): Change Comments.
 2018-08-29 20:32:30 +08:00
Chenghua Xu
a693765e23 [MIPS/GAS] Add Loongson EXT2 Instructions support. 
bfd/
	* elfxx-mips.c (print_mips_ases): Add Loongson EXT2 extension.

binutils/
	* readelf.c (print_mips_ases): Add Loongson EXT2 extension.

gas/
	* NEWS: Mention Loongson EXTensions R2 (EXT2) support.
	* config/tc-mips.c (options): Add OPTION_LOONGSON_EXT2 and
	OPTION_NO_LOONGSON_EXT2.
	(md_longopts): Likewise.
	(mips_ases): Define availability for EXT.
	(mips_convert_ase_flags): Map ASE_LOONGSON_EXT2 to
	AFL_ASE_LOONGSON_EXT2.
	(md_show_usage): Add help for -mloongson-ext2 and
	-mno-loongson-ext2.
	* doc/as.texi: Document -mloongson-ext2, -mno-loongson-ext2.
	* doc/c-mips.texi: Document -mloongson-ext2, -mno-loongson-ext2,
	.set loongson-ext2 and .set noloongson-ext2.
	* testsuite/gas/mips/loongson-ext2.d: New test.
	* testsuite/gas/mips/loongson-ext2.s: New test.
	* testsuite/gas/mips/mips.exp: Run loongson-ext2 test.

include/
	* elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
	* opcode/mips.h (ASE_LOONGSON_EXT2): New macro.

opcodes/
	* mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
	option.
	(print_mips_disassembler_options): Document -M loongson-ext.
	* mips-opc.c (LEXT2): New macro.
	(mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 2018-08-29 20:08:58 +08:00
Chenghua Xu
bdc6c06e3b [MIPS/GAS] Split Loongson EXT Instructions from loongson3a. 
bfd/
	 * elfxx-mips.c (infer_mips_abiflags): Use ases instead of
	 isa_ext for infer ABI flags.
	 (print_mips_ases): Add Loongson EXT extension.

binutils/
	 * readelf.c (print_mips_ases): Add Loongson EXT extension.

elfcpp/
	 * mips.h (AFL_ASE_LOONGSON_EXT): New enum.

gas/
	 * NEWS: Mention Loongson EXTensions (EXT) support.
	 * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and
	 OPTION_NO_LOONGSON_EXT.
	 (md_longopts): Likewise.
	 (mips_ases): Define availability for EXT.
	 (mips_convert_ase_flags): Map ASE_LOONGSON_EXT to
	 AFL_ASE_LOONGSON_EXT.
	 (mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a.
	 (md_show_usage): Add help for -mloongson-ext and
	 -mno-loongson-ext.
	 * doc/as.texi: Document -mloongson-ext, -mno-loongson-ext.
	 * doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext,
	 .set loongson-ext and .set noloongson-ext.
	 * testsuite/gas/mips/loongson-mmi.d: Add ASE flag.

include/
	 * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
	 (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
	 * opcode/mips.h (ASE_LOONGSON_EXT): New macro.

opcodes/
	 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
	 descriptors.
	 (parse_mips_ase_option): Handle -M loongson-ext option.
	 (print_mips_disassembler_options): Document -M loongson-ext.
	 * mips-opc.c (IL3A): Delete.
	 * mips-opc.c (LEXT): New macro.
	 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
	 instructions.
 2018-08-29 19:57:39 +08:00
Chenghua Xu
716c08de28 [MIPS/GAS] Split Loongson CAM Instructions from loongson3a 
bfd/
	* elfxx-mips.c (print_mips_ases): Add CAM extension.

binutils/
	* readelf.c (print_mips_ases): Add CAM extension.

gas/
	* NEWS: Mention Loongson Content Address Memory (CAM)
	support.
	* config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and
	OPTION_NO_LOONGSON_CAM.
	(md_longopts): Likewise.
	(mips_ases): Define availability for CAM.
	(mips_convert_ase_flags): Map ASE_LOONGSON_CAM to
	AFL_ASE_LOONGSON_CAM.
	(mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a.
	(md_show_usage): Add help for -mloongson-cam and
	-mno-loongson-cam.
	* doc/as.texi: Document -mloongson-cam, -mno-loongson-cam.
	* doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam,
	.set loongson-cam and .set noloongson-cam.
	* testsuite/gas/mips/loongson-3a-2.d: Move cam test to ...
	* testsuite/gas/mips/loongson-cam.d: Here.  Add ISA/ASE
	flag verification.
	* testsuite/gas/mips/loongson-3a-2.s: Move cam test to ...
	* testsuite/gas/mips/loongson-cam.s: Here.
	* testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag.
	* testsuite/gas/mips/mips.exp: Run loongson-cam test.

include/
	* elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
	* opcode/mips.h (ASE_LOONGSON_CAM): New macro.

opcodes/
	* mips-dis.c (mips_arch_choices): Add CAM to loongson3a
	descriptors.
	(parse_mips_ase_option): Handle -M loongson-cam option.
	(print_mips_disassembler_options): Document -M loongson-cam.
	* mips-opc.c (LCAM): New macro.
	(mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
	instructions.
 2018-08-29 19:33:09 +08:00
H.J. Lu
a9eafb08b3 x86: Update GNU_PROPERTY_X86_XXX macros 
This patch updates GNU_PROPERTY_X86_XXX macros:

1. GNU_PROPERTY_X86_UINT32_AND_XXX: A 4-byte unsigned integer property.
A bit is set if it is set in all relocatable inputs:

 #define GNU_PROPERTY_X86_UINT32_AND_LO      0xc0000002
 #define GNU_PROPERTY_X86_UINT32_AND_HI      0xc0007fff

2. GNU_PROPERTY_X86_UINT32_OR_XXX: A 4-byte unsigned integer property.
A bit is set if it is set in any relocatable inputs:

 #define GNU_PROPERTY_X86_UINT32_OR_LO    0xc0008000
 #define GNU_PROPERTY_X86_UINT32_OR_HI    0xc000ffff

3. GNU_PROPERTY_X86_UINT32_OR_AND_XXX: A 4-byte unsigned integer property.
A bit is set if it is set in any relocatable inputs and the property is
present in all relocatable inputs:

 #define GNU_PROPERTY_X86_UINT32_OR_AND_LO   0xc0010000
 #define GNU_PROPERTY_X86_UINT32_OR_AND_HI   0xc0017fff

4. GNU_PROPERTY_X86_FEATURE_2_NEEDED, GNU_PROPERTY_X86_FEATURE_2_USED
and GNU_PROPERTY_X86_FEATURE_2_XXX bits.

GNU_PROPERTY_X86_FEATURE_1_AND is unchanged.  GNU_PROPERTY_X86_ISA_1_USED
and GNU_PROPERTY_X86_ISA_1_NEEDED are updated to better support targeted
processors since GNU_PROPERTY_X86_ISA_1_?86 aren't isn't very useful.
A new set of GNU_PROPERTY_X86_ISA_1_XXX bits are defined.  The previous
GNU_PROPERTY_X86_ISA_1_XXX macros are deprecated and renamed to
GNU_PROPERTY_X86_COMPAT_ISA_1_XXX.

bfd/

	* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Handle
	X86_COMPAT_ISA_1_USED, X86_COMPAT_ISA_1_NEEDED,
	X86_UINT32_AND_LO, X86_UINT32_AND_HI, X86_UINT32_OR_LO,
	X86_UINT32_OR_HI, X86_UINT32_OR_AND_LO and X86_UINT32_OR_AND_HI
	instead of X86_ISA_1_USED, X86_ISA_1_NEEDED and X86_FEATURE_1_AND.
	(_bfd_x86_elf_merge_gnu_properties): Likewise.
	(_bfd_x86_elf_link_setup_gnu_properties): Add X86_FEATURE_2_NEEDED
	instead of X86_ISA_1_NEEDED.
	(_bfd_x86_elf_link_fixup_gnu_properties): Handle
	X86_COMPAT_ISA_1_USED, X86_COMPAT_ISA_1_NEEDED, X86_UINT32_AND_LO,
	X86_UINT32_AND_HI, X86_UINT32_OR_LO, X86_UINT32_OR_HI,
	X86_UINT32_OR_AND_LO and X86_UINT32_OR_AND_HI instead of
	X86_ISA_1_USED, X86_ISA_1_NEEDED and X86_FEATURE_1_AND.

binutils/

	* readelf.c (decode_x86_compat_isa): New function.
	(decode_x86_feature_2): Likewise.
	(decode_x86_isa): Updated for new X86_ISA_1_XXX bits.
	(decode_x86_feature): Renamed to ...
	(decode_x86_feature_1): This.  Remove the type argument.
	(print_gnu_property_note): Handle X86_COMPAT_ISA_1_USED,
	X86_COMPAT_ISA_1_NEEDED, X86_UINT32_AND_LO, X86_UINT32_AND_HI,
	X86_UINT32_OR_LO, X86_UINT32_OR_HI, X86_UINT32_OR_AND_LO and
	X86_UINT32_OR_AND_HI instead of X86_ISA_1_USED, X86_ISA_1_NEEDED
	and X86_FEATURE_1_AND.
	* testsuite/binutils-all/i386/pr21231b.s: Updated to the current
	GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED
	values.
	* testsuite/binutils-all/x86-64/pr21231b.s: Likewise.
	* testsuite/binutils-all/x86-64/pr23494a.s: Likewise.
	* testsuite/binutils-all/x86-64/pr23494b.s: Likewise.
	* testsuite/binutils-all/x86-64/pr23494c.s: Likewise.
	* testsuite/binutils-all/i386/pr21231b.d: Updated.
	* testsuite/binutils-all/x86-64/pr21231b.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494a.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494c.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494d.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494e.d: Likewise.

include/

	* elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
	(GNU_PROPERTY_X86_COMPAT_ISA_1_USED): This.
	(GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ...
	(GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED): This.
	(GNU_PROPERTY_X86_ISA_1_XXX): Renamed to ...
	(GNU_PROPERTY_X86_COMPAT_ISA_1_XXX): This.
	(GNU_PROPERTY_X86_UINT32_AND_LO): New.
	(GNU_PROPERTY_X86_UINT32_AND_HI): Likewise.
	(GNU_PROPERTY_X86_UINT32_OR_LO): Likewise.
	(GNU_PROPERTY_X86_UINT32_OR_HI): Likewise.
	(GNU_PROPERTY_X86_UINT32_OR_AND_LO): Likewise.
	(GNU_PROPERTY_X86_UINT32_OR_AND_HI): Likewise.
	(GNU_PROPERTY_X86_ISA_1_CMOV): Likewise.
	(GNU_PROPERTY_X86_ISA_1_SSE): Likewise.
	(GNU_PROPERTY_X86_ISA_1_SSE2): Likewise.
	(GNU_PROPERTY_X86_ISA_1_SSE3): Likewise.
	(GNU_PROPERTY_X86_ISA_1_SSSE3): Likewise.
	(GNU_PROPERTY_X86_ISA_1_SSE4_1): Likewise.
	(GNU_PROPERTY_X86_ISA_1_SSE4_2): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX2): Likewise.
	(GNU_PROPERTY_X86_ISA_1_FMA): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512F): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512CD): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512ER): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512PF): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512VL): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512DQ): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512BW): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512_BITALG): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512_IFMA): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512_VBMI): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2): Likewise.
	(GNU_PROPERTY_X86_ISA_1_AVX512_VNNI): Likewise.
	(GNU_PROPERTY_X86_FEATURE_2_X86): Likewise.
	(GNU_PROPERTY_X86_FEATURE_2_X87): Likewise.
	(GNU_PROPERTY_X86_FEATURE_2_MMX): Likewise.
	(GNU_PROPERTY_X86_FEATURE_2_XMM): Likewise.
	(GNU_PROPERTY_X86_FEATURE_2_YMM): Likewise.
	(GNU_PROPERTY_X86_FEATURE_2_ZMM): Likewise.
	(GNU_PROPERTY_X86_FEATURE_2_FXSR): Likewise.
	(GNU_PROPERTY_X86_FEATURE_2_XSAVE): Likewise.
	(GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT): Likewise.
	(GNU_PROPERTY_X86_FEATURE_2_XSAVEC): Likewise.
	(GNU_PROPERTY_X86_FEATURE_1_AND): Updated to
	(GNU_PROPERTY_X86_UINT32_AND_LO + 0).
	(GNU_PROPERTY_X86_ISA_1_NEEDED): Defined to
	(GNU_PROPERTY_X86_UINT32_OR_LO + 0).
	(GNU_PROPERTY_X86_FEATURE_2_NEEDED): New.  Defined to
	(GNU_PROPERTY_X86_UINT32_OR_LO + 1).
	(GNU_PROPERTY_X86_ISA_1_USED): Defined to
	(GNU_PROPERTY_X86_UINT32_OR_AND_LO + 0).
	(GNU_PROPERTY_X86_FEATURE_2_USED): New.  Defined to
	(GNU_PROPERTY_X86_UINT32_OR_AND_LO + 1).

ld/

	* testsuite/ld-i386/i386.exp: Run pr23372c, pr23372d, pr23486c
	and pr23486d.
	* testsuite/ld-i386/pr23372a.s: Update comments.
	* testsuite/ld-i386/pr23372b.s: Likewise.
	* testsuite/ld-i386/pr23372c.s: Likewise.
	* testsuite/ld-x86-64/pr23372a.s: Likewise.
	* testsuite/ld-x86-64/pr23372b.s: Likewise.
	* testsuite/ld-x86-64/pr23372c.s: Likewise.
	* testsuite/ld-x86-64/pr23486a.s: Likewise.
	* testsuite/ld-x86-64/pr23486b.s: Likewise.
	* testsuite/ld-i386/pr23372c.d: New file.
	* testsuite/ld-i386/pr23372d.d: Likewise.
	* testsuite/ld-i386/pr23486c.d: Likewise.
	* testsuite/ld-i386/pr23486d.d: Likewise.
	* testsuite/ld-x86-64/pr23372c-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23372c.d: Likewise.
	* testsuite/ld-x86-64/pr23372d-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23372d.d: Likewise.
	* testsuite/ld-x86-64/pr23372d.s: Likewise.
	* testsuite/ld-x86-64/pr23372e.s: Likewise.
	* testsuite/ld-x86-64/pr23372f.s: Likewise.
	* testsuite/ld-x86-64/pr23486c-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23486c.d: Likewise.
	* testsuite/ld-x86-64/pr23486c.s: Likewise.
	* testsuite/ld-x86-64/pr23486d-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23486d.d: Likewise.
	* testsuite/ld-x86-64/pr23486d.s: Likewise.
	* testsuite/ld-i386/property-3.r: Updated.
	* testsuite/ld-i386/property-4.r: Likewise.
	* testsuite/ld-i386/property-5.r: Likewise.
	* testsuite/ld-i386/property-x86-3.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt3a.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk3a.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk3b.d: Likewise.
	* testsuite/ld-x86-64/property-3.r: Likewise.
	* testsuite/ld-x86-64/property-4.r: Likewise.
	* testsuite/ld-x86-64/property-5.r: Likewise.
	* testsuite/ld-x86-64/property-x86-3-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-3.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise.
	* testsuite/ld-i386/property-x86-1.S: Updated to the current
	GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED
	values.
	* testsuite/ld-i386/property-x86-2.S: Likewise.
	* testsuite/ld-i386/property-x86-3.s: Likewise.
	* testsuite/ld-x86-64/property-x86-1.S: Likewise.
	* testsuite/ld-x86-64/property-x86-2.S: Likewise.
	* testsuite/ld-x86-64/property-x86-3.s: Likewise.
	* ld/testsuite/ld-x86-64/x86-64.exp: Run pr23372c, pr23372c-x32,
	pr23372d, pr23372d-x32, pr23486c, pr23486c-x32, pr23486d and
	pr23486d-x32.
 2018-08-24 04:42:15 -07:00
H.J. Lu
aa7bca9b2e x86: Add GNU_PROPERTY_X86_UINT32_VALID 
The older linker treats .note.gnu.property section as a generic note
and just concatenates all .note.gnu.property sections from the input
to the output.  On CET-enabled OS, the output of the older linker is
marked as CET enabled, but in fact, it is not CET enabled and it crashes
on CET-enabled machines.

This patch defines GNU_PROPERTY_X86_UINT32_VALID.  Linker is updated to
set the GNU_PROPERTY_X86_UINT32_VALID bit in GNU property note for
non-relocatable output to differentiate outputs from the older linker.

bfd/

	* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Mask out the
	GNU_PROPERTY_X86_UINT32_VALID bit.
	(_bfd_x86_elf_link_fixup_gnu_properties): Set the
	GNU_PROPERTY_X86_UINT32_VALID bit for non-relocatable output.

binutils/

	* readelf.c (print_gnu_property_note): Check the
	GNU_PROPERTY_X86_UINT32_VALID bit for invalid GNU property note.

include/

	* elf/common.h (GNU_PROPERTY_X86_UINT32_VALID): New.
 2018-08-24 04:38:02 -07:00
Alan Modra
ebf983a444 Fix changelog entries 2018-08-22 16:38:55 +09:30
John Darrington
4e57b45639 S12Z: Rename reloc R_S12Z_UKNWN_3 to R_S12Z_EXT18 and implement according to recently inferred information about this reloc. 
* bfd/elf32-s12z.c: (opru18_reloc): New function.
* bfd/elf32-s12z.c: (elf_s12z_howto_table): Adjust Howto according to new knowledge.
* include/elf/s12z.h: Rename R_S12Z_UKNWN_3 to R_S12Z_EXT18.
 2018-08-21 19:24:21 +02:00
Alan Modra
9cf7e5687f Use operand->extract to provide defaults for optional PowerPC operands 
Most optional operands to powerpc instructions use a default value of
zero, but there are a few exceptions.  Those have been handled by
PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table
for the default value, smuggled in the shift field.  This patch
changes that to using the operand extract function to provide non-zero
defaults.

I've also moved the code determining whether optional operands are
provided or omitted, to the point the first optional operand is seen,
and allowed for the possibility of optional base register operands
in a future patch.

The patch does change the error you get on invalid assembly like

  ld 3,4

You'll now see "missing operand" rather than
"syntax error; end of line, expected `('".

gas/
	* config/tc-ppc.c (md_assemble): Delay counting of optional
	operands until one is encountered.  Allow for the possibility
	of optional base regs, ie. PPC_OPERAND_PARENS.  Call
	ppc_optional_operand_value with extra args.
include/
	* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
	Mention use of "extract" function to provide default value.
	(PPC_OPERAND_OPTIONAL_VALUE): Delete.
	(ppc_optional_operand_value): Rewrite to use extract function.
opcodes/
	* ppc-dis.c (operand_value_powerpc): Init "invalid".
	(skip_optional_operands): Count optional operands, and update
	ppc_optional_operand_value call.
	* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
	(extract_vlensi): Likewise.
	(extract_fxm): Return default value for missing optional operand.
	(extract_ls, extract_raq, extract_tbr): Likewise.
	(insert_sxl, extract_sxl): New functions.
	(insert_esync, extract_esync): Remove Power9 handling and simplify.
	(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
	flag and extra entry.
	(powerpc_operands <SXL>): Likewise, and use insert_sxl and
	extract_sxl.
 2018-08-21 16:05:36 +09:30
Alan Modra
08a8fe2ffd Fix s12z test regexps 
Fixes
ERROR: tcl error sourcing .../gas/testsuite/gas/s12z/s12z.exp.
ERROR: couldn't compile regular expression pattern: quantifier operand invalid

run_dump_test expected output lines are regexps.

	* testsuite/gas/s12z/bit-manip-invalid.d: Correct regexps.
 2018-08-21 14:59:53 +09:30
Alan Modra
d203b41ac7 Tidy bit twiddling 
* sh-opc.h (MASK): Simplify.
 2018-08-20 09:54:20 +09:30
John Darrington
7ba3ba91a3 S12Z: Move opcode header to public include directory. 
opcodes/
        * s12z.h: Delete.
	* s12z-dis.c: Adjust path of included file.

include/
        * opcode/s12z.h: New file.

gas/
	* config/tc-s12z.c: Adjust path of included file.
 2018-08-18 07:50:03 +02:00
Richard Earnshaw
57285adece arm - Add some comments about the versions of ARM ELF that define various e_flags values 
This patch adds a few comments to include/elf/arm.h to clarify which
versions of the ARM ELF specification defined which headers.  Given
that the EABI is pretty ubiquitous these days, I've marked anything
not based on that as deprecated.

There are no plans to remove any deprecated definitions at this time,
but any new development shouldn't be building upon support for
deprecated definitions remaining in the long term.

	* elf/arm.h: Updated comments for e_flags definitions.
 2018-08-09 16:51:09 +01:00
claziss
db1e1b45b4 [ARC] Add Tag_ARC_ATR_version. 
Add a new tag (Tag_ARC_ATR_version) used to indicate if current
attributes are interpreted in GNU way. This attribute is used by
Synopsys custom compiler to correctly identify and interpret the
object attributes section as generated by GNU tools.

gas/
2017-08-02  Claudiu Zissulescu <claziss@synopsys.com>

	* config/tc-arc.c (arc_set_public_attributes): Add
	Tag_ARC_ATR_version.
	(arc_convert_symbolic_attribute): Likewise.
	* testsuite/gas/arc/attr-arc600.d: Update test.
	* testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise.
	* testsuite/gas/arc/attr-arc600_norm.d: Likewise.
	* testsuite/gas/arc/attr-arc601.d: Likewise.
	* testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise.
	* testsuite/gas/arc/attr-arc601_mul64.d: Likewise.
	* testsuite/gas/arc/attr-arc601_norm.d: Likewise.
	* testsuite/gas/arc/attr-arc700.d: Likewise.
	* testsuite/gas/arc/attr-arcem.d: Likewise.
	* testsuite/gas/arc/attr-archs.d: Likewise.
	* testsuite/gas/arc/attr-autodetect-1.d: Likewise.
	* testsuite/gas/arc/attr-cpu-a601.d: Likewise.
	* testsuite/gas/arc/attr-cpu-a700.d: Likewise.
	* testsuite/gas/arc/attr-cpu-em.d: Likewise.
	* testsuite/gas/arc/attr-cpu-hs.d: Likewise.
	* testsuite/gas/arc/attr-em.d: Likewise.
	* testsuite/gas/arc/attr-em4.d: Likewise.
	* testsuite/gas/arc/attr-em4_dmips.d: Likewise.
	* testsuite/gas/arc/attr-em4_fpuda.d: Likewise.
	* testsuite/gas/arc/attr-em4_fpus.d: Likewise.
	* testsuite/gas/arc/attr-hs.d: Likewise.
	* testsuite/gas/arc/attr-hs34.d: Likewise.
	* testsuite/gas/arc/attr-hs38.d: Likewise.
	* testsuite/gas/arc/attr-hs38_linux.d: Likewise.
	* testsuite/gas/arc/attr-mul64.d: Likewise.
	* testsuite/gas/arc/attr-name.d: Likewise.
	* testsuite/gas/arc/attr-nps400.d: Likewise.
	* testsuite/gas/arc/attr-override-mcpu.d: Likewise.
	* testsuite/gas/arc/attr-quarkse_em.d: Likewise.

bfd/
2017-08-02  Claudiu Zissulescu <claziss@synopsys.com>

	* elf32-arc.c (arc_elf_merge_attributes): Handle
	Tag_ARC_ATR_version.

binutils/
2017-08-02  Claudiu Zissulescu <claziss@synopsys.com>

	* readelf.c (display_arc_attribute): Print Tag_ARC_ATR_version.

include/
2017-08-02  Claudiu Zissulescu <claziss@synopsys.com>

	* elf/arc.h (Tag_ARC_ATR_version): New tag.

ld/
2017-08-02  Claudiu Zissulescu <claziss@synopsys.com>

	* testsuite/ld-arc/attr-merge-0.d: Update test.
	* testsuite/ld-arc/attr-merge-1.d: Likewise.
	* testsuite/ld-arc/attr-merge-2.d: Likewise.
	* testsuite/ld-arc/attr-merge-3.d: Likewise.
	* testsuite/ld-arc/attr-merge-5.d: Likewise.
 2018-08-06 16:41:32 +03:00
claziss
b6523c37fb [ARC] Update handling AUX-registers. 
Update aux-registers data-base, and accept aux-registers names with
upper/lowercase names.

opcode/
2017-07-18  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-regs.h: Update aux-registers.

gas/
2017-07-18  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (find_opcode_match): Accept uppercase aux-regs
	names.
	* testsuite/gas/arc/ld2.d: Update test.
	* testsuite/gas/arc/taux.d: Likewise.
	* testsuite/gas/arc/taux.s: Likewise.

include/
2017-07-18  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (ARC_OPCODE_ARCV1): Define.
 2018-08-06 16:41:32 +03:00
marxin
50320b1d4a Copy from GCC: Add linker_output as prefix for LTO temps (PR lto/86548). 
2018-07-26  Martin Liska  <mliska@suse.cz>

        PR lto/86548
	* libiberty.h (make_temp_file_with_prefix): New function.
2018-07-26  Martin Liska  <mliska@suse.cz>

        PR lto/86548
	* make-temp-file.c (TEMP_FILE): Remove leading 'cc'.
	(make_temp_file): Call make_temp_file_with_prefix with
        first argument set to NULL.
	(make_temp_file_with_prefix): Support also prefix.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@262999 138bc75d-0d04-0410-961f-82ee72b054a4
 2018-08-01 14:23:10 +01:00
Jim Wilson
eb41b24898 RISC-V: Set insn info fields correctly when disassembling. 
include/
	* opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR)
	(INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE)
	(INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New.

	opcodes/
	* riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
	fields.
	* riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 2018-07-30 13:55:41 -07:00
Andrew Jenner
b8891f8d62 Add support for the C_SKY series of processors. 
This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants.  V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc.  There is support for bare-metal ELF targets and Linux with both glibc and uClibc.

This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics.  C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers.  (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about.

bfd     * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY.
        (BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise.
        * Makefile.in: Regenerated.
        * archures.c (enum bfd_architecture): Add bfd_arch_csky and
        related bfd_mach defines.
        (bfd_csky_arch): Declare.
        (bfd_archures_list): Add C-SKY.
        * bfd-in.h (elf32_csky_build_stubs): Declare.
        (elf32_csky_size_stubs): Declare.
        (elf32_csky_next_input_section: Declare.
        (elf32_csky_setup_section_lists): Declare.
        * bfd-in2.h: Regenerated.
        * config.bfd: Add C-SKY.
        * configure.ac: Likewise.
        * configure: Regenerated.
        * cpu-csky.c: New file.
        * elf-bfd.h (enum elf_target_id): Add C-SKY.
        * elf32-csky.c: New file.
        * libbfd.h: Regenerated.
        * reloc.c: Add C-SKY relocations.
        * targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare.
        (_bfd_target_vector): Add C-SKY target vector entries.

binutils* readelf.c: Include elf/csky.h.
        (guess_is_rela): Handle EM_CSKY.
        (dump_relocations): Likewise.
        (get_machine_name): Likewise.
        (is_32bit_abs_reloc): Likewise.

include  * dis-asm.h (csky_symbol_is_valid): Declare.
         * opcode/csky.h: New file.

opcodes  * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
         * Makefile.in: Regenerated.
         * configure.ac: Add C-SKY.
         * configure: Regenerated.
         * csky-dis.c: New file.
         * csky-opc.h: New file.
         * disassemble.c (ARCH_csky): Define.
         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.

gas      * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY.
         (TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise.
         * Makefile.in: Regenerated.
         * config/tc-csky.c: New file.
         * config/tc-csky.h: New file.
         * config/te-csky_abiv1.h: New file.
         * config/te-csky_abiv1_linux.h: New file.
         * config/te-csky_abiv2.h: New file.
         * config/te-csky_abiv2_linux.h: New file.
         * configure.tgt: Add C-SKY.
         * doc/Makefile.am (CPU_DOCS): Add entry for C-SKY.
         * doc/Makefile.in: Regenerated.
         * doc/all.texi: Set CSKY feature.
         * doc/as.texi (Overview): Add C-SKY options.
         (Machine Dependencies): Likewise.
         * doc/c-csky.texi: New file.
         * testsuite/gas/csky/*: New test cases.

ld      * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations.
        (ecskyelf.c, ecskyelf_linux.c): New rules.
        * Makefile.in: Regenerated.
        * configure.tgt: Add C-SKY.
        * emulparams/cskyelf.sh: New file.
        * emulparams/cskyelf_linux.sh: New file.
        * emultempl/cskyelf.em: New file.
        * gen-doc.texi: Add C-SKY.
        * ld.texi: Likewise.
        (Options specific to C-SKY targets): New section.
        * testsuite/ld-csky/*: New tests.
 2018-07-30 12:24:14 +01:00
Chenghua Xu
2bb9bbe2e8 MIPS/GAS: Correct the AFL_ASE_MASK macro 
Fix an issue with commit 8095d2f70e ("MIPS/GAS: Split Loongson MMI
Instructions from loongson2f/3a"), AFL_ASE_MASK should be 0x0006ffff
instead of 0x0004ffff.

2018-07-27  Chenghua Xu  <paul.hua.gm@gmail.com>
            Maciej W. Rozycki  <macro@linux-mips.org>

include/
	* elf/mips.h (AFL_ASE_MASK): Correct typo.
 2018-07-27 01:12:43 +01:00
Alex Chadwick
fa758a7046 PowerPC Improve support for Gekko & Broadway 
This is a relatively straightforward patch to improve support for the
IBM Gekko and IBM Broadway processors.  Broadway is functionally
equivalent to the IBM 750CL, while Gekko's functionality is a subset
of theirs.  The patch simplifies this reality and adds -mgekko and
-mbroadway as aliases for -m750cl.  I didn't feel it was worth wasting
a PPC_OPCODE_* bit to differentiate Gekko.  The patch adds a number of
simplified mnemonics for special purpose register access.  Notably,
Broadway adds 4 additional IBAT and DBAT registers but these are not
assigned sequential SPR numbers.

gas/
	* config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway.
	* doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway.
	* doc/c-ppc.texi (PowerPC-Opts): Likewise.
	* testsuite/gas/ppc/broadway.d,
	* testsuite/gas/ppc/broadway.s: New test for broadway.
	* testsuite/gas/ppc/ppc.exp: Run new test.
include/
	* opcode/ppc.h (PPC_OPCODE_750): Adjust comment.
opcodes/
	* ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
	(powerpc_init_dialect): Handle bfd_mach_ppc_750.
	* ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
	support disjointed BAT.
	(powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
	(XSPRGQR_MASK, GEKKO, BROADWAY): Define.
	(powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 2018-07-26 17:42:47 +09:30
Alan Modra
33cb30a1f9 Implement PowerPC64 .localentry for value 1 
This adds support for ".localentry 1", a new st_other
STO_PPC64_LOCAL_MASK encoding that signifies a function with a single
entry point like ".localentry 0", but unlike a ".localentry 0"
function does not preserve r2.

include/
	* elf/ppc64.h: Specify byte offset to local entry for values
	of two to six in STO_PPC64_LOCAL_MASK.  Clarify r2 return
	value for such functions when entering via global entry point.
	Specify meaning of a value of one in STO_PPC64_LOCAL_MASK.
bfd/
	* elf64-ppc.c (ppc64_elf_size_stubs): Use a ppc_stub_long_branch_r2off
	for calls to symbols with STO_PPC64_LOCAL_MASK bits set to 1.
gas/
	* config/tc-ppc.c (ppc_elf_localentry): Allow .localentry values
	of 1 and 7 to directly set value into STO_PPC64_LOCAL_MASK bits.
ld/testsuite/
	* ld-powerpc/elfv2.s: Add .localentry f5,1 testcase.
	* ld-powerpc/elfv2exe.d: Update.
	* ld-powerpc/elfv2so.d: Update.
 2018-07-26 12:53:50 +09:30
Alan Modra
67ce483baa PR23430, Indices misspelled 
PR 23430
include/
	* elf/common.h (SHT_SYMTAB_SHNDX): Fix comment typo.
bfd/
	* dwarf2.c (dwarf_debug_section_enum): Fix comment typo.
	* elf.c (bfd_section_from_shdr, elf_sort_sections): Likewise.
binutils/
	* elfcomm.h (struct archive_info): Rename uses_64bit_indicies
	to uses_64bit_indices.
	* elfcomm.c (setup_archive): Update uses of above.
	* readelf.c (process_archive): Likewise.
	(get_section_type_name): Rename indicies to indices.
	(get_32bit_elf_symbols, get_64bit_elf_symbols): Likewise.
	(process_section_groups): Likewise.
cpu/
	* or1kcommon.cpu (spr-reg-indices): Fix description typo.
opcodes/
	* or1k-desc.h: Regenerate.
 2018-07-24 19:58:12 +09:30
Chenghua Xu
8095d2f70e MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a 
The MMI instruction set has been implemented in many Loongson
processors.  There is a lot of software optimized for MMI.  This patch
splits MMI from loongson2f/3a, and adds GAS and disassembler options for
MMI instructions.

2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
            Maciej W. Rozycki  <macro@mips.com>

bfd/
	* elfxx-mips.c (print_mips_ases): Add MMI extension.

binutils/
	* readelf.c (print_mips_ases): Add MMI extension.

gas/
	* NEWS: Mention MultiMedia extensions Instructions (MMI)
	support.
	* config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and
	OPTION_NO_LOONGSON_MMI.
	(md_longopts): Likewise.
	(mips_ases): Define availability for MMI.
	(mips_convert_ase_flags): Map ASE_LOONGSON_MMI to
	AFL_ASE_LOONGSON_MMI.
	(mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a.
	(md_show_usage): Add help for -mloongson-mmi and
	-mno-loongson-mmi.
	* doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi.
	* doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi,
	.set loongson-mmi and .set noloongson-mmi.
	* testsuite/gas/mips/loongson-2f.d: Move mmi test to ...
	* testsuite/gas/mips/loongson-2f-mmi.d: Here.  Add ISA/ASE
	flag verification.
	* testsuite/gas/mips/loongson-2f.s: Move mmi test to ...
	* testsuite/gas/mips/loongson-2f-mmi.s: Here.
	* testsuite/gas/mips/loongson-3a.d: Move mmi test to ...
	* testsuite/gas/mips/loongson-3a-mmi.d: Here.  Add ISA/ASE
	flag verification.
	* testsuite/gas/mips/loongson-3a.s: Move mmi test to ...
	* testsuite/gas/mips/loongson-3a-mmi.s: Here.
	* testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and
	loongson-3a-mmi tests.

include/
	* elf/mips.h (AFL_ASE_MMI): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI.
	* opcode/mips.h (ASE_LOONGSON_MMI): New macro.

opcodes/
	* mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
	loongson3a descriptors.
	(parse_mips_ase_option): Handle -M loongson-mmi option.
	(print_mips_disassembler_options): Document -M loongson-mmi.
	* mips-opc.c (LMMI): New macro.
	(mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
	instructions.
 2018-07-20 13:21:33 +01:00
Maciej W. Rozycki
d5c928c053 LD: Export relative-from-absolute symbol marking to BFD 
It is usually possible to tell absolute and ordinary symbols apart in
BFD throughout the link, by checking whether the section that owns the
symbol is absolute or not.

That however does not work for ordinary symbols defined in a linker
script outside an output section statement.  Initially such symbols are
entered into to the link hash as absolute symbols, owned by the absolute
section.  A flag is set in the internal linker expression defining such
symbols to tell the linker to convert them to section-relative ones in
the final phase of the link.  That flag is however not accessible to BFD
linker code, including BFD target code in particular.

Add a flag to the link hash then to copy the information held in the
linker expression.  Define a macro, `bfd_is_abs_symbol', for BFD code to
use where determining whether a symbol is absolute or ordinary is
required before the final link phase.

This macro will correctly identify the special `__ehdr_start' symbol as
ordinary throughout link, for example, even though early on it will be
assigned to the absolute section.  Of course this does not let BFD code
identify what the symbol's ultimate section will be before the final
link phase has converted this symbol (in `update_definedness').

	include/
	* bfdlink.h (bfd_link_hash_entry): Add `rel_from_abs' member.

	bfd/
	* linker.c (bfd_is_abs_symbol): New macro.
	* bfd-in2.h: Regenerate.

	ld/
	* ldexp.c (exp_fold_tree_1) <etree_assign, etree_provide>
	<etree_provided>: Copy expression's `rel_from_abs' flag to the
	link hash.
 2018-07-17 20:04:53 +01:00
Alan Modra
fe75810f8e Fix diagnostic errors 
Fixes a number of build errors like the following
.../elf32-arm.c: In function 'elf32_arm_nabi_write_core_note':
.../elf32-arm.c:2177: error: #pragma GCC diagnostic not allowed inside functions
.../elf32-arm.c:2186: error: #pragma GCC diagnostic not allowed inside functions
See the comment in diagnostics.h.

include/
	* diagnostics.h: Comment on macro usage.
bfd/
	* elf32-arm.c (elf32_arm_nabi_write_core_note): Don't use
	DIAGNOTIC_PUSH and DIAGNOSTIC_POP unconditionally.
	* elf32-ppc.c (ppc_elf_write_core_note): Likewise.
	* elf32-s390.c (elf_s390_write_core_note): Likewise.
	* elf64-ppc.c (ppc64_elf_write_core_note): Likewise.
	* elf64-s390.c (elf_s390_write_core_note): Likewise.
	* elfxx-aarch64.c (_bfd_aarch64_elf_write_core_note): Likewise.
 2018-07-06 15:18:59 +09:30
Simon Marchi
6821842f15 darwin: Silence syscall deprecated declaration warning 
This patch silences this warning:

/Users/simark/src/binutils-gdb/gdb/darwin-nat.c:839:10: error: 'syscall' is deprecated: first deprecated in macOS 10.12 - syscall(2) is unsupported; please switch to a supported interface. For SYS_kdebug_trace use kdebug_signpost(). [-Werror,-Wdeprecated-declarations]
          res = syscall (SYS___pthread_kill, thread->gdb_port, nsignal);
                ^
/usr/include/unistd.h:745:6: note: 'syscall' has been explicitly marked deprecated here
int      syscall(int, ...);
         ^

The comment of the new pthread_kill function explains why we use the
syscall function directly.

include/ChangeLog:

	* diagnostics.h (DIAGNOSTIC_IGNORE_DEPRECATED_DECLARATIONS):
	Define for clang.

gdb/ChangeLog:

	* darwin-nat.c (darwin_pthread_kill): New function.
	(darwin_resume_thread): Use darwin_pthread_kill.
 2018-07-05 21:50:18 -04:00
Maciej W. Rozycki
471b9d1507 GDB PR tdep/8282: MIPS: Wire in `set disassembler-options' 
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a8140 ("GDB: Add support for the new
set/show disassembler-options commands.").

This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options.  So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name.  Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.

Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected.  Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.

The resulting output for the MIPS target is as follows:

(gdb) show disassembler-options
The current disassembler options are ''

The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:

  no-aliases      Use canonical instruction forms.

  msa             Recognize MSA instructions.

  virt            Recognize the virtualization ASE instructions.

  xpa             Recognize the eXtended Physical Address (XPA) ASE
                  instructions.

  ginv            Recognize the Global INValidate (GINV) ASE instructions.

  gpr-names=ABI   Print GPR names according to specified ABI.
                  Default: based on binary being disassembled.

  fpr-names=ABI   Print FPR names according to specified ABI.
                  Default: numeric.

  cp0-names=ARCH  Print CP0 register names according to specified architecture.
                  Default: based on binary being disassembled.

  hwr-names=ARCH  Print HWR names according to specified architecture.
                  Default: based on binary being disassembled.

  reg-names=ABI   Print GPR and FPR names according to specified ABI.

  reg-names=ARCH  Print CP0 register and HWR names according to specified
                  architecture.

  For the options above, the following values are supported for "ABI":
    numeric 32 n32 64

  For the options above, the following values are supported for "ARCH":
    numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
    r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
    r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
    mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
    loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)

which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions.  The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.

This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:

(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''

The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:

  esa         Disassemble in ESA architecture mode
  zarch       Disassemble in z/Architecture mode
  insnlength  Print unknown instructions according to length from first two bits
(gdb)

but:

(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''

The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
  403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
  821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
  e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
  power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
  ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
  spe2, titan, vle, vsx
(gdb)

Existing affected target backends have been adjusted accordingly.

This has been verified manually with:

(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit

to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands.  A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.

2018-07-02  Maciej W. Rozycki  <macro@mips.com>
            Simon Marchi  <simon.marchi@polymtl.ca>

	include/
	PR tdep/8282
	* dis-asm.h (disasm_option_arg_t): New typedef.
	(disasm_options_and_args_t): Likewise.
	(disasm_options_t): Add `arg' member, document members.
	(disassembler_options_mips): New prototype.
	(disassembler_options_arm, disassembler_options_powerpc)
	(disassembler_options_s390): Update prototypes.

	opcodes/
	PR tdep/8282
	* mips-dis.c (mips_option_arg_t): New enumeration.
	(mips_options): New variable.
	(disassembler_options_mips): New function.
	(print_mips_disassembler_options): Reimplement in terms of
	`disassembler_options_mips'.
	* arm-dis.c (disassembler_options_arm): Adapt to using the
	`disasm_options_and_args_t' structure.
	* ppc-dis.c (disassembler_options_powerpc): Likewise.
	* s390-dis.c (disassembler_options_s390): Likewise.

	gdb/
	PR tdep/8282
	* disasm.h (gdb_disassembler): Add
	`m_disassembler_options_holder'. member
	* disasm.c (get_all_disassembler_options): New function.
	(gdb_disassembler::gdb_disassembler): Use it.
	(gdb_buffered_insn_length_init_dis): Likewise.
	(gdb_buffered_insn_length): Adjust accordingly.
	(set_disassembler_options): Handle options with arguments.
	(show_disassembler_options_sfunc): Likewise.  Add a leading new
	line if showing options with descriptions.
	(disassembler_options_completer): Adapt to using the
	`disasm_options_and_args_t' structure.
	* mips-tdep.c (mips_disassembler_options): New variable.
	(mips_disassembler_options_o32): Likewise.
	(mips_disassembler_options_n32): Likewise.
	(mips_disassembler_options_n64): Likewise.
	(gdb_print_insn_mips): Don't set `disassembler_options'.
	(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
	functions.
	(mips_gdbarch_init): Always set `gdbarch_print_insn' to
	`gdb_print_insn_mips'.  Set `gdbarch_disassembler_options',
	`gdbarch_disassembler_options_implicit' and
	`gdbarch_valid_disassembler_options'.
	* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
	`disasm_options_and_args_t' structure.
	* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
	method.
	(valid_disassembler_options): Switch from `disasm_options_t' to
	the `disasm_options_and_args_t' structure.
	* NEWS: Document `set disassembler-options' support for the MIPS
	target.
	* gdbarch.h: Regenerate.
	* gdbarch.c: Regenerate.

	gdb/doc/
	PR tdep/8282
	* gdb.texinfo (Source and Machine Code): Document `set
	disassembler-options' support for the MIPS target.

	gdb/testsuite/
	PR tdep/8282
	* gdb.arch/mips-disassembler-options.exp: New test.
	* gdb.arch/mips-disassembler-options.s: New test source.
 2018-07-02 23:57:21 +01:00
Tamar Christina
369c9167d4 Fix AArch64 encodings for by element instructions. 
Some instructions in Armv8-a place a limitation on FP16 registers that can be
used as the register from which to select an element from.

e.g. fmla restricts Rm to 4 bits when using an FP16 register.  This restriction
does not apply for all instructions, e.g. fcmla does not have this restriction
as it gets an extra bit from the M field.

Unfortunately, this restriction to S_H was added for all _Em operands before,
meaning for a large number of instructions you couldn't use the full register
file.

This fixes the issue by introducing a new operand _Em16 which applies this
restriction only when paired with S_H and leaves the _Em and the other
qualifiers for _Em16 unbounded (i.e. using the full 5 bit range).

Also the patch updates all instructions that should be affected by this.

opcodes/

	PR binutils/23192
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
	* aarch64-opc.c (operand_general_constraint_met_p,
	aarch64_print_operand): Likewise.
	* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
	smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
	fmlal2, fmlsl2.
	(AARCH64_OPERANDS): Add Em2.

gas/

	PR binutils/23192
	* config/tc-aarch64.c (process_omitted_operand, parse_operands): Add
	AARCH64_OPND_Em16
	* testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper
	16 registers.
	* testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
	* testsuite/gas/aarch64/advsimd-compnum.s: Likewise.
	* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
	* testsuite/gas/aarch64/sve.d: Likewise.

include/

	PR binutils/23192
	*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
 2018-06-29 12:14:42 +01:00
Alan Modra
2393a7e3e6 Revert "Use offsets instead of addresses in ELF_SECTION_IN_SEGMENT for non SHT_NOBITS" 
This reverts commit 57c0d77c2c.
 2018-06-26 21:28:05 +09:30
Nick Clifton
719d828850 Add 2.30 branch notes to ChangeLogs and NEWS files. 2018-06-24 18:36:15 +01:00
Alan Hayward
57c0d77c2c Use offsets instead of addresses in ELF_SECTION_IN_SEGMENT for non SHT_NOBITS 
For sections that are not SHT_NOBITS, use sh_offset and p_offset instead of
sh_addr and p_vaddr when calculating if a section fits in a segment. Both
methods are valid when using the GNU linker.

include/
	* elf/internal.h (ELF_SECTION_IN_SEGMENT): Don’t check addresses
	for non SHT_NOBITS.
 2018-06-21 09:37:58 +01:00
Simon Marchi
d856f9a8d6 include: Sync with GCC 
Bring changes from GCC in shared headers.

include/ChangeLog:

	Sync with GCC

	2018-05-24  Tom Rix  <trix@juniper.net>

	* dwarf2.def (DW_FORM_strx*, DW_FORM_addrx*): New.

	2017-11-20  Kito Cheng  <kito.cheng@gmail.com>

	* longlong.h [__riscv] (__umulsidi3): Define.
	[__riscv] (umul_ppmm): Likewise.
	[__riscv] (__muluw3): Likewise.
 2018-06-19 14:15:17 -04:00
Faraz Shahbazker
6f20c942c3 MIPS: Add Global INValidate ASE support 
Add support for the Global INValidate Application Specific Extension
for Release 6 of the MIPS Architecture.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
    Instruction Set Manual", Imagination Technologies Ltd., Document
    Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
    "Alphabetical List of Instructions", pp. 187-191

bfd/
	* elfxx-mips.c (print_mips_ases): Add GINV extension.

binutils/
	* readelf.c (print_mips_ases): Add GINV extension.

gas/
	* NEWS: Mention MIPS Global INValidate ASE support.
	* config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV.
	(md_longopts): Likewise.
	(mips_ases): Define availability for GINV.
	(mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV.
	(md_show_usage): Add help for -mginv and -mno-ginv.
	* doc/as.texinfo: Document -mginv, -mno-ginv.
	* doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and
	.set noginv.
	* testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV
	ASE.
	* testsuite/gas/mips/ase-errors-2.s: Likewise.
	* testsuite/gas/mips/ase-errors-1.l: Likewise.
	* testsuite/gas/mips/ase-errors-2.l: Likewise.
	* testsuite/gas/mips/ginv.d: New test.
	* testsuite/gas/mips/ginv-err.d: New test.
	* testsuite/gas/mips/ginv-err.l: New test stderr output.
	* testsuite/gas/mips/ginv.s: New test source.
	* testsuite/gas/mips/ginv-err.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

include/
	* elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
	(AFL_ASE_MASK): Update to include AFL_ASE_GINV.
	* opcode/mips.h: Document "+\" operand format.
	(ASE_GINV): New macro.

opcodes/
	* mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
	mips64r6 descriptors.
	(parse_mips_ase_option): Handle -Mginv option.
	(print_mips_disassembler_options): Document -Mginv.
	* mips-opc.c (decode_mips_operand) <+\>: New operand format.
	(GINV): New macro.
	(mips_opcodes): Define ginvi and ginvt.
 2018-06-14 21:34:49 +01:00
Scott Egerton
730c31740a MIPS: Add CRC ASE support 
Add support for the CRC Application Specific Extension for Release 6 of
the MIPS Architecture.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
    Instruction Set Manual", Imagination Technologies Ltd., Document
    Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
    "Alphabetical List of Instructions", pp. 143-148

[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
    Instruction Set Manual", Imagination Technologies Ltd., Document
    Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
    "Alphabetical List of Instructions", pp. 165-170

ChangeLog:

bfd/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* elfxx-mips.c (print_mips_ases): Add CRC.

binutils/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* readelf.c (print_mips_ases): Add CRC.

gas/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
            Maciej W. Rozycki  <macro@mips.com>

	* config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC.
	(md_longopts): Likewise.
	(md_show_usage): Add help for -mcrc and -mno-crc.
	(mips_ases): Define availability for CRC and CRC64.
	(mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC.
	* doc/as.texinfo: Document -mcrc, -mno-crc.
	* doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and
	.set no-crc.
	* testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC
	ASE.
	* testsuite/gas/mips/ase-errors-2.l: Likewise.
	* testsuite/gas/mips/ase-errors-1.s: Likewise.
	* testsuite/gas/mips/ase-errors-2.s: Likewise.
	* testsuite/gas/mips/crc.d: New test.
	* testsuite/gas/mips/crc64.d: New test.
	* testsuite/gas/mips/crc-err.d: New test.
	* testsuite/gas/mips/crc64-err.d: New test.
	* testsuite/gas/mips/crc-err.l: New test stderr output.
	* testsuite/gas/mips/crc64-err.l: New test stderr output.
	* testsuite/gas/mips/crc.s: New test source.
	* testsuite/gas/mips/crc64.s: New test source.
	* testsuite/gas/mips/crc-err.s: New test source.
	* testsuite/gas/mips/crc64-err.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

include/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* elf/mips.h (AFL_ASE_CRC): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
	* opcode/mips.h (ASE_CRC): New macro.
	* opcode/mips.h (ASE_CRC64): Likewise.

opcodes/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
	* mips-opc.c (CRC, CRC64): New macros.
	(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
	crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
	crc32cd for CRC64.
 2018-06-13 15:39:05 +01:00
Max Filippov
4b8e28c793 xtensa: use property tables for correct disassembly 
xtensa disassembler does not use information from the .xt.prop sections
to switch between code/data disassembly in text sections. This may
result in incorrect disassembly when data is interpreted as code and
disassembler loses synchronization with instruction stream. Use .xt.prop
section information to correctly interpret code and data and synchronize
with instruction stream.

2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
bfd/
	* elf32-xtensa.c (xtensa_read_table_entries): Make global.
	(compute_fill_extra_space): Drop declaration. Rename function to
	xtensa_compute_fill_extra_space.
	(compute_ebb_actions, remove_dead_literal): Update references to
	compute_fill_extra_space.

include/
	* elf/xtensa.h (xtensa_read_table_entries)
	(xtensa_compute_fill_extra_space): New declarations.

opcodes/
	* xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
	(dis_private): Add new fields for property section tracking.
	(xtensa_coalesce_insn_tables, xtensa_find_table_entry)
	(xtensa_instruction_fits): New functions.
	(fetch_data): Bump minimal fetch size to 4.
	(print_insn_xtensa): Make struct dis_private static.
	Load and prepare property table on section change.
	Don't disassemble literals. Don't disassemble instructions that
	cross property table boundaries.
 2018-06-04 10:38:55 -07:00
H.J. Lu
95da985446 Use DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION to silence GCC 8.1 
GCC 8.1 warns about destination size with -Wstringop-truncation:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643

Use DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION to silence it.

bfd/

	PR binutils/23146
	* bfd-in.h: Include "diagnostics.h".
	* bfd-in2.h: Regenerated.
	* elf32-arm.c (elf32_arm_nabi_write_core_note): Use
	DIAGNOSTIC_PUSH, DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION and
	DIAGNOSTIC_POP to silence GCC 8.1 warnings with
	-Wstringop-truncation.
	* elf32-ppc.c (ppc_elf_write_core_note): Likewse.
	* elf32-s390.c (elf_s390_write_core_note): Likewse.
	* elf64-ppc.c (ppc64_elf_write_core_note): Likewse.
	* elf64-s390.c (elf_s390_write_core_note): Likewse.
	* elfxx-aarch64.c (_bfd_aarch64_elf_write_core_note): Likewse.

include/

	* diagnostics.h (DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): Always
	define for GCC.
 2018-06-04 10:01:46 -07:00
H.J. Lu
23081219bf Add DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION 
Add DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION for GCC 8.1 to silence
-Wstringop-truncation warning:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643

	* diagnostics.h (DIAGNOSTIC_STRINGIFY_1): New.
	(DIAGNOSTIC_STRINGIFY): Likewise.
	(DIAGNOSTIC_IGNORE): Replace STRINGIFY with DIAGNOSTIC_STRINGIFY.
	(DIAGNOSTIC_IGNORE_SELF_MOVE): Define empty if not defined.
	(DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER): Likewise.
	(DIAGNOSTIC_IGNORE_UNUSED_FUNCTION): Likewise.
	(DIAGNOSTIC_IGNORE_SWITCH_DIFFERENT_ENUM_TYPES): Likewise.
	(DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): New.
 2018-06-04 06:35:07 -07:00
H.J. Lu
e9cb46ab59 Move gdb/common/diagnostics.h to include/diagnostics.h 
Move gdb/common/diagnostics.h to include/diagnostics.h so that it can
be used in binutils.

gdb/

	* ada-lex.l: Include "diagnostics.h" instead of
	"common/diagnostics.h".
	* unittests/environ-selftests.c: Likewise.
	* common/diagnostics.h: Moved to ../include.

include/

	* diagnostics.h: Moved from ../gdb/common/diagnostics.h.
 2018-06-01 09:40:30 -07:00
edlinger
22467434fd include: 2018-05-28 Bernd Edlinger <bernd.edlinger@hotmail.de> 
include:
        * splay-tree.h (splay_tree_compare_strings,
        splay_tree_delete_pointers): Declare new utility functions.

libiberty:
2018-05-28  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        * splay-tree.c (splay_tree_compare_strings,
        splay_tree_delete_pointers): New utility functions.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260850 138bc75d-0d04-0410-961f-82ee72b054a4
 2018-05-31 10:17:13 +01:00
Peter Bergner
98553ad33e Remove fake operand handling for extended mnemonics. 
opcodes/
	* ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
	insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
	(insert_bab, extract_bab, insert_btab, extract_btab,
	insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
	(BAT, BBA VBA RBS XB6S): Delete macros.
	(BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
	(BB, BD, RBX, XC6): Update for new macros.
	(powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
	crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
	e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
	* ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.

include/
	* opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.

gas/
	* config/tc-ppc.c (md_assemble): Delete handling of fake operands.
	* testsuite/gas/ppc/common.s (crmove, cror, or., or, nor., nor): Add
	test of extended mnemonics.
	* testsuite/gas/ppc/common.d: Likewise.  Don't match instruction offset.
	* testsuite/gas/ppc/spe.s (evor, evnor): Add test of extended mnemonics.
	* testsuite/gas/ppc/spe.d: Likewise.  Don't match instruction offset.
 2018-05-21 17:31:07 -05:00
Jim Wilson
7f99954970 RISC-V: Add RV32E support. 
Kito Cheng  <kito.cheng@gmail.com>
	Monk Chiang  <sh.chiang04@gmail.com>

	bfd/
	* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Handle
	EF_RISCV_RVE.

	binutils/
	* readelf.c (get_machine_flags): Handle EF_RISCV_RVE.

	gas/
	* config/tc-riscv.c (rve_abi): New.
	(riscv_set_options): Add rve field.  Initialize it.
	(riscv_set_rve) New function.
	(riscv_set_arch): Support 'e' ISA subset.
	(reg_lookup_internal): If rve, check register is available.
	(riscv_set_abi): New parameter rve.
	(md_parse_option): Pass new argument to riscv_set_abi.
	(riscv_after_parse_args): Call riscv_set_rve.  If rve_abi, set
	EF_RISCV_RVE.
	* doc/c-riscv.texi (-mabi): Document new ilp32e argument.

	include/
	* elf/riscv.h (EF_RISCV_RVE): New define.
 2018-05-18 14:03:18 -07:00
John Darrington
7b4ae82428 Add support for the Freescale s12z processor. 
bfd	* Makefile.am: Add s12z files.
	* Makefile.in: Regenerate.
	* archures.c: Add bfd_s12z_arch.
	* bfd-in.h: Add exports of bfd_putb24 and bfd_putl24.
	* bfd-in2.h: Regenerate.
	* config.bfd: Add s12z target.
	* configure.ac: Add s12z target.
	* configure: Regenerate.
	* cpu-s12z.c: New file.
	* elf32-s12z.c: New file.
	* libbfd.c (bfd_putb24): New function.
	(bfd_putl24): New function.
	* libbfd.h: Regenerate.
	* reloc.c: Add s12z relocations.
	(bfd_get_reloc_size): Handle size 5 relocs.
	* targets.c: Add s12z_elf32_vec.

opcodes	* Makefile.am: Add support for s12z architecture.
	* configure.ac: Likewise.
	* disassemble.c: Likewise.
	* disassemble.h: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* s12z-dis.c: New file.
	* s12z.h: New file.

include	* elf/s12z.h: New header.

ld	* Makefile.am: Add support for s12z architecture.
	* configure.tgt: Likewise.
	* Makefile.in: Regenerate.
	* emulparams/m9s12zelf.sh: New file.
	* scripttempl/elfm9s12z.sc: New file.
	* testsuite/ld-discard/static.d: Expect to fail for the s12z
	target.
	* testsuite/ld-elf/endsym.d: Likewise.
	* testsuite/ld-elf/merge.d: Likewise.
	* testsuite/ld-elf/pr14926.d: Skip for the s12z target.
	* testsuite/ld-elf/sec64k.exp: Likewise.
	* testsuite/ld-s12z: New directory.
	* testsuite/ld-s12z/opr-linking.d: New file.
	* testsuite/ld-s12z/opr-linking.s: New file.
	* testsuite/ld-s12z/relative-linking.d: New file.
	* testsuite/ld-s12z/relative-linking.s: New file.
	* testsuite/ld-s12z/z12s.exp: New file.

gas	* Makefile.am: Add support for s12z target.
	* Makefile.in: Regenerate.
	* NEWS: Mention the new support.
	* config/tc-s12z.c: New file.
	* config/tc-s12z.h: New file.
	* configure.tgt: Add  s12z support.
	* doc/Makefile.am: Likewise.
	* doc/Makefile.in: Regenerate.
	* doc/all.texi: Add s12z documentation.
	* doc/as.textinfo: Likewise.
	* doc/c-s12z.texi: New file.
	* testsuite/gas/s12z: New directory.
	* testsuite/gas/s12z/abs.d: New file.
	* testsuite/gas/s12z/abs.s: New file.
	* testsuite/gas/s12z/adc-imm.d: New file.
	* testsuite/gas/s12z/adc-imm.s: New file.
	* testsuite/gas/s12z/adc-opr.d: New file.
	* testsuite/gas/s12z/adc-opr.s: New file.
	* testsuite/gas/s12z/add-imm.d: New file.
	* testsuite/gas/s12z/add-imm.s: New file.
	* testsuite/gas/s12z/add-opr.d: New file.
	* testsuite/gas/s12z/add-opr.s: New file.
	* testsuite/gas/s12z/and-imm.d: New file.
	* testsuite/gas/s12z/and-imm.s: New file.
	* testsuite/gas/s12z/and-opr.d: New file.
	* testsuite/gas/s12z/and-opr.s: New file.
	* testsuite/gas/s12z/and-or-cc.d: New file.
	* testsuite/gas/s12z/and-or-cc.s: New file.
	* testsuite/gas/s12z/bfext-special.d: New file.
	* testsuite/gas/s12z/bfext-special.s: New file.
	* testsuite/gas/s12z/bfext.d: New file.
	* testsuite/gas/s12z/bfext.s: New file.
	* testsuite/gas/s12z/bit-manip.d: New file.
	* testsuite/gas/s12z/bit-manip.s: New file.
	* testsuite/gas/s12z/bit.d: New file.
	* testsuite/gas/s12z/bit.s: New file.
	* testsuite/gas/s12z/bra-expression-defined.d: New file.
	* testsuite/gas/s12z/bra-expression-defined.s: New file.
	* testsuite/gas/s12z/bra-expression-undef.d: New file.
	* testsuite/gas/s12z/bra-expression-undef.s: New file.
	* testsuite/gas/s12z/bra.d: New file.
	* testsuite/gas/s12z/bra.s: New file.
	* testsuite/gas/s12z/brclr-symbols.d: New file.
	* testsuite/gas/s12z/brclr-symbols.s: New file.
	* testsuite/gas/s12z/brset-clr-opr-imm-rel.d: New file.
	* testsuite/gas/s12z/brset-clr-opr-imm-rel.s: New file.
	* testsuite/gas/s12z/brset-clr-opr-reg-rel.d: New file.
	* testsuite/gas/s12z/brset-clr-opr-reg-rel.s: New file.
	* testsuite/gas/s12z/brset-clr-reg-imm-rel.d: New file.
	* testsuite/gas/s12z/brset-clr-reg-imm-rel.s: New file.
	* testsuite/gas/s12z/brset-clr-reg-reg-rel.d: New file.
	* testsuite/gas/s12z/brset-clr-reg-reg-rel.s: New file.
	* testsuite/gas/s12z/clb.d: New file.
	* testsuite/gas/s12z/clb.s: New file.
	* testsuite/gas/s12z/clr-opr.d: New file.
	* testsuite/gas/s12z/clr-opr.s: New file.
	* testsuite/gas/s12z/clr.d: New file.
	* testsuite/gas/s12z/clr.s: New file.
	* testsuite/gas/s12z/cmp-imm.d: New file.
	* testsuite/gas/s12z/cmp-imm.s: New file.
	* testsuite/gas/s12z/cmp-opr-inc.d: New file.
	* testsuite/gas/s12z/cmp-opr-inc.s: New file.
	* testsuite/gas/s12z/cmp-opr-rdirect.d: New file.
	* testsuite/gas/s12z/cmp-opr-rdirect.s: New file.
	* testsuite/gas/s12z/cmp-opr-reg.d: New file.
	* testsuite/gas/s12z/cmp-opr-reg.s: New file.
	* testsuite/gas/s12z/cmp-opr-rindirect.d: New file.
	* testsuite/gas/s12z/cmp-opr-rindirect.s: New file.
	* testsuite/gas/s12z/cmp-opr-sxe4.d: New file.
	* testsuite/gas/s12z/cmp-opr-sxe4.s: New file.
	* testsuite/gas/s12z/cmp-opr-xys.d: New file.
	* testsuite/gas/s12z/cmp-opr-xys.s: New file.
	* testsuite/gas/s12z/cmp-s-imm.d: New file.
	* testsuite/gas/s12z/cmp-s-imm.s: New file.
	* testsuite/gas/s12z/cmp-s-opr.d: New file.
	* testsuite/gas/s12z/cmp-s-opr.s: New file.
	* testsuite/gas/s12z/cmp-xy.d: New file.
	* testsuite/gas/s12z/cmp-xy.s: New file.
	* testsuite/gas/s12z/com-opr.d: New file.
	* testsuite/gas/s12z/com-opr.s: New file.
	* testsuite/gas/s12z/complex-shifts.d: New file.
	* testsuite/gas/s12z/complex-shifts.s: New file.
	* testsuite/gas/s12z/db-tb-cc-opr.d: New file.
	* testsuite/gas/s12z/db-tb-cc-opr.s: New file.
	* testsuite/gas/s12z/db-tb-cc-reg.d: New file.
	* testsuite/gas/s12z/db-tb-cc-reg.s: New file.
	* testsuite/gas/s12z/dbCC.d: New file.
	* testsuite/gas/s12z/dbCC.s: New file.
	* testsuite/gas/s12z/dec-opr.d: New file.
	* testsuite/gas/s12z/dec-opr.s: New file.
	* testsuite/gas/s12z/dec.d: New file.
	* testsuite/gas/s12z/dec.s: New file.
	* testsuite/gas/s12z/div.d: New file.
	* testsuite/gas/s12z/div.s: New file.
	* testsuite/gas/s12z/eor.d: New file.
	* testsuite/gas/s12z/eor.s: New file.
	* testsuite/gas/s12z/exg.d: New file.
	* testsuite/gas/s12z/exg.s: New file.
	* testsuite/gas/s12z/ext24-ld-xy.d: New file.
	* testsuite/gas/s12z/ext24-ld-xy.s: New file.
	* testsuite/gas/s12z/inc-opr.d: New file.
	* testsuite/gas/s12z/inc-opr.s: New file.
	* testsuite/gas/s12z/inc.d: New file.
	* testsuite/gas/s12z/inc.s: New file.
	* testsuite/gas/s12z/inh.d: New file.
	* testsuite/gas/s12z/inh.s: New file.
	* testsuite/gas/s12z/jmp.d: New file.
	* testsuite/gas/s12z/jmp.s: New file.
	* testsuite/gas/s12z/jsr.d: New file.
	* testsuite/gas/s12z/jsr.s: New file.
	* testsuite/gas/s12z/ld-imm-page2.d: New file.
	* testsuite/gas/s12z/ld-imm-page2.s: New file.
	* testsuite/gas/s12z/ld-imm.d: New file.
	* testsuite/gas/s12z/ld-imm.s: New file.
	* testsuite/gas/s12z/ld-immu18.d: New file.
	* testsuite/gas/s12z/ld-immu18.s: New file.
	* testsuite/gas/s12z/ld-large-direct.d: New file.
	* testsuite/gas/s12z/ld-large-direct.s: New file.
	* testsuite/gas/s12z/ld-opr.d: New file.
	* testsuite/gas/s12z/ld-opr.s: New file.
	* testsuite/gas/s12z/ld-s-opr.d: New file.
	* testsuite/gas/s12z/ld-s-opr.s: New file.
	* testsuite/gas/s12z/ld-small-direct.d: New file.
	* testsuite/gas/s12z/ld-small-direct.s: New file.
	* testsuite/gas/s12z/lea-immu18.d: New file.
	* testsuite/gas/s12z/lea-immu18.s: New file.
	* testsuite/gas/s12z/lea.d: New file.
	* testsuite/gas/s12z/lea.s: New file.
	* testsuite/gas/s12z/mac.d: New file.
	* testsuite/gas/s12z/mac.s: New file.
	* testsuite/gas/s12z/min-max.d: New file.
	* testsuite/gas/s12z/min-max.s: New file.
	* testsuite/gas/s12z/mod.d: New file.
	* testsuite/gas/s12z/mod.s: New file.
	* testsuite/gas/s12z/mov.d: New file.
	* testsuite/gas/s12z/mov.s: New file.
	* testsuite/gas/s12z/mul-imm.d: New file.
	* testsuite/gas/s12z/mul-imm.s: New file.
	* testsuite/gas/s12z/mul-opr-opr.d: New file.
	* testsuite/gas/s12z/mul-opr-opr.s: New file.
	* testsuite/gas/s12z/mul-opr.d: New file.
	* testsuite/gas/s12z/mul-opr.s: New file.
	* testsuite/gas/s12z/mul-reg.d: New file.
	* testsuite/gas/s12z/mul-reg.s: New file.
	* testsuite/gas/s12z/mul.d: New file.
	* testsuite/gas/s12z/mul.s: New file.
	* testsuite/gas/s12z/neg-opr.d: New file.
	* testsuite/gas/s12z/neg-opr.s: New file.
	* testsuite/gas/s12z/not-so-simple-shifts.d: New file.
	* testsuite/gas/s12z/not-so-simple-shifts.s: New file.
	* testsuite/gas/s12z/opr-18u.d: New file.
	* testsuite/gas/s12z/opr-18u.s: New file.
	* testsuite/gas/s12z/opr-expr.d: New file.
	* testsuite/gas/s12z/opr-expr.s: New file.
	* testsuite/gas/s12z/opr-ext-18.d: New file.
	* testsuite/gas/s12z/opr-ext-18.s: New file.
	* testsuite/gas/s12z/opr-idx-24-reg.d: New file.
	* testsuite/gas/s12z/opr-idx-24-reg.s: New file.
	* testsuite/gas/s12z/opr-idx3-reg.d: New file.
	* testsuite/gas/s12z/opr-idx3-reg.s: New file.
	* testsuite/gas/s12z/opr-idx3-xysp-24.d: New file.
	* testsuite/gas/s12z/opr-idx3-xysp-24.s: New file.
	* testsuite/gas/s12z/opr-indirect-expr.d: New file.
	* testsuite/gas/s12z/opr-indirect-expr.s: New file.
	* testsuite/gas/s12z/opr-symbol.d: New file.
	* testsuite/gas/s12z/opr-symbol.s: New file.
	* testsuite/gas/s12z/or-imm.d: New file.
	* testsuite/gas/s12z/or-imm.s: New file.
	* testsuite/gas/s12z/or-opr.d: New file.
	* testsuite/gas/s12z/or-opr.s: New file.
	* testsuite/gas/s12z/p2-mul.d: New file.
	* testsuite/gas/s12z/p2-mul.s: New file.
	* testsuite/gas/s12z/page2-inh.d: New file.
	* testsuite/gas/s12z/page2-inh.s: New file.
	* testsuite/gas/s12z/psh-pul.d: New file.
	* testsuite/gas/s12z/psh-pul.s: New file.
	* testsuite/gas/s12z/qmul.d: New file.
	* testsuite/gas/s12z/qmul.s: New file.
	* testsuite/gas/s12z/rotate.d: New file.
	* testsuite/gas/s12z/rotate.s: New file.
	* testsuite/gas/s12z/s12z.exp: New file.
	* testsuite/gas/s12z/sat.d: New file.
	* testsuite/gas/s12z/sat.s: New file.
	* testsuite/gas/s12z/sbc-imm.d: New file.
	* testsuite/gas/s12z/sbc-imm.s: New file.
	* testsuite/gas/s12z/sbc-opr.d: New file.
	* testsuite/gas/s12z/sbc-opr.s: New file.
	* testsuite/gas/s12z/shift.d: New file.
	* testsuite/gas/s12z/shift.s: New file.
	* testsuite/gas/s12z/simple-shift.d: New file.
	* testsuite/gas/s12z/simple-shift.s: New file.
	* testsuite/gas/s12z/single-ops.d: New file.
	* testsuite/gas/s12z/single-ops.s: New file.
	* testsuite/gas/s12z/specd6.d: New file.
	* testsuite/gas/s12z/specd6.s: New file.
	* testsuite/gas/s12z/st-large-direct.d: New file.
	* testsuite/gas/s12z/st-large-direct.s: New file.
	* testsuite/gas/s12z/st-opr.d: New file.
	* testsuite/gas/s12z/st-opr.s: New file.
	* testsuite/gas/s12z/st-s-opr.d: New file.
	* testsuite/gas/s12z/st-s-opr.s: New file.
	* testsuite/gas/s12z/st-small-direct.d: New file.
	* testsuite/gas/s12z/st-small-direct.s: New file.
	* testsuite/gas/s12z/st-xy.d: New file.
	* testsuite/gas/s12z/st-xy.s: New file.
	* testsuite/gas/s12z/sub-imm.d: New file.
	* testsuite/gas/s12z/sub-imm.s: New file.
	* testsuite/gas/s12z/sub-opr.d: New file.
	* testsuite/gas/s12z/sub-opr.s: New file.
	* testsuite/gas/s12z/tfr.d: New file.
	* testsuite/gas/s12z/tfr.s: New file.
	* testsuite/gas/s12z/trap.d: New file.
	* testsuite/gas/s12z/trap.s: New file.

binutils* readelf.c: Add support for s12z architecture.
	* testsuite/lib/binutils-common.exp (is_elf_format): Excluse s12z
	targets.
 2018-05-18 15:26:18 +01:00
Tamar Christina
f9830ec165 Implement Read/Write constraints on system registers on AArch64 
This patch adds constraints for read and write only system registers with the
msr and mrs instructions.  The code will treat having both flags set and none
set as the same.  These flags add constraints that must be matched up. e.g. a
system register with a READ only flag set, can only be used with mrs.  If The
constraint fails a warning is emitted.

Examples of the warnings generated:

test.s: Assembler messages:
test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3'
test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0'
test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3'

and disassembly notes:

0000000000000000 <main>:
   0:	d5130503 	msr	dbgdtrtx_el0, x3
   4:	d5130503 	msr	dbgdtrtx_el0, x3
   8:	d5330503 	mrs	x3, dbgdtrrx_el0
   c:	d5330503 	mrs	x3, dbgdtrrx_el0
  10:	d5180003 	msr	midr_el1, x3	; note: writing to a read-only register.

Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during
disassembly the constraints are use to disambiguate between the two.  An exact
constraint match is always prefered over partial ones if available.

As always the warnings can be suppressed with -w and also be made errors using
warnings as errors.

binutils/

	PR binutils/21446
	* doc/binutils.texi (-M): Document AArch64 options.

gas/

	PR binutils/21446
	* testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test.
	* testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise.
	* testsuite/gas/aarch64/sysreg-diagnostic.s: New.
	* testsuite/gas/aarch64/sysreg-diagnostic.l: New.
	* testsuite/gas/aarch64/sysreg-diagnostic.d: New.

include/

	PR binutils/21446
	* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.

opcodes/

	PR binutils/21446
	* aarch64-asm.c (opintl.h): Include.
	(aarch64_ins_sysreg): Enforce read/write constraints.
	* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
	* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
	(F_REG_READ, F_REG_WRITE): New.
	* aarch64-opc.c (aarch64_print_operand): Generate notes for
	AARCH64_OPND_SYSREG.
	(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
	(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
	mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
	id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
	id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
	id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
	mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
	id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
	id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
	id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
	csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
	rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
	mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
	mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
	pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
	* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
	msr (F_SYS_WRITE), mrs (F_SYS_READ).
 2018-05-15 17:17:36 +01:00
Tamar Christina
7d02540ab7 Allow non-fatal errors to be emitted and for disassembly notes be placed on AArch64 
This patch adds a new platform option "notes" that can be used to indicate if
disassembly notes should be placed in the disassembly as comments.

These notes can contain information about a failing constraint such as reading
from a write-only register.  The disassembly will not be blocked because of this
but -M notes will emit a comment saying that the operation is not allowed.

For assembly this patch adds a new non-fatal status for errors.  This is
essentially a warning.  The reason for not creating an actual warning type is
that this causes the interaction between the ordering of warnings and errors to
be problematic.  Currently the error buffer is almost always filled because of
the way operands are matched during assembly. An earlier template may have put
an error there that would only be displayed if no other template matches or
generates a higher priority error.  But by definition a warning is lower
priority than a warning, so the error (which is incorrect if another template
matched) will supersede the warning.  By treating warnings as errors and only
later relaxing the severity this relationship keeps working and the existing
reporting infrastructure can be re-used.

binutils/

	PR binutils/21446
	* doc/binutils.texi (-M): Document AArch64 options.
	* NEWS: Document notes and warnings.

gas/

	PR binutils/21446
	* config/tc-aarch64.c (print_operands): Indicate no notes.
	(output_operand_error_record): Support non-fatal errors.
	(output_operand_error_report, warn_unpredictable_ldst, md_assemble):
	Likewise.

include/

	PR binutils/21446
	* opcode/aarch64.h (aarch64_operand_error): Add non_fatal.
	(aarch64_print_operand): Support notes.

opcodes/

	PR binutils/21446
	* aarch64-dis.c (no_notes: New.
	(parse_aarch64_dis_option): Support notes.
	(aarch64_decode_insn, print_operands): Likewise.
	(print_aarch64_disassembler_options): Document notes.
	* aarch64-opc.c (aarch64_print_operand): Support notes.
 2018-05-15 17:17:36 +01:00
Tamar Christina
561a72d4dd Modify AArch64 Assembly and disassembly functions to be able to fail and report why. 
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.

These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.

This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.

The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.

gas/

	PR binutils/21446
	* config/tc-aarch64.c (parse_sys_reg): Return register flags.
	(parse_operands): Fill in register flags.

gdb/

	PR binutils/21446
	* aarch64-tdep.c (aarch64_analyze_prologue,
	aarch64_software_single_step, aarch64_displaced_step_copy_insn):
	Indicate not interested in errors.

include/

	PR binutils/21446
	* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
	(aarch64_decode_insn): Accept error struct.

opcodes/

	PR binutils/21446
	* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
	and take error struct.
	* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
	aarch64_ins_reglist, aarch64_ins_ldst_reglist,
	aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
	aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
	aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
	aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
	aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
	aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
	aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
	aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
	aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
	aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
	aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
	aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
	aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
	aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
	aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
	aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
	aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
	aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
	aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
	aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
	aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
	aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
	aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
	* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
	* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
	aarch64_ext_reglist, aarch64_ext_ldst_reglist,
	aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
	aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
	aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
	aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
	aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
	aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
	aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
	aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
	aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
	aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
	aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
	aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
	aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
	aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
	aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
	aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
	aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
	aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
	aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
	aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
	aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
	aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
	aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
	(determine_disassembling_preference, aarch64_decode_insn,
	print_insn_aarch64_word, print_insn_data): Take errors struct.
	(print_insn_aarch64): Use errors.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-gen.c (print_operand_inserter): Use errors and change type to
	boolean in aarch64_insert_operan.
	(print_operand_extractor): Likewise.
	* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 2018-05-15 17:17:36 +01:00
Francois H. Theron
1678bd35a3 Fix error messages in the NFP sources when building for 32-bit targets. 
bfd	* targets.c: Wrap nfp_elf64_vec in BFD64 ifdef.

include	* opcode/nfp.h: Use uint64_t instead of bfd_vma.

opcodes	* nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 2018-05-15 13:28:06 +01:00
John Darrington
637b19704c Add support for detecting Freescale S12Z binaries in readelf. 
* include/elf/common.h (EM_S12Z): New macro
* binutils/readelf.c (get_machine_name): EM_S12Z - handle new case.
 2018-05-10 12:51:42 +01:00
Alan Modra
84f9f8c330 PR22069, Several instances of register accidentally spelled as regsiter 
PR 22069
binutils/
	* od-macho.c (dump_unwind_encoding_x86): Adjust for macro renaming.
cpu/ChangeLog
	* or1kcommon.cpu (spr-reg-info): Typo fix.
include/ChangeLog
	* mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS):
	Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS.
	(MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from
	MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS.
opcodes/ChangeLog
	* cr16-opc.c (cr16_instruction): Comment typo fix.
	* hppa-dis.c (print_insn_hppa): Likewise.
sim/ppc/ChangeLog
	* e500_registers.h: Comment typo fix.
	* ppc-instructions (ppc_insn_mfcr): Likewise.
 2018-05-09 15:55:28 +09:30
Jim Wilson
e6f372ba66 RISC-V: Add missing hint instructions from RV128I. 
gas/
	* testsuite/gas/riscv/c-zero-imm.d: Add more tests.
	* testsuite/gas/riscv/c-zero-imm.s: Likewise.
	* testsuite/gas/riscv/c-zero-reg.d: Fix typo in test.  Add disabled
	future test for RV128 support.
	* testsuite/gas/riscv/c-zero-reg.s: Likewise.

	include/
	* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
	(MATCH_C_SRAI64, MASK_C_SRAI64): New.
	(MATCH_C_SLLI64, MASK_C_SLLI64): New.

	opcodes/
	* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
	(match_c_slli64, match_srxi_as_c_srxi): New.
	(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
	<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
	<c.slli, c.srli, c.srai>: Use match_s_slli.
	<c.slli64, c.srli64, c.srai64>: New.
 2018-05-08 15:46:19 -07:00
Peter Bergner
2ceb7719f7 Cleanup ppc code dealing with opcode dumps. 
include/
	* opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned.
	(vle_num_opcodes): Likewise.
	(spe2_num_opcodes): Likewise.

opcodes/
	* ppc-opc.c (powerpc_num_opcodes): Likewise.
	(vle_num_opcodes): Likewise.
	(spe2_num_opcodes): Likewise.
	* ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
	initialization loop.
	(disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
	(disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
	only once.

gas/
	* config/tc-ppc.c (ppc_setup_opcodes) <powerpc_opcodes>: Rewrite code
	to dump the entire opcode table.
	(ppc_setup_opcodes) <spe2_opcodes>: Likewise.
	(ppc_setup_opcodes) <vle_opcodes>: Likewise.  Fix calculation of
	opcode index.
 2018-05-07 09:40:59 -05:00
Alan Modra
602f165704 -Wstringop-truncation warnings 
This patch is aimed at silencing gcc8 -Wstringop-truncation warnings.

Unfortunately adding  __attribute__ ((__nonstring)) doesn't work in a
number of the places patched here, (see
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643) so if you have
recent glibc headers installed you'll need to configure binutils with
--disable-werror to compile using gcc8 or gcc9.

include/
	* ansidecl.h: Import from gcc.
	* coff/internal.h (struct internal_scnhdr): Add ATTRIBUTE_NONSTRING
	to s_name.
	(struct internal_syment): Add ATTRIBUTE_NONSTRING to _n_name.
bfd/
	* elf-linux-core.h (struct elf_external_linux_prpsinfo32_ugid32),
	(struct elf_external_linux_prpsinfo32_ugid16),
	(struct elf_external_linux_prpsinfo64_ugid32),
	(struct elf_external_linux_prpsinfo64_ugid16): Add ATTRIBUTE_NONSTRING
	to pr_fname and pr_psargs fields.  Remove GCC diagnostic pragmas.
	Move comment to..
	* elf.c (elfcore_write_prpsinfo): ..here.  Indent nested preprocessor
	directives.
	* elf32-arm.c (elf32_arm_nabi_write_core_note): Add ATTRIBUTE_NONSTRING
	to data.
	* elf32-ppc.c (ppc_elf_write_core_note): Likewise.
	* elf32-s390.c (elf_s390_write_core_note): Likewise.
	* elf64-s390.c (elf_s390_write_core_note): Likewise.
	* elfxx-aarch64.c (_bfd_aarch64_elf_write_core_note): Likewise.
	* elf64-x86-64.c (elf_x86_64_write_core_note): Add GCC diagnostic
	pragmas.
	* peXXigen.c (_bfd_XXi_swap_scnhdr_out): Use strnlen to avoid
	false positive gcc-8 warning.
gas/
	* config/obj-evax.c (shorten_identifier): Use memcpy in place
	of strncpy.
	* config/obj-macho.c (obj_mach_o_make_or_get_sect): Ensure
	segname and sectname fields are NUL terminated.
 2018-05-04 18:58:23 +09:30
Francois H. Theron
fe944acf8f This patch adds support to objdump for disassembly of NFP (Netronome Flow Processor) ELF files (.nffw) as well as some basic readelf support. 
bfd	* Makefile.am: Added NFP files to build.
	* archures.c: Added bfd_arch_nfp
	* config.bfd: Added NFP support.
	* configure.ac: Added NFP support.
	* cpu-nfp.c: New, for NFP support.
	* elf-bfd.h: Added elf_section_info()
	* elf64-nfp.c: New, for NFP support.
	* po/SRC-POTFILES.in: Added NFP source files.
	* targets.c: Added nfp_elf64_vec
	* bfd-in2.h: Regenerate.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

binutils* readelf.c: Very basic support for EM_NFP and its section types.
	* testsuite/binutils-all/nfp: New directory.
	* testsuite/binutils-all/nfp/objdump.exp: New file.  Run new
	tests.
	* testsuite/binutils-all/nfp/test2_ctx8.d: New file.
	* testsuite/binutils-all/nfp/test2_no-pc_ctx4.d: New file.
	* testsuite/binutils-all/nfp/test1.d: New file.
	* testsuite/binutils-all/nfp/nfp6000.nffw: New file.
	* testsuite/binutils-all/nfp/test2_nfp6000.nffw: New file.
	* NEWS: Mention the new support.

include	* dis-asm.h: Added print_nfp_disassembler_options prototype.
	* elf/common.h: Added EM_NFP, officially assigned. See Google Group
	Generic System V Application Binary Interface.
	* elf/nfp.h: New, for NFP support.
	* opcode/nfp.h: New, for NFP support.

opcodes	Makefile.am: Added nfp-dis.c.
	configure.ac: Added bfd_nfp_arch.
	disassemble.h: Added print_insn_nfp prototype.
	disassemble.c: Added ARCH_nfp and call to print_insn_nfp
	nfp-dis.c: New, for NFP support.
	po/POTFILES.in: Added nfp-dis.c to the list.
	Makefile.in: Regenerate.
	configure: Regenerate.
 2018-04-30 17:02:59 +01:00
Christophe Lyon
5c5a4843ec [ARM] Add TLS relocations for FDPIC. 
Define and handle TLS relocations for FDPIC in BFD and gas.

In gas, the new relocations are rejected if the --fdpic option was not
specified.

We also define the __tdata_start symbol to mark the start of the
.tdata section. This allows FDPIC static binaries to find the start of
.tdata section, since phdr->p_vaddr of TLS segment is not a valid
value for FDPIC.

2018-04-25  Christophe Lyon  <christophe.lyon@st.com>
	Mickaël Guêné  <mickael.guene@st.com>

	bfd/:
	* bfd-in2.h (BFD_RELOC_ARM_TLS_GD32_FDPIC)
	(BFD_RELOC_ARM_TLS_LDM32_FDPIC, BFD_RELOC_ARM_TLS_IE32_FDPIC): New
	relocations.
	* elf32-arm.c (elf32_arm_howto_table_2): Add R_ARM_TLS_GD32_FDPIC,
	R_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_IE32_FDPIC relocations.
	(elf32_arm_reloc_map): Add R_ARM_TLS_GD32_FDPIC,
	R_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_IE32_FDPIC.
	(struct elf32_arm_link_hash_table): Update comment.
	(elf32_arm_final_link_relocate): Handle TLS FDPIC relocations.
	(IS_ARM_TLS_RELOC): Likewise.
	(elf32_arm_check_relocs): Likewise.
	(allocate_dynrelocs_for_symbol): Likewise.
	(elf32_arm_size_dynamic_sections): Update comment.
	* reloc.c: Add BFD_RELOC_ARM_TLS_GD32_FDPIC,
	BFD_RELOC_ARM_TLS_LDM32_FDPIC, BFD_RELOC_ARM_TLS_IE32_FDPIC.

	gas/
	* config/tc-arm.c (reloc_names): Add TLSGD_FDPIC, TLSLDM_FDPIC,
	GOTTPOFF_FDIC relocations.
	(md_apply_fix): Handle the new TLS FDPIC relocations.
	(tc_gen_reloc): Likewise.
	(arm_fix_adjustable): Likewise.

	include/
	* elf/arm.h: Add R_ARM_TLS_GD32_FDPIC, R_ARM_TLS_LDM32_FDPIC,
	R_ARM_TLS_IE32_FDPIC.

	ld/
	* scripttempl/elf.sc: Define __tdata_start for .tdata section.
 2018-04-25 20:57:02 +00:00
Christophe Lyon
188fd7aea6 [ARM] Add FDPIC relocations definitions 
Add FDPIC relocation definitions in BFD and gas.
Gas rejects them if the --fdpic option was not specified.

2018-04-25  Christophe Lyon  <christophe.lyon@st.com>
	Mickaël Guêné  <mickael.guene@st.com>

	bfd/
	* bfd-in2.c (BFD_RELOC_ARM_GOTFUNCDESC)
	(BFD_RELOC_ARM_GOTOFFFUNCDESC, BFD_RELOC_ARM_FUNCDESC)
	(BFD_RELOC_ARM_FUNCDESC_VALUE): New.
	* elf32-arm.c (elf32_arm_howto_table_2): Add R_ARM_GOTFUNCDESC,
	R_ARM_GOTOFFFUNCDESC, R_ARM_FUNCDESC, R_ARM_FUNCDESC_VALUE.
	(elf32_arm_howto_from_type): Take new members of
	elf32_arm_howto_table_2 into account.
	(elf32_arm_reloc_map): Add BFD_RELOC_ARM_GOTFUNCDESC,
	BFD_RELOC_ARM_GOTOFFFUNCDESC, BFD_RELOC_ARM_FUNCDESC,
	BFD_RELOC_ARM_FUNCDESC_VALUE.
	* reloc.c: Add BFD_RELOC_ARM_GOTFUNCDESC,
	BFD_RELOC_ARM_GOTOFFFUNCDESC, BFD_RELOC_ARM_FUNCDESC,
	BFD_RELOC_ARM_FUNCDESC_VALUE.

	gas/
	* config/tc-arm.c (reloc_names): Add gotfuncdesc, gotofffuncdesc,
	funcdesc.
	(md_apply_fix): Support the new relocations.
	(tc_gen_reloc): Likewise.
	* testsuite/gas/arm/reloc-fdpic.d: New.
	* testsuite/gas/arm/reloc-fdpic.s: New.

	include/
	* elf/arm.h (R_ARM_GOTFUNCDESC, R_ARM_GOTOFFFUNCDESC)
	(R_ARM_FUNCDESC)
	(R_ARM_FUNCDESC_VALUE): Define new relocations.
 2018-04-25 20:51:53 +00:00
Christophe Lyon
18a2033805 [ARM] Add FDPIC OSABI flag support. 
ELF files targetting ARM FDPIC use the ELFOSABI_ARM_FDPIC flag.
Set it appropriately in file generators (eg. gas), and handle it in
readers (eg. readelf).

2018-04-25  Christophe Lyon  <christophe.lyon@st.com>
	Mickaël Guêné  <mickael.guene@st.com>

	bfd/
	* elf32-arm.c (elf32_arm_print_private_bfd_data): Support
	EF_ARM_PIC and ELFOSABI_ARM_FDPIC.
	(elf32_arm_post_process_headers): Support ELFOSABI_ARM_FDPIC.
	(ELF_OSABI): Define to ELFOSABI_ARM_FDPIC.

	binutils/
	* readelf.c (decode_ARM_machine_flags): Support EF_ARM_PIC.
	(get_osabi_name): Support ELFOSABI_ARM_FDPIC.

	gas/
	* config/tc-arm.c (arm_fdpic): New.
	(elf32_arm_target_format): Support FDPIC.
	(OPTION_FDPIC): New.
	(md_longopts): Support FDPIC.
	(md_parse_option): Likewise.
	(md_show_usage): Likewise.

	include/
	* elf/arm.h (EF_ARM_FDPIC): New.
 2018-04-25 20:49:57 +00:00
Alan Modra
3596d8ceb2 Remove mips aout, coff, and pe support 
include/coff/mips.h needs to stay for ecoff debug support.

include/
	* coff/mipspe.h: Delete.
bfd/
	* Makefile.am: Remove mips aout, coff, and pe support.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* coff-mips.c: Delete
	* mipsbsd.c: Delete
	* pe-mips.c: Delete
	* pei-mips.c: Delete
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
 2018-04-18 17:09:50 +09:30
Alan Modra
c65c21e1ff various i386-aout and i386-coff target removal 
Also tidies some other aout leftovers in binutils-common.exp.

bfd/
	* Makefile.am: Remove support for assorted i386 aout and coff targets.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* doc/bfdint.texi: Likewise.
	* targets.c: Likewise.
	* freebsd.h: Delete.
	* i386dynix.c: Delete.
	* i386freebsd.c: Delete.
	* i386linux.c: Delete.
	* i386mach3.c: Delete.
	* i386netbsd.c: Delete.
	* i386os9k.c: Delete.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
binutils/
	* testsuite/lib/binutils-common.exp: Remove support for assorted
	aout targets.
gas/
	* Makefile.am: Remove support for assorted i386 aout and coff targets.
	* config/obj-elf.c: Likewise.
	* config/tc-i386.h: Likewise.
	* configure.ac: Likewise.
	* configure.tgt: Likewise.
	* config/te-dynix.h: Delete.
	* config/te-i386aix.h: Delete.
	* config/te-mach.h: Delete.
	* Makefile.in: Regenerate.
	* config.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
include/
	* aout/dynix3.h: Delete.
ld/
	* Makefile.am: Remove support for assorted i386 aout and coff targets.
	* configure.tgt: Likewise.
	* testsuite/ld-discard/discard.exp: Likewise.
	* testsuite/ld-elf/binutils.exp: Likewise.
	* testsuite/ld-elf/tls.exp: Likewise.
	* testsuite/ld-elf/tls_common.exp: Likewise.
	* testsuite/ld-elfvers/vers.exp: Likewise.
	* testsuite/ld-elfvsb/elfvsb.exp: Likewise.
	* testsuite/ld-elfweak/elfweak.exp: Likewise.
	* testsuite/ld-gc/abi-note.d: Likewise.
	* testsuite/ld-gc/pr19167.d: Likewise.
	* testsuite/ld-gc/pr20022.d: Likewise.
	* testsuite/ld-gc/start.d: Likewise.
	* testsuite/ld-gc/stop.d: Likewise.
	* testsuite/ld-i386/i386.exp: Likewise.
	* testsuite/ld-ifunc/binutils.exp: Likewise.
	* testsuite/ld-ifunc/ifunc.exp: Likewise.
	* testsuite/ld-linkonce/linkonce.exp: Likewise.
	* testsuite/ld-plugin/lto.exp: Likewise.
	* testsuite/ld-scripts/empty-address-2a.d: Likewise.
	* testsuite/ld-scripts/empty-address-2b.d: Likewise.
	* testsuite/ld-scripts/phdrs2.exp: Likewise.
	* testsuite/ld-scripts/section-match-1.d: Likewise.
	* testsuite/ld-shared/shared.exp: Likewise.
	* testsuite/ld-size/size.exp: Likewise.
	* testsuite/ld-sparc/sparc.exp: Likewise.
	* emulparams/i386coff.sh: Delete.
	* emulparams/i386linux.sh: Delete.
	* emulparams/i386mach.sh: Delete.
	* emulparams/i386nbsd.sh: Delete.
	* emulparams/vsta.sh: Delete.
	* scripttempl/i386coff.sc: Delete.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
 2018-04-18 09:34:19 +09:30
Alan Modra
884d4d8aa7 Correct ChangeLog dates for git commit 3f0a5f17d7 2018-04-18 09:34:19 +09:30
Michael Eager
3f0a5f17d7 [MicroBlaze] PIC data text relative 
Andrew Sadek <andrew.sadek.se@gmail.com>

A new implemented feature in GCC Microblaze that allows Position
Independent Code to run using Data Text Relative addressing instead
of using Global Offset Table.

Its aim was to make 'PIC' more efficient and flexible as elf size
excess performance overhead were noticed when using GOT due to the
indirect addressing.

include/ChangeLog:
	* bfdlink.h (Add flag): Add new flag @ 'bfd_link_info' struct.
	* elf/microblaze.h (Add 3 new relocations):
	R_MICROBLAZE_TEXTPCREL_64, R_MICROBLAZE_TEXTREL_64
	and R_MICROBLAZE_TEXTREL_32_LO for relax function.
bfd/ChangeLog:
	* bfd/reloc.c (2 new BFD relocations):
	BFD_RELOC_MICROBLAZE_64_TEXTPCREL &
	BFD_RELOC_MICROBLAZE_64_TEXTPCREL
	* bfd/bfd-in2.h: Regenerate
	* bfd/libbfd.h: Regenerate
	* bfd/elf32-microblaze.c (Handle new relocs): define 'HOWTO' of 3
	new relocs and handle them in both relocate and relax functions.
	(microblaze_elf_reloc_type_lookup): add mapping between for new
	bfd relocs.
	(microblaze_elf_relocate_section): Handle new relocs in case of
	elf relocation.
	(microblaze_elf_relax_section): Handle new relocs for elf relaxation.
gas/ChangeLog:
	* gas/config/tc-microblaze.c (Handle new relocs directives in
	assembler): Handle new relocs from compiler output.
	(imm_types): add new imm types for data text relative addressing
	TEXT_OFFSET, TEXT_PC_OFFSET
	(md_convert_frag): conversion for BFD_RELOC_MICROBLAZE_64_TEXTPCREL,
	BFD_RELOC_MICROBLAZE_64_TEXTPCREL
	(md_apply_fix): apply fix for BFD_RELOC_MICROBLAZE_64_TEXTPCREL,
	BFD_RELOC_MICROBLAZE_64_TEXTPCREL
	(md_estimate_size_before_relax): estimate size for
	BFD_RELOC_MICROBLAZE_64_TEXTPCREL,
	BFD_RELOC_MICROBLAZE_64_TEXTPCREL
	(tc_gen_reloc): generate relocations for
	BFD_RELOC_MICROBLAZE_64_TEXTPCREL,
	BFD_RELOC_MICROBLAZE_64_TEXTPCREL
ld/ChangeLog:
	* ld/lexsup.c (Add 2 ld options):
	(ld_options): add disable-multiple-abs-defs @ 'ld_options' array
	(parse_args): parse new option and pass flag to 'link_info' struct.
	* ld/ldlex.h (Add enum): add new enum @ 'option_values' enum.
	* ld/ld.texinfo (Add new option): Add description for
	'disable-multiple-abs-defs'
	* ld/main.c: Initialize flags with false @ 'main'. Handle
	disable-multiple-abs-defs @ 'mutiple_definition'.
 2018-04-17 14:47:13 -07:00
Alan Modra
f954747f10 Reinstate readelf decoding of i860, i960 and i370 relocs 
include/
	* elf/i370.h: Revert removal.
	* elf/i860.h: Likewise.
	* elf/i960.h: Likewise.
binutils
	* readelf.c: Revert 2018-04-16 and 2018-04-11 changes.
 2018-04-17 10:48:58 +09:30
Alan Modra
5452f388a5 sparc-coff removal leftover 
* coff/sparc.h: Delete.
 2018-04-16 20:27:22 +09:30
Alan Modra
dc12032bca Remove m68k-aout and m68k-coff support 
include/
	* aout/host.h: Remove m68k-aout and m68k-coff support.
	* aout/hp300hpux.h: Delete.
	* coff/apollo.h: Delete.
	* coff/aux-coff.h: Delete.
	* coff/m68k.h: Delete.
bfd/
	* Makefile.am: Remove m68k-aout and m68k-coff support.
	* aoutf1.h: Likewise.
	* aoutx.h: Likewise.
	* archive.c: Likewise.
	* bfd-in.h: Likewise.
	* bfd.c: Likewise.
	* coffcode.h: Likewise.
	* coffswap.h: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* configure.host: Likewise.
	* doc/bfd.texinfo: Likewise.
	* doc/bfdint.texi: Likewise.
	* freebsd.h: Likewise.
	* gen-aout.c: Likewise.
	* hpux-core.c: Likewise.
	* libaout.h: Likewise.
	* libbfd-in.h: Likewise.
	* pdp11.c: Likewise.
	* peicode.h: Likewise.
	* riscix.c: Likewise.
	* targets.c: Likewise.
	* aout0.c: Delete.
	* coff-apollo.c: Delete.
	* coff-aux.c: Delete.
	* coff-m68k.c: Delete.
	* coff-svm68k.c: Delete.
	* coff-u68k.c: Delete.
	* hosts/delta68.h: Delete.
	* hosts/hp300bsd.h: Delete.
	* hosts/m68kaux.h: Delete.
	* hosts/news.h: Delete.
	* hp300bsd.c: Delete.
	* hp300hpux.c: Delete.
	* liboasys.h: Delete.
	* m68k4knetbsd.c: Delete.
	* m68klinux.c: Delete.
	* m68knetbsd.c: Delete.
	* oasys.c: Delete.
	* versados.c: Delete.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* libbfd.h: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
binutils/
	* testsuite/binutils-all/copy-2.d: Remove m68k-aout and m68k-coff
	support.
	* testsuite/binutils-all/copy-3.d: Likewise.
	* testsuite/binutils-all/objcopy.exp: Likewise.
	* testsuite/lib/binutils-common.exp: Likewise.
gas/
	* Makefile.am: Remove m68k-aout and m68k-coff support.
	* config/tc-m68k.c: Likewise.
	* config/tc-m68k.h: Likewise.
	* configure.ac: Likewise.
	* configure.tgt: Likewise.
	* testsuite/gas/all/weakref1u.d: Likewise.
	* testsuite/gas/m68k/all.exp: Likewise.
	* testsuite/gas/m68k/br-isaa.d: Likewise.
	* testsuite/gas/m68k/br-isab.d: Likewise.
	* testsuite/gas/m68k/br-isac.d: Likewise.
	* config/te-psos.h: Delete.
	* config/te-sun3.h: Delete.
	* testsuite/gas/m68k-coff/gas.exp: Delete.
	* testsuite/gas/m68k-coff/p2389.s: Delete.
	* testsuite/gas/m68k-coff/p2389a.s: Delete.
	* testsuite/gas/m68k-coff/p2430.s: Delete.
	* testsuite/gas/m68k-coff/p2430a.s: Delete.
	* testsuite/gas/m68k-coff/t1.s: Delete.
	* testsuite/gas/m68k/p3041.d: Delete.
	* testsuite/gas/m68k/p3041.s: Delete.
	* testsuite/gas/m68k/p3041data.d: Delete.
	* testsuite/gas/m68k/p3041data.s: Delete.
	* testsuite/gas/m68k/p3041pcrel.d: Delete.
	* testsuite/gas/m68k/p3041pcrel.s: Delete.
	* testsuite/gas/m68k/t2.d: Delete.
	* Makefile.in: Regenerate.
	* config.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
ld/
	* Makefile.am: Remove m68k-aout and m68k-coff support.
	* configure.tgt: Likewise.
	* emultempl/m68kelf.em: Likewise.
	* ld.texinfo: Likewise.
	* mri.c: Likewise.
	* emulparams/delta68.sh: Delete.
	* emulparams/hp300bsd.sh: Delete.
	* emulparams/hp3hpux.sh: Delete.
	* emulparams/m68k4knbsd.sh: Delete.
	* emulparams/m68kaout.sh: Delete.
	* emulparams/m68kaux.sh: Delete.
	* emulparams/m68kcoff.sh: Delete.
	* emulparams/m68klinux.sh: Delete.
	* emulparams/m68knbsd.sh: Delete.
	* emulparams/m68kpsos.sh: Delete.
	* emulparams/sun3.sh: Delete.
	* emultempl/m68kcoff.em: Delete.
	* scripttempl/delta68.sc: Delete.
	* scripttempl/m68kaux.sc: Delete.
	* scripttempl/m68kcoff.sc: Delete.
	* scripttempl/psos.sc: Delete.
	* testsuite/ld-versados/t1-1.ro: Delete.
	* testsuite/ld-versados/t1-2.ro: Delete.
	* testsuite/ld-versados/t1.ld: Delete.
	* testsuite/ld-versados/t1.ook: Delete.
	* testsuite/ld-versados/t2-1.ro: Delete.
	* testsuite/ld-versados/t2-2.ro: Delete.
	* testsuite/ld-versados/t2-3.ro: Delete.
	* testsuite/ld-versados/t2.ld: Delete.
	* testsuite/ld-versados/t2.ook: Delete.
	* testsuite/ld-versados/versados.exp: Delete.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
 2018-04-16 15:31:36 +09:30
Alan Modra
211dc24b87 Remove sh5 and sh64 support 
include/
	* dis-asm.h: Remove sh5 and sh64 support.
bfd/
	* Makefile.am: Remove sh5 and sh64 support.
	* archures.c: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* cpu-sh.c: Likewise.
	* elf32-sh-relocs.h: Likewise.
	* elf32-sh.c: Likewise.
	* targets.c: Likewise.
	* elf32-sh64-com.c: Delete.
	* elf32-sh64.c: Delete.
	* elf32-sh64.h: Delete.
	* elf64-sh64.c: Delete.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
opcodes/
	* Makefile.am: Remove sh5 and sh64 support.
	* configure.ac: Likewise.
	* disassemble.c: Likewise.
	* disassemble.h: Likewise.
	* sh-dis.c: Likewise.
	* sh64-dis.c: Delete.
	* sh64-opc.c: Delete.
	* sh64-opc.h: Delete.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
bintuils/
	* testsuite/binutils-all/objcopy.exp: Remove sh5 and sh64 support.
gas/
	* Makefile.am: Remove sh5 and sh64 support.
	* config/tc-sh.c: Likewise.
	* configure.tgt: Likewise.
	* doc/Makefile.am: Likewise.
	* doc/as.texinfo: Likewise.
	* testsuite/gas/cfi/cfi.exp: Likewise.
	* testsuite/gas/sh/basic.exp: Likewise.
	* config/tc-sh64.c: Delete.
	* config/tc-sh64.h: Delete.
	* doc/c-sh64.texi: Delete.
	* testsuite/gas/sh/sh64/abi-32.d: Delete.
	* testsuite/gas/sh/sh64/abi-32.s: Delete.
	* testsuite/gas/sh/sh64/abi-64.d: Delete.
	* testsuite/gas/sh/sh64/abi-64.s: Delete.
	* testsuite/gas/sh/sh64/basic-1.d: Delete.
	* testsuite/gas/sh/sh64/basic-1.s: Delete.
	* testsuite/gas/sh/sh64/case-1.d: Delete.
	* testsuite/gas/sh/sh64/case-1.s: Delete.
	* testsuite/gas/sh/sh64/case-noexp-1.d: Delete.
	* testsuite/gas/sh/sh64/crange1-1.d: Delete.
	* testsuite/gas/sh/sh64/crange1-2.d: Delete.
	* testsuite/gas/sh/sh64/crange1.s: Delete.
	* testsuite/gas/sh/sh64/crange2-1.d: Delete.
	* testsuite/gas/sh/sh64/crange2-2.d: Delete.
	* testsuite/gas/sh/sh64/crange2-noexp-1.d: Delete.
	* testsuite/gas/sh/sh64/crange2.s: Delete.
	* testsuite/gas/sh/sh64/crange3-1.d: Delete.
	* testsuite/gas/sh/sh64/crange3.s: Delete.
	* testsuite/gas/sh/sh64/crange4-1.d: Delete.
	* testsuite/gas/sh/sh64/crange4.s: Delete.
	* testsuite/gas/sh/sh64/crange5-1.d: Delete.
	* testsuite/gas/sh/sh64/crange5.s: Delete.
	* testsuite/gas/sh/sh64/creg-1.d: Delete.
	* testsuite/gas/sh/sh64/creg-1.s: Delete.
	* testsuite/gas/sh/sh64/creg-2.d: Delete.
	* testsuite/gas/sh/sh64/creg-2.s: Delete.
	* testsuite/gas/sh/sh64/datal-1.s: Delete.
	* testsuite/gas/sh/sh64/datal-2.d: Delete.
	* testsuite/gas/sh/sh64/datal-2.s: Delete.
	* testsuite/gas/sh/sh64/datal-3.s: Delete.
	* testsuite/gas/sh/sh64/datal32-1.d: Delete.
	* testsuite/gas/sh/sh64/datal32-3.d: Delete.
	* testsuite/gas/sh/sh64/datal64-1.d: Delete.
	* testsuite/gas/sh/sh64/datal64-3.d: Delete.
	* testsuite/gas/sh/sh64/eh-1.d: Delete.
	* testsuite/gas/sh/sh64/eh-1.s: Delete.
	* testsuite/gas/sh/sh64/endian-1.d: Delete.
	* testsuite/gas/sh/sh64/endian-1.s: Delete.
	* testsuite/gas/sh/sh64/endian-2.d: Delete.
	* testsuite/gas/sh/sh64/endian-2.s: Delete.
	* testsuite/gas/sh/sh64/err-1.s: Delete.
	* testsuite/gas/sh/sh64/err-2.s: Delete.
	* testsuite/gas/sh/sh64/err-3.s: Delete.
	* testsuite/gas/sh/sh64/err-4.s: Delete.
	* testsuite/gas/sh/sh64/err-abi-32.s: Delete.
	* testsuite/gas/sh/sh64/err-abi-64.s: Delete.
	* testsuite/gas/sh/sh64/err-dsp.s: Delete.
	* testsuite/gas/sh/sh64/err-movi-noexp-1.s: Delete.
	* testsuite/gas/sh/sh64/err-noexp-cmd1.s: Delete.
	* testsuite/gas/sh/sh64/err-pt-1.s: Delete.
	* testsuite/gas/sh/sh64/err-pt32-cmd1.s: Delete.
	* testsuite/gas/sh/sh64/err-pt32-cmd2.s: Delete.
	* testsuite/gas/sh/sh64/err-pt32-cmd3.s: Delete.
	* testsuite/gas/sh/sh64/err-ptb-1.s: Delete.
	* testsuite/gas/sh/sh64/err-ptb-2.s: Delete.
	* testsuite/gas/sh/sh64/err.exp: Delete.
	* testsuite/gas/sh/sh64/immexpr1.s: Delete.
	* testsuite/gas/sh/sh64/immexpr2.s: Delete.
	* testsuite/gas/sh/sh64/immexpr32-1.d: Delete.
	* testsuite/gas/sh/sh64/immexpr32-2.d: Delete.
	* testsuite/gas/sh/sh64/immexpr64-1.d: Delete.
	* testsuite/gas/sh/sh64/immexpr64-2.d: Delete.
	* testsuite/gas/sh/sh64/lineno.d: Delete.
	* testsuite/gas/sh/sh64/lineno.s: Delete.
	* testsuite/gas/sh/sh64/localcom-1.d: Delete.
	* testsuite/gas/sh/sh64/localcom-1.s: Delete.
	* testsuite/gas/sh/sh64/mix-1.d: Delete.
	* testsuite/gas/sh/sh64/mix-1.s: Delete.
	* testsuite/gas/sh/sh64/mix-noexp-1.d: Delete.
	* testsuite/gas/sh/sh64/movi-1.s: Delete.
	* testsuite/gas/sh/sh64/movi-2.s: Delete.
	* testsuite/gas/sh/sh64/movi-3.d: Delete.
	* testsuite/gas/sh/sh64/movi-3.s: Delete.
	* testsuite/gas/sh/sh64/movi32-1.d: Delete.
	* testsuite/gas/sh/sh64/movi32-2.d: Delete.
	* testsuite/gas/sh/sh64/movi32-noexp-2.d: Delete.
	* testsuite/gas/sh/sh64/movi64-1.d: Delete.
	* testsuite/gas/sh/sh64/movi64-2.d: Delete.
	* testsuite/gas/sh/sh64/movi64-2.s: Delete.
	* testsuite/gas/sh/sh64/movi64-3.d: Delete.
	* testsuite/gas/sh/sh64/movi64-noexp-2.d: Delete.
	* testsuite/gas/sh/sh64/pt-1.d: Delete.
	* testsuite/gas/sh/sh64/pt-1.s: Delete.
	* testsuite/gas/sh/sh64/pt-2.s: Delete.
	* testsuite/gas/sh/sh64/pt-noexp-1.d: Delete.
	* testsuite/gas/sh/sh64/pt32-1.d: Delete.
	* testsuite/gas/sh/sh64/pt32-noexp-2.d: Delete.
	* testsuite/gas/sh/sh64/pt64-1.d: Delete.
	* testsuite/gas/sh/sh64/pt64-32-1.d: Delete.
	* testsuite/gas/sh/sh64/pt64-32-2.d: Delete.
	* testsuite/gas/sh/sh64/pt64-noexp-2.d: Delete.
	* testsuite/gas/sh/sh64/ptc-1.s: Delete.
	* testsuite/gas/sh/sh64/ptc32-1.d: Delete.
	* testsuite/gas/sh/sh64/ptc32-noexp-1.d: Delete.
	* testsuite/gas/sh/sh64/ptc64-1.d: Delete.
	* testsuite/gas/sh/sh64/ptc64-32-1.d: Delete.
	* testsuite/gas/sh/sh64/ptc64-noexp-1.d: Delete.
	* testsuite/gas/sh/sh64/ptext-1.s: Delete.
	* testsuite/gas/sh/sh64/ptext32-1.d: Delete.
	* testsuite/gas/sh/sh64/ptext32-noexp-1.d: Delete.
	* testsuite/gas/sh/sh64/ptext64-1.d: Delete.
	* testsuite/gas/sh/sh64/ptext64-32-1.d: Delete.
	* testsuite/gas/sh/sh64/ptext64-noexp-1.d: Delete.
	* testsuite/gas/sh/sh64/rel-1.s: Delete.
	* testsuite/gas/sh/sh64/rel-2.s: Delete.
	* testsuite/gas/sh/sh64/rel-3.s: Delete.
	* testsuite/gas/sh/sh64/rel-4.s: Delete.
	* testsuite/gas/sh/sh64/rel-5.s: Delete.
	* testsuite/gas/sh/sh64/rel32-1.d: Delete.
	* testsuite/gas/sh/sh64/rel32-2.d: Delete.
	* testsuite/gas/sh/sh64/rel32-3.d: Delete.
	* testsuite/gas/sh/sh64/rel32-4.d: Delete.
	* testsuite/gas/sh/sh64/rel32-5.d: Delete.
	* testsuite/gas/sh/sh64/rel64-1.d: Delete.
	* testsuite/gas/sh/sh64/rel64-2.d: Delete.
	* testsuite/gas/sh/sh64/rel64-3.d: Delete.
	* testsuite/gas/sh/sh64/rel64-4.d: Delete.
	* testsuite/gas/sh/sh64/rel64-5.d: Delete.
	* testsuite/gas/sh/sh64/relax-1.d: Delete.
	* testsuite/gas/sh/sh64/relax-1.s: Delete.
	* testsuite/gas/sh/sh64/relax-2.d: Delete.
	* testsuite/gas/sh/sh64/relax-2.s: Delete.
	* testsuite/gas/sh/sh64/relax-3.d: Delete.
	* testsuite/gas/sh/sh64/relax-3.s: Delete.
	* testsuite/gas/sh/sh64/sh64.exp: Delete.
	* testsuite/gas/sh/sh64/shift-1.s: Delete.
	* testsuite/gas/sh/sh64/shift-2.s: Delete.
	* testsuite/gas/sh/sh64/shift-3.s: Delete.
	* testsuite/gas/sh/sh64/shift32-1.d: Delete.
	* testsuite/gas/sh/sh64/shift32-3.d: Delete.
	* testsuite/gas/sh/sh64/shift32-noexp-3.d: Delete.
	* testsuite/gas/sh/sh64/shift64-1.d: Delete.
	* testsuite/gas/sh/sh64/shift64-2.d: Delete.
	* testsuite/gas/sh/sh64/shift64-3.d: Delete.
	* testsuite/gas/sh/sh64/shift64-noexp-3.d: Delete.
	* testsuite/gas/sh/sh64/syntax-1.d: Delete.
	* testsuite/gas/sh/sh64/syntax-1.s: Delete.
	* testsuite/gas/sh/sh64/syntax-2.d: Delete.
	* testsuite/gas/sh/sh64/syntax-2.s: Delete.
	* testsuite/gas/sh/sh64/ua-1.s: Delete.
	* testsuite/gas/sh/sh64/ua32-1.d: Delete.
	* testsuite/gas/sh/sh64/ua64-1.d: Delete.
	* Makefile.in: Regenerate.
	* doc/Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
ld/
	* Makefile.am: Remove sh5 and sh64 support.
	* configure.tgt: Likewise.
	* ldlang.c: Likewise.
	* testsuite/ld-elfcomm/elfcomm.exp: Likewise.
	* testsuite/ld-gc/gc.exp: Likewise.
	* testsuite/ld-gc/pr13683.d: Likewise.
	* testsuite/ld-scripts/crossref.exp: Likewise.
	* testsuite/ld-selective/selective.exp: Likewise.
	* testsuite/ld-sh/ld-r-1.d: Likewise.
	* testsuite/ld-sh/rd-sh.exp: Likewise.
	* testsuite/ld-sh/sh.exp: Likewise.
	* testsuite/ld-srec/srec.exp: Likewise.
	* testsuite/ld-undefined/undefined.exp: Likewise.
	* emulparams/shelf32.sh: Delete.
	* emulparams/shelf32_linux.sh: Delete.
	* emulparams/shelf32_nbsd.sh: Delete.
	* emulparams/shelf64.sh: Delete.
	* emulparams/shelf64_nbsd.sh: Delete.
	* emulparams/shlelf32.sh: Delete.
	* emulparams/shlelf32_linux.sh: Delete.
	* emulparams/shlelf32_nbsd.sh: Delete.
	* emulparams/shlelf64.sh: Delete.
	* emulparams/shlelf64_nbsd.sh: Delete.
	* emultempl/sh64elf.em: Delete.
	* testsuite/ld-sh/sh64/abi32.sd: Delete.
	* testsuite/ld-sh/sh64/abi32.xd: Delete.
	* testsuite/ld-sh/sh64/abi64.sd: Delete.
	* testsuite/ld-sh/sh64/abi64.xd: Delete.
	* testsuite/ld-sh/sh64/abixx-noexp.sd: Delete.
	* testsuite/ld-sh/sh64/cmpct1.sd: Delete.
	* testsuite/ld-sh/sh64/cmpct1.xd: Delete.
	* testsuite/ld-sh/sh64/crange-1.s: Delete.
	* testsuite/ld-sh/sh64/crange-2a.s: Delete.
	* testsuite/ld-sh/sh64/crange-2b.s: Delete.
	* testsuite/ld-sh/sh64/crange-2c.s: Delete.
	* testsuite/ld-sh/sh64/crange-2d.s: Delete.
	* testsuite/ld-sh/sh64/crange-2e.s: Delete.
	* testsuite/ld-sh/sh64/crange-2f.s: Delete.
	* testsuite/ld-sh/sh64/crange-2g.s: Delete.
	* testsuite/ld-sh/sh64/crange-2h.s: Delete.
	* testsuite/ld-sh/sh64/crange-2i.s: Delete.
	* testsuite/ld-sh/sh64/crange1.rd: Delete.
	* testsuite/ld-sh/sh64/crange2.rd: Delete.
	* testsuite/ld-sh/sh64/crange3-cmpct.rd: Delete.
	* testsuite/ld-sh/sh64/crange3-media.rd: Delete.
	* testsuite/ld-sh/sh64/crange3.dd: Delete.
	* testsuite/ld-sh/sh64/crange3.rd: Delete.
	* testsuite/ld-sh/sh64/crangerel1.rd: Delete.
	* testsuite/ld-sh/sh64/crangerel2.rd: Delete.
	* testsuite/ld-sh/sh64/dlsection-1.s: Delete.
	* testsuite/ld-sh/sh64/dlsection.sd: Delete.
	* testsuite/ld-sh/sh64/endian.dbd: Delete.
	* testsuite/ld-sh/sh64/endian.dld: Delete.
	* testsuite/ld-sh/sh64/endian.ld: Delete.
	* testsuite/ld-sh/sh64/endian.s: Delete.
	* testsuite/ld-sh/sh64/endian.sbd: Delete.
	* testsuite/ld-sh/sh64/endian.sld: Delete.
	* testsuite/ld-sh/sh64/gotplt.d: Delete.
	* testsuite/ld-sh/sh64/gotplt.map: Delete.
	* testsuite/ld-sh/sh64/gotplt.s: Delete.
	* testsuite/ld-sh/sh64/init-cmpct.d: Delete.
	* testsuite/ld-sh/sh64/init-media.d: Delete.
	* testsuite/ld-sh/sh64/init.s: Delete.
	* testsuite/ld-sh/sh64/init64.d: Delete.
	* testsuite/ld-sh/sh64/mix1-noexp.sd: Delete.
	* testsuite/ld-sh/sh64/mix1.sd: Delete.
	* testsuite/ld-sh/sh64/mix1.xd: Delete.
	* testsuite/ld-sh/sh64/mix2-noexp.sd: Delete.
	* testsuite/ld-sh/sh64/mix2.sd: Delete.
	* testsuite/ld-sh/sh64/mix2.xd: Delete.
	* testsuite/ld-sh/sh64/rd-sh64.exp: Delete.
	* testsuite/ld-sh/sh64/rel-1.s: Delete.
	* testsuite/ld-sh/sh64/rel-2.s: Delete.
	* testsuite/ld-sh/sh64/rel32.xd: Delete.
	* testsuite/ld-sh/sh64/rel64.xd: Delete.
	* testsuite/ld-sh/sh64/relax.exp: Delete.
	* testsuite/ld-sh/sh64/relax1.s: Delete.
	* testsuite/ld-sh/sh64/relax2.s: Delete.
	* testsuite/ld-sh/sh64/relax3.s: Delete.
	* testsuite/ld-sh/sh64/relax4.s: Delete.
	* testsuite/ld-sh/sh64/reldl-1.s: Delete.
	* testsuite/ld-sh/sh64/reldl-2.s: Delete.
	* testsuite/ld-sh/sh64/reldl32.rd: Delete.
	* testsuite/ld-sh/sh64/reldl64.rd: Delete.
	* testsuite/ld-sh/sh64/relfail.exp: Delete.
	* testsuite/ld-sh/sh64/relfail.s: Delete.
	* testsuite/ld-sh/sh64/sh64-1.s: Delete.
	* testsuite/ld-sh/sh64/sh64-2.s: Delete.
	* testsuite/ld-sh/sh64/sh64.exp: Delete.
	* testsuite/ld-sh/sh64/shcmp-1.s: Delete.
	* testsuite/ld-sh/sh64/shdl-1.s: Delete.
	* testsuite/ld-sh/sh64/shdl-2.s: Delete.
	* testsuite/ld-sh/sh64/shdl32.xd: Delete.
	* testsuite/ld-sh/sh64/shdl64.sd: Delete.
	* testsuite/ld-sh/sh64/shdl64.xd: Delete.
	* testsuite/ld-sh/sh64/shmix-1.s: Delete.
	* testsuite/ld-sh/sh64/shmix-2.s: Delete.
	* testsuite/ld-sh/sh64/shmix-3.s: Delete.
	* testsuite/ld-sh/sh64/stobin-0-dso.d: Delete.
	* testsuite/ld-sh/sh64/stobin-1.d: Delete.
	* testsuite/ld-sh/sh64/stobin.s: Delete.
	* testsuite/ld-sh/sh64/stolib.s: Delete.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
 2018-04-16 15:29:39 +09:30
Alan Modra
a9a4b30244 Remove w65 support 
include/
	* coff/internal.h: Remove w65 support.
	* coff/w65.h: Delete.
bfd/
	* Makefile.am: Remove w65 support.
	* archures.c: Likewise.
	* coffcode.h: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* coff-w65.c: Delete.
	* cpu-w65.c: Delete.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
opcodes/
	* Makefile.am: Remove w65 support.
	* configure.ac: Likewise.
	* disassemble.c: Likewise.
	* disassemble.h: Likewise.
	* w65-dis.c: Delete.
	* w65-opc.h: Delete.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
binutils/
	* testsuite/binutils-all/objcopy.exp: Remove w65 support.
ld/
	* Makefile.am: Remove w65 support.
	* configure.tgt: Likewise.
	* emulparams/w65.sh: Delete.
	* scripttempl/w65.sc: Delete.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
 2018-04-16 15:26:05 +09:30
Alan Modra
04cb01fd5a Remove we32k support 
include/
	* coff/we32k.h: Delete.
bfd/
	* Makefile.am: Remove we32k support.
	* archures.c: Likewise.
	* coffcode.h: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* coff-we32k.c: Delete.
	* cpu-we32k.c: Delete.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
opcodes/
	* configure.ac: Remove we32k support.
	* configure: Regenerate.
bintuils/
	* testsuite/binutils-all/objdump.exp: Remove we32k support.
 2018-04-16 15:24:43 +09:30
Alan Modra
c2bf1eecf9 Remove m88k support 
include/
	* coff/internal.h: Remove m88k support.
	* coff/m88k.h: Delete.
	* opcode/m88k.h: Delete.
bfd/
	* Makefile.am: Remove m88k support.
	* aoutx.h: Likewise.
	* archures.c: Likewise.
	* coffcode.h: Likewise.
	* coffswap.h: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* cpu-ns32k.c: Likewise.
	* elf32-nds32.c: Likewise.
	* mach-o.c: Likewise.
	* netbsd-core.c: Likewise.
	* reloc.c: Likewise.
	* targets.c: Likewise.
	* coff-m88k.c: Delete.
	* cpu-m88k.c: Delete.
	* elf32-m88k.c: Delete.
	* hosts/m88kmach3.h: Delete.
	* m88kmach3.c: Delete.
	* m88kopenbsd.c: Delete.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
opcodes/
	* Makefile.am: Remove m88k support.
	* configure.ac: Likewise.
	* disassemble.c: Likewise.
	* disassemble.h: Likewise.
	* m88k-dis.c: Delete.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
binutils/
	* MAINTAINERS (Mark Kettenis): Move to past maintainers.
	* testsuite/binutils-all/objdump.exp: Remove m88k support.
gas/
	* configure.ac: Remove m88k support.
	* config.in: Regenerate.
	* configure: Regenerate.
ld/
	* Makefile.am: Remove m88k support.
	* configure.host: Likewise.
	* configure.tgt: Likewise.
	* testsuite/ld-elf/sec-to-seg.exp: Likewise.
	* emulparams/m88kbcs.sh: Delete.
	* scripttempl/m88kbcs.sc: Delete.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
 2018-04-16 15:23:38 +09:30