Mike Frysinger
5f05936d9b
sim: v850: cleanup build warnings
...
This port only had one minor warning left in it, so fix it and then
enable -Werror behavior by deleting the macro call. We'll use the
common default now (which is -Werror).
2021-01-31 15:19:16 -05:00
Mike Frysinger
44b30b7f0e
sim: v850: fix handling of SYS_times
...
My recent rewrite of the nltvals generator fixed a bug where SYS_times
was not being exported for v850. But that in turn uncovered this bug
where the SYS_times codepath had a compile error.
2021-01-31 15:15:33 -05:00
Mike Frysinger
68ed285428
sim: clean up C11 header includes
...
Since we require C11 now, we can assume many headers exist, and
clean up all of the conditional includes. It's not like any of
this code actually accounted for the headers not existing, just
whether we could include them.
The strings.h cleanup is a little nuanced: it isn't in C11, but
every use of it in the codebase will include strings.h only if
string.h doesn't exist. Since we now assume the C11 string.h
exists, we'll never include strings.h, so we can delete it.
2021-01-11 08:05:54 -05:00
Dominik Vogt
1d19cae752
Fix invalid left shift of negative value
...
Fix occurrences of left-shifting negative constants in C code.
sim/arm/ChangeLog:
* thumbemu.c (handle_T2_insn): Fix left shift of negative value.
* armemu.c (handle_v6_insn): Likewise.
sim/avr/ChangeLog:
* interp.c (sign_ext): Fix left shift of negative value.
sim/mips/ChangeLog:
* micromips.igen (process_isa_mode): Fix left shift of negative
value.
sim/msp430/ChangeLog:
* msp430-sim.c (get_op, put_op): Fix left shift of negative value.
sim/v850/ChangeLog:
* simops.c (v850_bins): Fix left shift of negative value.
2015-12-15 14:09:14 +01:00
Nick Clifton
a3976a7c56
Fixes problems building the V850 simulator introduced with the previous delta.
...
* sim-main.h (reg64_t): New type.
(v850_regs): Add selID_sregs field.
(VR, SAT16, SAT32, ABS16, ABS32 ): New macros.
* v850-dc: Add fields for v850e3v5 instructions.
* v850.igen (cvtf.dl): Use correctly signed local value.
(cvtf.dw, cvtf.sw, trncf.dul, trncf.dl, trncf.sul, trncf.sw):
Likewise.
* interp.c: Fix old style function declarations.
* simops.c: Likewise.
2015-02-27 09:53:03 +00:00
Nick Clifton
67d7515b0a
* simops.c (v850_rotl): New function.
...
(v850_bins): New function.
* simops.h: Add prototypes fir v850_rotl and v850_bins.
* v850-dc: Add entries for V850e3v5.
* v850.igen: Add support for v850e3v5.
(ld.dw, st.dw, rotl, bins): New patterns.
2013-01-28 10:06:51 +00:00
Kevin Buettner
2aaed97917
Commit gdb and sim support for v850e2 and v850e2v3 on behalf of
...
Rathish C <Rathish.C@kpitcummins.com>.
2012-03-29 00:57:19 +00:00
Kevin Buettner
d0f0baa272
* simops (OP_10007E0): Update errno handling as most traps
...
do not invoke the host's functionality directly. Invoke
sim_io_stat() instead of stat() for implementing TARGET_SYS_stat.
Implement TARGET_SYS_fstat, TARGET_SYS_rename, and TARGET_SYS_unlink.
2011-03-21 22:05:56 +00:00
Mike Frysinger
d79fe0d643
sim: punt zfree()
...
The sim keeps track of which allocations are zero-ed internally (via
zalloc) and then calls a helper "zfree" function rather than "free".
But this "zfree" function simply calls "free" itself. Since I can
see no point in this and it is simply useless overhead, punt it.
The only real change is in hw-alloc.c where we remove the zalloc_p
tracking, and sim-utils.c where zfree is delete. The rest of the
changes are a simple `sed` from "zfree" to "free".
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-14 05:14:28 +00:00
DJ Delorie
98e460c30d
* simops.c (OP_1C007E0): Compensate for 64 bit hosts.
...
(OP_18007E0): Likewise.
(OP_2C007E0): Likewise.
(OP_28007E0): Likewise.
* v850.igen (divh): Likewise.
2008-02-06 04:41:26 +00:00
DJ Delorie
c5fbc25baf
Index: ChangeLog
...
* configure.ac (v850): V850 now has a testsuite.
* configure (v850): Likewise.
Index: testsuite/ChangeLog
* sim/v850/: New directory.
* sim/v850/allinsns.exp: New.
* sim/v850/bsh.cgs: New.
* sim/v850/div.cgs: New.
* sim/v850/divh.cgs: New.
* sim/v850/divh_3.cgs: New.
* sim/v850/divhu.cgs: New.
* sim/v850/divu.cgs: New.
* sim/v850/sar.cgs: New.
* sim/v850/satadd.cgs: New.
* sim/v850/satsub.cgs: New.
* sim/v850/satsubi.cgs: New.
* sim/v850/satsubr.cgs: New.
* sim/v850/shl.cgs: New.
* sim/v850/shr.cgs: New.
* sim/v850/testutils.cgs: New.
* sim/v850/testutils.inc: New.
Index: v850/ChangeLog
* simops.c (OP_C0): Correct saturation logic.
(OP_220): Likewise.
(OP_A0): Likewise.
(OP_660): Likewise.
(OP_80): Likewise.
* simops.c (OP_2A0): If the shift count is zero, clear the
carry.
(OP_A007E0): Likewise.
(OP_2C0): Likewise.
(OP_C007E0): Likewise.
(OP_280): Likewise.
(OP_8007E0): Likewise.
* simops.c (OP_2C207E0): Correct PSW flags for special divu
conditions.
(OP_2C007E0): Likewise, for div.
(OP_28207E0): Likewise, for divhu.
(OP_28007E0): Likewise, for divh. Also, sign-extend the correct
operand.
* v850.igen (divh): Likewise, for 2-op divh.
* v850.igen (bsh): Fix carry logic.
2008-02-06 00:40:05 +00:00
Mark Kettenis
4389ce38f0
* simops.c: Include <sys/types.h>.
2004-01-18 14:56:40 +00:00
Nick Clifton
ebc115b7bb
* simops.c (OP_40): Delete. Move code to...
...
* v850-igen.c (): ...Here. Sign extend the first operand.
* simops.h (OP_40): Remove prototype.
2003-04-06 08:51:04 +00:00
Andrew Cagney
0da2b66558
2002-11-30 Andrew Cagney <cagney@redhat.com>
...
* simops.c: Use int, 1, 0 instead of boolean, true and false.
* sim-main.h: Ditto.
2002-11-30 18:01:30 +00:00
Jim Wilson
30458d39d6
Fix handling of v850e bit-twiddle instructions.
...
* simops.c (OP_E6077E0): And op1 with 7 after reading register, not
before.
(BIT_CHANGE_OP): Likewise.
2002-09-30 20:11:08 +00:00
Jim Wilson
2e8162cedb
Fix bug in support for trap instruction.
...
* simops (OP_10007E0): Don't subtract 4 from PC.
2002-09-27 18:59:08 +00:00
Nick Clifton
e551c2572e
Makefile.in: Add gen-zero-r0 option.
...
sim-main.h (GPR_SET, GPR_CLEAR): Define.
simops.c (OP_24007E0): Sign extend the imm9 operand of a mul instruction.
2002-08-29 16:59:20 +00:00
Andrew Cagney
d62274a397
* simops.c (trace_result): Fix printf formatting.
2002-06-17 21:49:05 +00:00
Stan Shebs
c906108c21
Initial creation of sourceware repository
1999-04-16 01:35:26 +00:00
Stan Shebs
071ea11e85
Initial creation of sourceware repository
1999-04-16 01:34:07 +00:00
Andrew Cagney
a276b6f057
Clean up tracing for Bcond & jmp insns.
...
Fix computation of disp16 and disp22.
Clean up tracing of sld* insns.
1997-09-19 06:39:21 +00:00
Andrew Cagney
bd4c35cc6d
Fix cmov immed.
1997-09-19 02:20:02 +00:00
Andrew Cagney
60fe0e06a8
Fix cmov insn.
1997-09-19 00:50:19 +00:00
Andrew Cagney
a72f8fb439
Clean up more tracing.
...
FIX interrupt delivery - was zapping PSW before it had been saved.
FIX interrupt return, was one instruction out.
1997-09-17 08:14:23 +00:00
Andrew Cagney
6aead89a5f
Fix tracing for: "ctret", "bsw", "hsw"
...
Fix bugs in: "bsh", "callt", "stsr".
1997-09-17 05:31:00 +00:00
Andrew Cagney
fb1fd47514
Smooth some of ALU tracing's rough edges.
...
Fix switch insn.
1997-09-16 14:00:15 +00:00
Andrew Cagney
3f33acd039
Use trace_one_insn in trace functions. Buffer up trace data so that
...
it is displayed in a single block.
1997-09-16 07:03:41 +00:00
Andrew Cagney
c7db488f71
Restrict ldsr (load system register) to modifying just non-reserved PSW bits.
...
For v850eq, include PSW[US] in bits that can be modified.
1997-09-16 04:49:24 +00:00
Jim Wilson
5262de2167
* simops.c (Multiply64): Don't store into register zero.
1997-09-16 01:45:23 +00:00
Andrew Cagney
bda6163995
Fix sanitization for v850 V v850e V v850eq
1997-09-15 14:42:51 +00:00
Andrew Cagney
658303f7d4
For v850eq start up with US bit set.
...
Let sim_analyze_program determine the architecture.
Fix various sanitizations.
1997-09-15 08:18:20 +00:00
Andrew Cagney
02508bb179
Have trace_input, trace_output use sim-trace for IO.
1997-09-10 05:40:04 +00:00
Andrew Cagney
5d37a07bc5
Add multi-sim support to v850/v850e/v850eq simulators.
1997-09-08 17:42:48 +00:00
Andrew Cagney
da3a66e5ca
Replace memory model with one from sim/common directory.
1997-09-04 10:10:02 +00:00
Andrew Cagney
b5e935ae85
Pacify gcc-current -Wall.
1997-09-03 07:30:17 +00:00
Andrew Cagney
9cdd2c6d72
Add real SIM_DESC arg to v850 simulator.
...
Add --enable-sim-warnings, use/fix errors.
Add --enable-sim-endian, don't use.
Add common modules. Don't yet use most.
1997-09-03 04:10:33 +00:00
Andrew Cagney
0ffba68fdc
Compile from UNIX to cygwin32.
1997-09-01 03:43:56 +00:00
Nick Clifton
6061622830
Updated with respect to the HDD-tool-0611 document.
1997-08-22 17:41:20 +00:00
Nick Clifton
64ad9cecb6
Added N step divide routines, courtesy of Sugimoto at NEC.
1997-08-20 22:42:55 +00:00
Nick Clifton
70caad98c1
Fixed interpretation of SR bit in list18 structures.
1997-08-20 20:57:05 +00:00
Andrew Cagney
87e43259f1
Cleanups to compile under FreeBSD
1997-04-17 06:05:19 +00:00
Michael Meissner
6ec96a0265
Deal with kill encoding the signal via the exit status.
1996-12-31 23:18:55 +00:00
Michael Meissner
ee3f2d4f6a
Allow exit to work normally under gdb
1996-12-27 19:50:03 +00:00
Gavin Romig-Koch
7fc45edb6c
Fix linux build problem.
1996-10-31 19:58:14 +00:00
Jeff Law
8824fb459b
* simops.c (OP_10007E0): Handle SYS_times and SYS_gettimeofday.
...
Check it into devo too.
1996-10-30 16:30:59 +00:00
Jeff Law
6803f89b14
* simops.c (OP_10007E0): Handle SYS_time.
...
Check into devo too.
1996-10-30 15:51:39 +00:00
Jeff Law
c500c07496
* simops.c: Include <sys/stat.h>.
...
(OP_10007E0): Handle SYS_stat.
For RW testing.
1996-10-29 21:24:01 +00:00
Jeff Law
f009978996
* simops.c (OP_500): Mask off low bit in displacement
...
for sld.w.
(OP_501): Similarly.
More bugs exposed by tda testing.
1996-10-24 21:19:22 +00:00
Jeff Law
85c09b0518
* simops.c (OP_500): Fix displacement handling for sld.w.
...
(OP_501): Similarly for sst.w.
More fixes exposed by tda testing.
1996-10-24 20:49:06 +00:00
Jeff Law
0a89af6efd
* simops.c (trace_input): Remove all references to SEXT7.
...
(OP_300, OP_400, OP_500, OP_380, OP_480, OP_501): Displacement
is zero extended for sst/sld instructions.
* v850_sim.h (SEX7): Delete. It's no longer needed (and it
was incorrect anyway).
So we properly simulate sst/sld instructions.
1996-10-24 18:28:43 +00:00