[ARM]: Modify assembler to accept floating and signless datatypes for MVE instruction VLDR.
This patch modifies assembler to accept the equivalent sized floating and signless datatypes for VLDR instruction but as alias for the unsigned version. gas/ChangeLog: 2019-09-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (do_mve_vstr_vldr_RQ): Modify function to allow float * and signless datatypes for few cases of VLDR instruction. * testsuite/gas/arm/mve-vldr-bad-3.l: Modify. * testsuite/gas/arm/mve-vldr-bad-3.s: Likewise. * testsuite/gas/arm/mve-vstrldr-1.d: Likewise. * testsuite/gas/arm/mve-vstrldr-1.s: Likewise.
This commit is contained in:
Srinath Parvathaneni
parent
5d33705c7b
commit
e449ea97eb
@ -17282,6 +17282,7 @@ static void
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do_mve_vstr_vldr_RQ (int size, int elsize, int load)
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{
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unsigned os = inst.operands[1].imm >> 5;
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unsigned type = inst.vectype.el[0].type;
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constraint (os != 0 && size == 8,
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_("can not shift offsets when accessing less than half-word"));
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constraint (os && os != neon_logbits (size),
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@ -17312,15 +17313,14 @@ do_mve_vstr_vldr_RQ (int size, int elsize, int load)
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constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
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_("destination register and offset register may not be"
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" the same"));
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constraint (size == elsize && inst.vectype.el[0].type != NT_unsigned,
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constraint (size == elsize && type == NT_signed, BAD_EL_TYPE);
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constraint (size != elsize && type != NT_unsigned && type != NT_signed,
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BAD_EL_TYPE);
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constraint (inst.vectype.el[0].type != NT_unsigned
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&& inst.vectype.el[0].type != NT_signed, BAD_EL_TYPE);
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inst.instruction |= (inst.vectype.el[0].type == NT_unsigned) << 28;
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inst.instruction |= ((size == elsize) || (type == NT_unsigned)) << 28;
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}
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else
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{
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constraint (inst.vectype.el[0].type != NT_untyped, BAD_EL_TYPE);
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constraint (type != NT_untyped, BAD_EL_TYPE);
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}
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inst.instruction |= 1 << 23;
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@ -133,3 +133,37 @@
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[^:]*:134: Error: syntax error -- `vldrweq.32 q0,\[r0\]'
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[^:]*:135: Error: vector predicated instruction should be in VPT/VPST block -- `vldrwt.32 q0,\[r0\]'
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[^:]*:137: Error: instruction missing MVE vector predication code -- `vldrw.32 q0,\[r0\]'
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[^:]*:140: Error: bad element type for instruction -- `vldrb.16 q0,\[r2,q3\]'
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[^:]*:140: Error: bad element type for instruction -- `vldrb.32 q0,\[r2,q3\]'
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[^:]*:140: Error: bad element type for instruction -- `vldrb.64 q0,\[r2,q3\]'
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[^:]*:140: Error: bad element type for instruction -- `vldrb.f16 q0,\[r2,q3\]'
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[^:]*:140: Error: bad element type for instruction -- `vldrb.f32 q0,\[r2,q3\]'
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[^:]*:140: Error: bad element type for instruction -- `vldrb.f64 q0,\[r2,q3\]'
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[^:]*:140: Error: bad element type for instruction -- `vldrb.p16 q0,\[r2,q3\]'
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[^:]*:140: Error: bad element type for instruction -- `vldrb.p32 q0,\[r2,q3\]'
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[^:]*:140: Error: bad element type for instruction -- `vldrb.p64 q0,\[r2,q3\]'
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[^:]*:140: Error: bad element type for instruction -- `vldrb.s8 q0,\[r2,q3\]'
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[^:]*:143: Error: bad element type for instruction -- `vldrh.8 q0,\[r2,q3,uxtw#1\]'
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[^:]*:143: Error: bad element type for instruction -- `vldrh.32 q0,\[r2,q3,uxtw#1\]'
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[^:]*:143: Error: bad element type for instruction -- `vldrh.64 q0,\[r2,q3,uxtw#1\]'
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[^:]*:143: Error: bad element type for instruction -- `vldrh.f32 q0,\[r2,q3,uxtw#1\]'
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[^:]*:143: Error: bad element type for instruction -- `vldrh.f64 q0,\[r2,q3,uxtw#1\]'
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[^:]*:143: Error: bad element type for instruction -- `vldrh.p32 q0,\[r2,q3,uxtw#1\]'
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[^:]*:143: Error: bad element type for instruction -- `vldrh.p64 q0,\[r2,q3,uxtw#1\]'
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[^:]*:143: Error: bad element type for instruction -- `vldrh.s16 q0,\[r2,q3,uxtw#1\]'
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[^:]*:146: Error: bad element type for instruction -- `vldrw.8 q0,\[r2,q3,uxtw#2\]'
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[^:]*:146: Error: bad element type for instruction -- `vldrw.16 q0,\[r2,q3,uxtw#2\]'
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[^:]*:146: Error: bad element type for instruction -- `vldrw.64 q0,\[r2,q3,uxtw#2\]'
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[^:]*:146: Error: bad element type for instruction -- `vldrw.f16 q0,\[r2,q3,uxtw#2\]'
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[^:]*:146: Error: bad element type for instruction -- `vldrw.f64 q0,\[r2,q3,uxtw#2\]'
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[^:]*:146: Error: bad element type for instruction -- `vldrw.p16 q0,\[r2,q3,uxtw#2\]'
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[^:]*:146: Error: bad element type for instruction -- `vldrw.p64 q0,\[r2,q3,uxtw#2\]'
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[^:]*:146: Error: bad element type for instruction -- `vldrw.s32 q0,\[r2,q3,uxtw#2\]'
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[^:]*:149: Error: bad element type for instruction -- `vldrd.8 q0,\[r2,q3,uxtw#3\]'
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[^:]*:149: Error: bad element type for instruction -- `vldrd.16 q0,\[r2,q3,uxtw#3\]'
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[^:]*:149: Error: bad element type for instruction -- `vldrd.32 q0,\[r2,q3,uxtw#3\]'
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[^:]*:149: Error: bad element type for instruction -- `vldrd.f16 q0,\[r2,q3,uxtw#3\]'
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[^:]*:149: Error: bad element type for instruction -- `vldrd.f32 q0,\[r2,q3,uxtw#3\]'
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[^:]*:149: Error: bad element type for instruction -- `vldrd.p16 q0,\[r2,q3,uxtw#3\]'
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[^:]*:149: Error: bad element type for instruction -- `vldrd.p32 q0,\[r2,q3,uxtw#3\]'
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[^:]*:149: Error: bad element type for instruction -- `vldrd.s64 q0,\[r2,q3,uxtw#3\]'
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@ -135,4 +135,15 @@ vldrweq.32 q0, [r0]
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vldrwt.32 q0, [r0]
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vpst
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vldrw.32 q0, [r0]
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.irp op1, 16, 32, 64, f16, f32, f64, p16, p32, p64, s8
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vldrb.\op1 q0, [r2, q3]
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.endr
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.irp op1, 8, 32, 64, f32, f64, p32, p64, s16
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vldrh.\op1 q0, [r2, q3, uxtw #1]
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.endr
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.irp op1, 8, 16, 64, f16, f64, p16, p64, s32
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vldrw.\op1 q0, [r2, q3, uxtw #2]
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.endr
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.irp op1, 8, 16, 32, f16, f32, p16, p32, s64
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vldrd.\op1 q0, [r2, q3, uxtw #3]
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.endr
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@ -7561,3 +7561,20 @@ Disassembly of section .text:
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[^>]*> fe71 8f4d vpste
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[^>]*> fc93 6fdb vldrdt.u64 q3, \[r3, q5, uxtw #3\]
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[^>]*> fc97 efd9 vldrde.u64 q7, \[r7, q4, uxtw #3\]
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[^>]*> fc92 0e06 vldrb.u8 q0, \[r2, q3\]
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[^>]*> ec92 0e86 vldrb.s16 q0, \[r2, q3\]
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[^>]*> fc92 0e06 vldrb.u8 q0, \[r2, q3\]
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[^>]*> fc92 0e97 vldrh.u16 q0, \[r2, q3, uxtw #1\]
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[^>]*> fc92 0e97 vldrh.u16 q0, \[r2, q3, uxtw #1\]
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[^>]*> ec92 0f17 vldrh.s32 q0, \[r2, q3, uxtw #1\]
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[^>]*> fc92 0e97 vldrh.u16 q0, \[r2, q3, uxtw #1\]
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[^>]*> fc92 0e97 vldrh.u16 q0, \[r2, q3, uxtw #1\]
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[^>]*> fc92 0f17 vldrh.u32 q0, \[r2, q3, uxtw #1\]
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[^>]*> fc92 0f47 vldrw.u32 q0, \[r2, q3, uxtw #2\]
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[^>]*> fc92 0f47 vldrw.u32 q0, \[r2, q3, uxtw #2\]
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[^>]*> fc92 0f47 vldrw.u32 q0, \[r2, q3, uxtw #2\]
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[^>]*> fc92 0f47 vldrw.u32 q0, \[r2, q3, uxtw #2\]
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[^>]*> fc92 0fd7 vldrd.u64 q0, \[r2, q3, uxtw #3\]
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[^>]*> fc92 0fd7 vldrd.u64 q0, \[r2, q3, uxtw #3\]
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[^>]*> fc92 0fd7 vldrd.u64 q0, \[r2, q3, uxtw #3\]
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[^>]*> fc92 0fd7 vldrd.u64 q0, \[r2, q3, uxtw #3\]
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@ -116,3 +116,16 @@ vldrde.u64 q2, [r0, q1]
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vpste
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vldrdt.u64 q3, [r3, q5, UXTW #3]
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vldrde.u64 q7, [r7, q4, UXTW #3]
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.irp dt, u8, s16, 8
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vldrb.\dt q0, [r2, q3]
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.endr
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.irp dt, 16, u16, s32, f16, p16, u32
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vldrh.\dt q0, [r2, q3, UXTW #1]
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.endr
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.irp dt, 32, u32, f32, p32
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vldrw.\dt q0, [r2, q3, UXTW #2]
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.endr
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.irp dt, 64, u64, f64, p64
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vldrd.\dt q0, [r2, q3, UXTW #3]
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.endr
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