Implement RDRSEED, ADX and PRFCHW instructions
gas/ * config/tc-i386.c: Add ADX, RDSEED and PRFCHW asm directives. * doc/c-i386.texi: Document the new directives. gas/testsuite/ * gas/i386/i386.exp: Run adx, rdseed and prefetchw tests. * gas/i386/x86-64-arch-2.s: Use prefetchw as 3dnow and Prfchw tests. * gas/i386/arch-10.s: Likewise. * gas/i386/arch-10-1.l: Changed correspondingly. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.d: Likewise. * gas/i386/arch-10-lzcnt.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-arch-2-lzcnt.d: Likewise. * gas/i386/ilp32/x86-64-arch-2.d: Likewise. * gas/i386/arch-10-prefetchw.d: New file. * gas/i386/x86-64-arch-2-prefetchw.d: Likewise. * gas/i386/rdseed.s: Likewise. * gas/i386/rdseed.d: Likewise. * gas/i386/rdseed-intel.d: Likewise. * gas/i386/adx.s: Likewise. * gas/i386/adx.d: Likewise. * gas/i386/adx-intel.d: Likewise. * gas/i386/x86-64-rdseed.s: Likewise. * gas/i386/x86-64-rdseed.d: Likewise. * gas/i386/x86-64-rdseed-intel.d: Likewise. * gas/i386/x86-64-adx.s: Likewise. * gas/i386/x86-64-adx.d: Likewise. * gas/i386/x86-64-adx-intel.d: Likewise. opcodes/ * i386-dis.c (PREFIX_0F38F6): New. (prefix_table): Add adcx, adox instructions. (three_byte_table): Use PREFIX_0F38F6. (mod_table): Add rdseed instruction. * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW. (cpu_flags): Likewise. * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW. (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw. * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend prefetchw. * i386-tbl.h: Regenerate. * i386-init.h: Likewise.
This commit is contained in:
H.J. Lu
parent
094b34ac0b
commit
e2e1fcde62
@ -1,3 +1,8 @@
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2012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* config/tc-i386.c: Add ADX, RDSEED and PRFCHW asm directives.
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* doc/c-i386.texi: Document the new directives.
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2012-07-02 Nick Clifton <nickc@redhat.com>
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* write.c (fixup_segment): Only perform the subtraction of an
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@ -767,6 +767,12 @@ static const arch_entry cpu_arch[] =
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CPU_BMI_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
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CPU_TBM_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
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CPU_ADX_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
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CPU_RDSEED_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
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CPU_PRFCHW_FLAGS, 0, 0 },
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};
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#ifdef I386COFF
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@ -143,6 +143,9 @@ accept various extension mnemonics. For example,
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@code{nosse},
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@code{avx},
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@code{avx2},
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@code{adx},
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@code{rdseed},
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@code{prfchw},
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@code{noavx},
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@code{vmx},
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@code{vmfunc},
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@ -1018,7 +1021,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
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@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
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@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
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@item @samp{.rtm}
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@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
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@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
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@ -1,3 +1,32 @@
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2012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* gas/i386/i386.exp: Run adx, rdseed and prefetchw tests.
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* gas/i386/x86-64-arch-2.s: Use prefetchw as 3dnow and Prfchw tests.
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* gas/i386/arch-10.s: Likewise.
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* gas/i386/arch-10-1.l: Changed correspondingly.
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* gas/i386/arch-10-2.l: Likewise.
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* gas/i386/arch-10-3.l: Likewise.
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* gas/i386/arch-10-4.l: Likewise.
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* gas/i386/arch-10.d: Likewise.
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* gas/i386/arch-10-lzcnt.d: Likewise.
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* gas/i386/x86-64-arch-2.d: Likewise.
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* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
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* gas/i386/ilp32/x86-64-arch-2.d: Likewise.
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* gas/i386/arch-10-prefetchw.d: New file.
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* gas/i386/x86-64-arch-2-prefetchw.d: Likewise.
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* gas/i386/rdseed.s: Likewise.
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* gas/i386/rdseed.d: Likewise.
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* gas/i386/rdseed-intel.d: Likewise.
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* gas/i386/adx.s: Likewise.
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* gas/i386/adx.d: Likewise.
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* gas/i386/adx-intel.d: Likewise.
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* gas/i386/x86-64-rdseed.s: Likewise.
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* gas/i386/x86-64-rdseed.d: Likewise.
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* gas/i386/x86-64-rdseed-intel.d: Likewise.
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* gas/i386/x86-64-adx.s: Likewise.
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* gas/i386/x86-64-adx.d: Likewise.
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* gas/i386/x86-64-adx-intel.d: Likewise.
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2012-07-02 Roland McGrath <mcgrathr@google.com>
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* gas/i386/rep-suffix.s: Add 'rep nop' case.
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31
gas/testsuite/gas/i386/adx-intel.d
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31
gas/testsuite/gas/i386/adx-intel.d
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@ -0,0 +1,31 @@
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#objdump: -dwMintel
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#name: i386 ADX (Intel disassembly)
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#source: adx.s
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 66 0f 38 f6 81 90 01 00 00 adcx eax,DWORD PTR \[ecx\+0x190\]
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[ ]*[a-f0-9]+: 66 0f 38 f6 ca adcx ecx,edx
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[ ]*[a-f0-9]+: 66 0f 38 f6 94 f4 0f 04 f6 ff adcx edx,DWORD PTR \[esp\+esi\*8-0x9fbf1\]
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[ ]*[a-f0-9]+: 66 0f 38 f6 00 adcx eax,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 f6 ca adcx ecx,edx
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[ ]*[a-f0-9]+: 66 0f 38 f6 00 adcx eax,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 81 90 01 00 00 adox eax,DWORD PTR \[ecx\+0x190\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 ca adox ecx,edx
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[ ]*[a-f0-9]+: f3 0f 38 f6 94 f4 0f 04 f6 ff adox edx,DWORD PTR \[esp\+esi\*8-0x9fbf1\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 00 adox eax,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 ca adox ecx,edx
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[ ]*[a-f0-9]+: f3 0f 38 f6 00 adox eax,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 f6 82 8f 01 00 00 adcx eax,DWORD PTR \[edx\+0x18f\]
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[ ]*[a-f0-9]+: 66 0f 38 f6 d1 adcx edx,ecx
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[ ]*[a-f0-9]+: 66 0f 38 f6 94 f4 c0 1d fe ff adcx edx,DWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+: 66 0f 38 f6 00 adcx eax,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 82 8f 01 00 00 adox eax,DWORD PTR \[edx\+0x18f\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 d1 adox edx,ecx
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[ ]*[a-f0-9]+: f3 0f 38 f6 94 f4 c0 1d fe ff adox edx,DWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 00 adox eax,DWORD PTR \[eax\]
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#pass
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30
gas/testsuite/gas/i386/adx.d
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30
gas/testsuite/gas/i386/adx.d
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@ -0,0 +1,30 @@
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#objdump: -dw
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#name: i386 ADX
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 66 0f 38 f6 81 90 01 00 00 adcx 0x190\(%ecx\),%eax
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[ ]*[a-f0-9]+: 66 0f 38 f6 ca adcx %edx,%ecx
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[ ]*[a-f0-9]+: 66 0f 38 f6 94 f4 0f 04 f6 ff adcx -0x9fbf1\(%esp,%esi,8\),%edx
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[ ]*[a-f0-9]+: 66 0f 38 f6 00 adcx \(%eax\),%eax
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[ ]*[a-f0-9]+: 66 0f 38 f6 ca adcx %edx,%ecx
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[ ]*[a-f0-9]+: 66 0f 38 f6 00 adcx \(%eax\),%eax
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[ ]*[a-f0-9]+: f3 0f 38 f6 81 90 01 00 00 adox 0x190\(%ecx\),%eax
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[ ]*[a-f0-9]+: f3 0f 38 f6 ca adox %edx,%ecx
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[ ]*[a-f0-9]+: f3 0f 38 f6 94 f4 0f 04 f6 ff adox -0x9fbf1\(%esp,%esi,8\),%edx
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[ ]*[a-f0-9]+: f3 0f 38 f6 00 adox \(%eax\),%eax
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[ ]*[a-f0-9]+: f3 0f 38 f6 ca adox %edx,%ecx
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[ ]*[a-f0-9]+: f3 0f 38 f6 00 adox \(%eax\),%eax
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[ ]*[a-f0-9]+: 66 0f 38 f6 82 8f 01 00 00 adcx 0x18f\(%edx\),%eax
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[ ]*[a-f0-9]+: 66 0f 38 f6 d1 adcx %ecx,%edx
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[ ]*[a-f0-9]+: 66 0f 38 f6 94 f4 c0 1d fe ff adcx -0x1e240\(%esp,%esi,8\),%edx
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[ ]*[a-f0-9]+: 66 0f 38 f6 00 adcx \(%eax\),%eax
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[ ]*[a-f0-9]+: f3 0f 38 f6 82 8f 01 00 00 adox 0x18f\(%edx\),%eax
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[ ]*[a-f0-9]+: f3 0f 38 f6 d1 adox %ecx,%edx
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[ ]*[a-f0-9]+: f3 0f 38 f6 94 f4 c0 1d fe ff adox -0x1e240\(%esp,%esi,8\),%edx
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[ ]*[a-f0-9]+: f3 0f 38 f6 00 adox \(%eax\),%eax
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#pass
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30
gas/testsuite/gas/i386/adx.s
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30
gas/testsuite/gas/i386/adx.s
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# Check ADX instructions.
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.allow_index_reg
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.text
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_start:
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adcx 400(%ecx), %eax
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adcx %edx, %ecx
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adcx -654321(%esp,%esi,8), %edx
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adcx (%eax), %eax
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adcxl %edx, %ecx
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adcxl (%eax), %eax
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adox 400(%ecx), %eax
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adox %edx, %ecx
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adox -654321(%esp,%esi,8), %edx
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adox (%eax), %eax
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adoxl %edx, %ecx
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adoxl (%eax), %eax
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.intel_syntax noprefix
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adcx eax, DWORD PTR [edx+399]
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adcx edx, ecx
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adcx edx, DWORD PTR [esp+esi*8-123456]
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adcx eax, DWORD PTR [eax]
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adox eax, DWORD PTR [edx+399]
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adox edx, ecx
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adox edx, DWORD PTR [esp+esi*8-123456]
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adox eax, DWORD PTR [eax]
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@ -30,7 +30,6 @@
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.*:60: Error: .*
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.*:62: Error: .*
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.*:64: Error: .*
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.*:66: Error: .*
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GAS LISTING .*
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@ -83,24 +82,22 @@ GAS LISTING .*
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[ ]*46[ ]+invept \(%ecx\),%ebx
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[ ]*47[ ]+\# RDTSCP
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[ ]*48[ ]+rdtscp
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[ ]*49[ ]+\# 3DNow
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[ ]*50[ ]+pmulhrw %mm4,%mm3
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[ ]*51[ ]+\# 3DNow Extensions
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[ ]*52[ ]+pswapd %mm4,%mm3
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[ ]*53[ ]+\# SSE4a
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[ ]*54[ ]+insertq %xmm2,%xmm1
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[ ]*55[ ]+\# SVME
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[ ]*56[ ]+vmload
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[ ]*49[ ]+\# 3DNow or PRFCHW
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[ ]*50[ ]+prefetchw 0x1000\(,%esi,2\)
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[ ]*51[ ]+\# SSE4a
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[ ]*52[ ]+insertq %xmm2,%xmm1
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[ ]*53[ ]+\# SVME
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[ ]*54[ ]+vmload
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[ ]*55[ ]+\# ABM/LZCNT
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[ ]*56[ ]+lzcnt %ecx,%ebx
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GAS LISTING .*
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[ ]*57[ ]+\# ABM/LZCNT
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[ ]*58[ ]+lzcnt %ecx,%ebx
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[ ]*59[ ]+\# PadLock
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[ ]*60[ ]+xstorerng
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[ ]*61[ ]+\# nop
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[ ]*62[ ]+nopl \(%eax\)
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[ ]*63[ ]+\# BMI
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[ ]*64[ ]+blsr %ecx,%ebx
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[ ]*65[ ]+\# TBM
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[ ]*66[ ]+blcfill %ecx,%ebx
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[ ]*57[ ]+\# PadLock
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[ ]*58[ ]+xstorerng
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[ ]*59[ ]+\# nop
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[ ]*60[ ]+nopl \(%eax\)
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[ ]*61[ ]+\# BMI
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[ ]*62[ ]+blsr %ecx,%ebx
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[ ]*63[ ]+\# TBM
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[ ]*64[ ]+blcfill %ecx,%ebx
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@ -29,7 +29,6 @@
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.*:60: Error: .*
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.*:62: Error: .*
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.*:64: Error: .*
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.*:66: Error: .*
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GAS LISTING .*
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@ -82,24 +81,22 @@ GAS LISTING .*
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[ ]*46[ ]+invept \(%ecx\),%ebx
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[ ]*47[ ]+\# RDTSCP
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[ ]*48[ ]+rdtscp
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[ ]*49[ ]+\# 3DNow
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[ ]*50[ ]+pmulhrw %mm4,%mm3
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[ ]*51[ ]+\# 3DNow Extensions
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[ ]*52[ ]+pswapd %mm4,%mm3
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[ ]*53[ ]+\# SSE4a
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[ ]*54[ ]+insertq %xmm2,%xmm1
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[ ]*55[ ]+\# SVME
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[ ]*56[ ]+vmload
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[ ]*49[ ]+\# 3DNow or PRFCHW
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[ ]*50[ ]+prefetchw 0x1000\(,%esi,2\)
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[ ]*51[ ]+\# SSE4a
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[ ]*52[ ]+insertq %xmm2,%xmm1
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[ ]*53[ ]+\# SVME
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[ ]*54[ ]+vmload
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[ ]*55[ ]+\# ABM/LZCNT
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[ ]*56[ ]+lzcnt %ecx,%ebx
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GAS LISTING .*
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[ ]*57[ ]+\# ABM/LZCNT
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[ ]*58[ ]+lzcnt %ecx,%ebx
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[ ]*59[ ]+\# PadLock
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[ ]*60[ ]+xstorerng
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[ ]*61[ ]+\# nop
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[ ]*62[ ]+nopl \(%eax\)
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[ ]*63[ ]+\# BMI
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[ ]*64[ ]+blsr %ecx,%ebx
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[ ]*65[ ]+\# TBM
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[ ]*66[ ]+blcfill %ecx,%ebx
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[ ]*57[ ]+\# PadLock
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[ ]*58[ ]+xstorerng
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[ ]*59[ ]+\# nop
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[ ]*60[ ]+nopl \(%eax\)
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[ ]*61[ ]+\# BMI
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[ ]*62[ ]+blsr %ecx,%ebx
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[ ]*63[ ]+\# TBM
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[ ]*64[ ]+blcfill %ecx,%ebx
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@ -22,7 +22,6 @@
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.*:60: Error: .*
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.*:62: Error: .*
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.*:64: Error: .*
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.*:66: Error: .*
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GAS LISTING .*
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@ -78,24 +77,22 @@ GAS LISTING .*
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[ ]*46[ ]+invept \(%ecx\),%ebx
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[ ]*47[ ]+\# RDTSCP
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[ ]*48[ ]+rdtscp
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[ ]*49[ ]+\# 3DNow
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[ ]*50[ ]+pmulhrw %mm4,%mm3
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[ ]*51[ ]+\# 3DNow Extensions
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[ ]*52[ ]+pswapd %mm4,%mm3
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[ ]*53[ ]+\# SSE4a
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[ ]*49[ ]+\# 3DNow or PRFCHW
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[ ]*50[ ]+prefetchw 0x1000\(,%esi,2\)
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[ ]*51[ ]+\# SSE4a
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[ ]*52[ ]+insertq %xmm2,%xmm1
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[ ]*53[ ]+\# SVME
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GAS LISTING .*
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[ ]*54[ ]+insertq %xmm2,%xmm1
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[ ]*55[ ]+\# SVME
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[ ]*56[ ]+vmload
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[ ]*57[ ]+\# ABM/LZCNT
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[ ]*58[ ]+lzcnt %ecx,%ebx
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[ ]*59[ ]+\# PadLock
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[ ]*60[ ]+xstorerng
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[ ]*61[ ]+\# nop
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[ ]*62[ ]+nopl \(%eax\)
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[ ]*63[ ]+\# BMI
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[ ]*64[ ]+blsr %ecx,%ebx
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[ ]*65[ ]+\# TBM
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[ ]*66[ ]+blcfill %ecx,%ebx
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[ ]*54[ ]+vmload
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[ ]*55[ ]+\# ABM/LZCNT
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[ ]*56[ ]+lzcnt %ecx,%ebx
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[ ]*57[ ]+\# PadLock
|
||||
[ ]*58[ ]+xstorerng
|
||||
[ ]*59[ ]+\# nop
|
||||
[ ]*60[ ]+nopl \(%eax\)
|
||||
[ ]*61[ ]+\# BMI
|
||||
[ ]*62[ ]+blsr %ecx,%ebx
|
||||
[ ]*63[ ]+\# TBM
|
||||
[ ]*64[ ]+blcfill %ecx,%ebx
|
||||
|
||||
@ -20,7 +20,6 @@
|
||||
.*:60: Error: .*
|
||||
.*:62: Error: .*
|
||||
.*:64: Error: .*
|
||||
.*:66: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
@ -76,24 +75,22 @@ GAS LISTING .*
|
||||
[ ]*46[ ]+invept \(%ecx\),%ebx
|
||||
[ ]*47[ ]+\# RDTSCP
|
||||
[ ]*48[ ]+rdtscp
|
||||
[ ]*49[ ]+\# 3DNow
|
||||
[ ]*50[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*51[ ]+\# 3DNow Extensions
|
||||
[ ]*52[ ]+pswapd %mm4,%mm3
|
||||
[ ]*53[ ]+\# SSE4a
|
||||
[ ]*49[ ]+\# 3DNow or PRFCHW
|
||||
[ ]*50[ ]+prefetchw 0x1000\(,%esi,2\)
|
||||
[ ]*51[ ]+\# SSE4a
|
||||
[ ]*52[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*53[ ]+\# SVME
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*54[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*55[ ]+\# SVME
|
||||
[ ]*56[ ]+vmload
|
||||
[ ]*57[ ]+\# ABM/LZCNT
|
||||
[ ]*58[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*59[ ]+\# PadLock
|
||||
[ ]*60[ ]+xstorerng
|
||||
[ ]*61[ ]+\# nop
|
||||
[ ]*62[ ]+nopl \(%eax\)
|
||||
[ ]*63[ ]+\# BMI
|
||||
[ ]*64[ ]+blsr %ecx,%ebx
|
||||
[ ]*65[ ]+\# TBM
|
||||
[ ]*66[ ]+blcfill %ecx,%ebx
|
||||
[ ]*54[ ]+vmload
|
||||
[ ]*55[ ]+\# ABM/LZCNT
|
||||
[ ]*56[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*57[ ]+\# PadLock
|
||||
[ ]*58[ ]+xstorerng
|
||||
[ ]*59[ ]+\# nop
|
||||
[ ]*60[ ]+nopl \(%eax\)
|
||||
[ ]*61[ ]+\# BMI
|
||||
[ ]*62[ ]+blsr %ecx,%ebx
|
||||
[ ]*63[ ]+\# TBM
|
||||
[ ]*64[ ]+blcfill %ecx,%ebx
|
||||
|
||||
@ -31,8 +31,7 @@ Disassembly of section .text:
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
|
||||
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%esi,2\)
|
||||
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
|
||||
[ ]*[a-f0-9]+: 0f 01 da vmload
|
||||
[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
|
||||
|
||||
42
gas/testsuite/gas/i386/arch-10-prefetchw.d
Normal file
42
gas/testsuite/gas/i386/arch-10-prefetchw.d
Normal file
@ -0,0 +1,42 @@
|
||||
#source: arch-10.s
|
||||
#as: -march=i686+nop+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+sse4a+svme+lzcnt+padlock+bmi+tbm+prfchw
|
||||
#objdump: -dw
|
||||
#name: i386 arch 10 (prefetchw)
|
||||
|
||||
.*: file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <.text>:
|
||||
[ ]*[a-f0-9]+: 0f 44 d8 cmove %eax,%ebx
|
||||
[ ]*[a-f0-9]+: 0f ae 38 clflush \(%eax\)
|
||||
[ ]*[a-f0-9]+: 0f 05 syscall
|
||||
[ ]*[a-f0-9]+: 0f fc dc paddb %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: f3 0f 58 dc addss %xmm4,%xmm3
|
||||
[ ]*[a-f0-9]+: f2 0f 58 dc addsd %xmm4,%xmm3
|
||||
[ ]*[a-f0-9]+: 66 0f d0 dc addsubpd %xmm4,%xmm3
|
||||
[ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3
|
||||
[ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3
|
||||
[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx
|
||||
[ ]*[a-f0-9]+: c5 fc 77 vzeroall
|
||||
[ ]*[a-f0-9]+: 0f 01 c4 vmxoff
|
||||
[ ]*[a-f0-9]+: 0f 37 getsec
|
||||
[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
|
||||
[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \(%ecx\)
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%ecx\),%xmm0,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 49 44 d4 08 vpclmulqdq \$0x8,%xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
|
||||
[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%esi,2\)
|
||||
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
|
||||
[ ]*[a-f0-9]+: 0f 01 da vmload
|
||||
[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
|
||||
[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng
|
||||
[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\)
|
||||
[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
|
||||
[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx
|
||||
#pass
|
||||
@ -30,8 +30,7 @@ Disassembly of section .text:
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx
|
||||
[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
|
||||
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%esi,2\)
|
||||
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
|
||||
[ ]*[a-f0-9]+: 0f 01 da vmload
|
||||
[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
|
||||
|
||||
@ -46,10 +46,8 @@ movbe (%ecx),%ebx
|
||||
invept (%ecx),%ebx
|
||||
# RDTSCP
|
||||
rdtscp
|
||||
# 3DNow
|
||||
pmulhrw %mm4,%mm3
|
||||
# 3DNow Extensions
|
||||
pswapd %mm4,%mm3
|
||||
# 3DNow or PRFCHW
|
||||
prefetchw 0x1000(,%esi,2)
|
||||
# SSE4a
|
||||
insertq %xmm2,%xmm1
|
||||
# SVME
|
||||
|
||||
@ -126,6 +126,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
||||
run_dump_test "arch-9"
|
||||
run_dump_test "arch-10"
|
||||
run_dump_test "arch-10-lzcnt"
|
||||
run_dump_test "arch-10-prefetchw"
|
||||
run_list_test "arch-10-1" "-march=generic32 -I${srcdir}/$subdir -al"
|
||||
run_list_test "arch-10-2" "-march=i686 -I${srcdir}/$subdir -al"
|
||||
run_list_test "arch-10-3" "-march=i686+sse4.2 -I${srcdir}/$subdir -al"
|
||||
@ -207,6 +208,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
||||
run_dump_test "bundle"
|
||||
run_dump_test "bundle-lock"
|
||||
run_dump_test "bundle-bad"
|
||||
run_dump_test "adx"
|
||||
run_dump_test "adx-intel"
|
||||
run_dump_test "rdseed"
|
||||
run_dump_test "rdseed-intel"
|
||||
|
||||
# These tests require support for 8 and 16 bit relocs,
|
||||
# so we only run them for ELF and COFF targets.
|
||||
@ -374,6 +379,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
||||
run_dump_test "x86-64-arch-1"
|
||||
run_dump_test "x86-64-arch-2"
|
||||
run_dump_test "x86-64-arch-2-lzcnt"
|
||||
run_dump_test "x86-64-arch-2-prefetchw"
|
||||
run_dump_test "x86-64-xsave"
|
||||
run_dump_test "x86-64-xsave-intel"
|
||||
run_dump_test "x86-64-aes"
|
||||
@ -437,6 +443,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
||||
run_dump_test "x86-64-rdrnd"
|
||||
run_dump_test "x86-64-rdrnd-intel"
|
||||
run_dump_test "x86-64-bundle"
|
||||
run_dump_test "x86-64-adx"
|
||||
run_dump_test "x86-64-adx-intel"
|
||||
run_dump_test "x86-64-rdseed"
|
||||
run_dump_test "x86-64-rdseed-intel"
|
||||
|
||||
if { ![istarget "*-*-aix*"]
|
||||
&& ![istarget "*-*-beos*"]
|
||||
|
||||
@ -31,8 +31,7 @@ Disassembly of section .text:
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx
|
||||
[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
|
||||
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%rsi,2\)
|
||||
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
|
||||
[ ]*[a-f0-9]+: 0f 01 da vmload
|
||||
[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
|
||||
|
||||
14
gas/testsuite/gas/i386/rdseed-intel.d
Normal file
14
gas/testsuite/gas/i386/rdseed-intel.d
Normal file
@ -0,0 +1,14 @@
|
||||
#objdump: -dwMintel
|
||||
#name: i386 RdSeed (Intel disassembly)
|
||||
#source: rdseed.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f c7 f8 rdseed ax
|
||||
[ ]*[a-f0-9]+: 0f c7 f8 rdseed eax
|
||||
[ ]*[a-f0-9]+: 66 0f c7 fb rdseed bx
|
||||
[ ]*[a-f0-9]+: 0f c7 fb rdseed ebx
|
||||
14
gas/testsuite/gas/i386/rdseed.d
Normal file
14
gas/testsuite/gas/i386/rdseed.d
Normal file
@ -0,0 +1,14 @@
|
||||
#objdump: -dw
|
||||
#name: i386 RdSeed
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f c7 f8 rdseed %ax
|
||||
[ ]*[a-f0-9]+: 0f c7 f8 rdseed %eax
|
||||
[ ]*[a-f0-9]+: 66 0f c7 fb rdseed %bx
|
||||
[ ]*[a-f0-9]+: 0f c7 fb rdseed %ebx
|
||||
#pass
|
||||
10
gas/testsuite/gas/i386/rdseed.s
Normal file
10
gas/testsuite/gas/i386/rdseed.s
Normal file
@ -0,0 +1,10 @@
|
||||
# Check RdSeed instruction.
|
||||
|
||||
.text
|
||||
foo:
|
||||
rdseed %ax
|
||||
rdseed %eax
|
||||
|
||||
.intel_syntax noprefix
|
||||
rdseed bx
|
||||
rdseed ebx
|
||||
51
gas/testsuite/gas/i386/x86-64-adx-intel.d
Normal file
51
gas/testsuite/gas/i386/x86-64-adx-intel.d
Normal file
@ -0,0 +1,51 @@
|
||||
#objdump: -drwMintel
|
||||
#name: x86-64 ADX(Intel mode)
|
||||
#source: x86-64-adx.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 81 90 01 00 00 adcx eax,DWORD PTR \[ecx\+0x190\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f6 ca adcx ecx,edx
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 94 f4 0f 04 f6 ff adcx edx,DWORD PTR \[esp\+esi\*8-0x9fbf1\]
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 00 adcx eax,DWORD PTR \[eax\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f6 ca adcx ecx,edx
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 00 adcx eax,DWORD PTR \[eax\]
|
||||
[ ]*[a-f0-9]+: 66 4c 0f 38 f6 99 90 01 00 00 adcx r11,QWORD PTR \[rcx\+0x190\]
|
||||
[ ]*[a-f0-9]+: 66 4d 0f 38 f6 e6 adcx r12,r14
|
||||
[ ]*[a-f0-9]+: 67 66 48 0f 38 f6 94 f4 0f 04 f6 ff adcx rdx,QWORD PTR \[esp\+esi\*8-0x9fbf1\]
|
||||
[ ]*[a-f0-9]+: 66 49 0f 38 f6 00 adcx rax,QWORD PTR \[r8\]
|
||||
[ ]*[a-f0-9]+: 66 48 0f 38 f6 ca adcx rcx,rdx
|
||||
[ ]*[a-f0-9]+: 66 48 0f 38 f6 00 adcx rax,QWORD PTR \[rax\]
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 81 90 01 00 00 adox eax,DWORD PTR \[ecx\+0x190\]
|
||||
[ ]*[a-f0-9]+: f3 0f 38 f6 ca adox ecx,edx
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 94 f4 0f 04 f6 ff adox edx,DWORD PTR \[esp\+esi\*8-0x9fbf1\]
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 00 adox eax,DWORD PTR \[eax\]
|
||||
[ ]*[a-f0-9]+: f3 0f 38 f6 ca adox ecx,edx
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 00 adox eax,DWORD PTR \[eax\]
|
||||
[ ]*[a-f0-9]+: f3 4c 0f 38 f6 99 90 01 00 00 adox r11,QWORD PTR \[rcx\+0x190\]
|
||||
[ ]*[a-f0-9]+: f3 4d 0f 38 f6 e6 adox r12,r14
|
||||
[ ]*[a-f0-9]+: 67 f3 48 0f 38 f6 94 f4 0f 04 f6 ff adox rdx,QWORD PTR \[esp\+esi\*8-0x9fbf1\]
|
||||
[ ]*[a-f0-9]+: f3 49 0f 38 f6 00 adox rax,QWORD PTR \[r8\]
|
||||
[ ]*[a-f0-9]+: f3 48 0f 38 f6 ca adox rcx,rdx
|
||||
[ ]*[a-f0-9]+: f3 48 0f 38 f6 00 adox rax,QWORD PTR \[rax\]
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 82 8f 01 00 00 adcx eax,DWORD PTR \[edx\+0x18f\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f6 d1 adcx edx,ecx
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 94 f4 c0 1d fe ff adcx edx,DWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 00 adcx eax,DWORD PTR \[eax\]
|
||||
[ ]*[a-f0-9]+: 66 49 0f 38 f6 83 8f 01 00 00 adcx rax,QWORD PTR \[r11\+0x18f\]
|
||||
[ ]*[a-f0-9]+: 66 49 0f 38 f6 d1 adcx rdx,r9
|
||||
[ ]*[a-f0-9]+: 66 48 0f 38 f6 94 f4 c0 1d fe ff adcx rdx,QWORD PTR \[rsp\+rsi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 66 48 0f 38 f6 03 adcx rax,QWORD PTR \[rbx\]
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 82 8f 01 00 00 adox eax,DWORD PTR \[edx\+0x18f\]
|
||||
[ ]*[a-f0-9]+: f3 0f 38 f6 d1 adox edx,ecx
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 94 f4 c0 1d fe ff adox edx,DWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 00 adox eax,DWORD PTR \[eax\]
|
||||
[ ]*[a-f0-9]+: f3 49 0f 38 f6 83 8f 01 00 00 adox rax,QWORD PTR \[r11\+0x18f\]
|
||||
[ ]*[a-f0-9]+: f3 49 0f 38 f6 d1 adox rdx,r9
|
||||
[ ]*[a-f0-9]+: f3 48 0f 38 f6 94 f4 c0 1d fe ff adox rdx,QWORD PTR \[rsp\+rsi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: f3 48 0f 38 f6 03 adox rax,QWORD PTR \[rbx\]
|
||||
#pass
|
||||
50
gas/testsuite/gas/i386/x86-64-adx.d
Normal file
50
gas/testsuite/gas/i386/x86-64-adx.d
Normal file
@ -0,0 +1,50 @@
|
||||
#objdump: -dw
|
||||
#name: x86-64 ADX
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 81 90 01 00 00 adcx 0x190\(%ecx\),%eax
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f6 ca adcx %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 94 f4 0f 04 f6 ff adcx -0x9fbf1\(%esp,%esi,8\),%edx
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 00 adcx \(%eax\),%eax
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f6 ca adcx %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 00 adcx \(%eax\),%eax
|
||||
[ ]*[a-f0-9]+: 66 4c 0f 38 f6 99 90 01 00 00 adcx 0x190\(%rcx\),%r11
|
||||
[ ]*[a-f0-9]+: 66 4d 0f 38 f6 e6 adcx %r14,%r12
|
||||
[ ]*[a-f0-9]+: 67 66 48 0f 38 f6 94 f4 0f 04 f6 ff adcx -0x9fbf1\(%esp,%esi,8\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 49 0f 38 f6 00 adcx \(%r8\),%rax
|
||||
[ ]*[a-f0-9]+: 66 48 0f 38 f6 ca adcx %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: 66 48 0f 38 f6 00 adcx \(%rax\),%rax
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 81 90 01 00 00 adox 0x190\(%ecx\),%eax
|
||||
[ ]*[a-f0-9]+: f3 0f 38 f6 ca adox %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 94 f4 0f 04 f6 ff adox -0x9fbf1\(%esp,%esi,8\),%edx
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 00 adox \(%eax\),%eax
|
||||
[ ]*[a-f0-9]+: f3 0f 38 f6 ca adox %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 00 adox \(%eax\),%eax
|
||||
[ ]*[a-f0-9]+: f3 4c 0f 38 f6 99 90 01 00 00 adox 0x190\(%rcx\),%r11
|
||||
[ ]*[a-f0-9]+: f3 4d 0f 38 f6 e6 adox %r14,%r12
|
||||
[ ]*[a-f0-9]+: 67 f3 48 0f 38 f6 94 f4 0f 04 f6 ff adox -0x9fbf1\(%esp,%esi,8\),%rdx
|
||||
[ ]*[a-f0-9]+: f3 49 0f 38 f6 00 adox \(%r8\),%rax
|
||||
[ ]*[a-f0-9]+: f3 48 0f 38 f6 ca adox %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: f3 48 0f 38 f6 00 adox \(%rax\),%rax
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 82 8f 01 00 00 adcx 0x18f\(%edx\),%eax
|
||||
[ ]*[a-f0-9]+: 66 0f 38 f6 d1 adcx %ecx,%edx
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 94 f4 c0 1d fe ff adcx -0x1e240\(%esp,%esi,8\),%edx
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 f6 00 adcx \(%eax\),%eax
|
||||
[ ]*[a-f0-9]+: 66 49 0f 38 f6 83 8f 01 00 00 adcx 0x18f\(%r11\),%rax
|
||||
[ ]*[a-f0-9]+: 66 49 0f 38 f6 d1 adcx %r9,%rdx
|
||||
[ ]*[a-f0-9]+: 66 48 0f 38 f6 94 f4 c0 1d fe ff adcx -0x1e240\(%rsp,%rsi,8\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 48 0f 38 f6 03 adcx \(%rbx\),%rax
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 82 8f 01 00 00 adox 0x18f\(%edx\),%eax
|
||||
[ ]*[a-f0-9]+: f3 0f 38 f6 d1 adox %ecx,%edx
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 94 f4 c0 1d fe ff adox -0x1e240\(%esp,%esi,8\),%edx
|
||||
[ ]*[a-f0-9]+: 67 f3 0f 38 f6 00 adox \(%eax\),%eax
|
||||
[ ]*[a-f0-9]+: f3 49 0f 38 f6 83 8f 01 00 00 adox 0x18f\(%r11\),%rax
|
||||
[ ]*[a-f0-9]+: f3 49 0f 38 f6 d1 adox %r9,%rdx
|
||||
[ ]*[a-f0-9]+: f3 48 0f 38 f6 94 f4 c0 1d fe ff adox -0x1e240\(%rsp,%rsi,8\),%rdx
|
||||
[ ]*[a-f0-9]+: f3 48 0f 38 f6 03 adox \(%rbx\),%rax
|
||||
#pass
|
||||
53
gas/testsuite/gas/i386/x86-64-adx.s
Normal file
53
gas/testsuite/gas/i386/x86-64-adx.s
Normal file
@ -0,0 +1,53 @@
|
||||
# Check 64 bit ADX instructions.
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
adcx 400(%ecx), %eax
|
||||
adcx %edx, %ecx
|
||||
adcx -654321(%esp,%esi,8), %edx
|
||||
adcx (%eax), %eax
|
||||
adcxl %edx, %ecx
|
||||
adcxl (%eax), %eax
|
||||
|
||||
adcx 400(%rcx), %r11
|
||||
adcx %r14, %r12
|
||||
adcx -654321(%esp,%esi,8), %rdx
|
||||
adcx (%r8), %rax
|
||||
adcxq %rdx, %rcx
|
||||
adcxq (%rax), %rax
|
||||
|
||||
adox 400(%ecx), %eax
|
||||
adox %edx, %ecx
|
||||
adox -654321(%esp,%esi,8), %edx
|
||||
adox (%eax), %eax
|
||||
adoxl %edx, %ecx
|
||||
adoxl (%eax), %eax
|
||||
|
||||
adox 400(%rcx), %r11
|
||||
adox %r14, %r12
|
||||
adox -654321(%esp,%esi,8), %rdx
|
||||
adox (%r8), %rax
|
||||
adoxq %rdx, %rcx
|
||||
adoxq (%rax), %rax
|
||||
|
||||
.intel_syntax noprefix
|
||||
|
||||
adcx eax, DWORD PTR [edx+399]
|
||||
adcx edx, ecx
|
||||
adcx edx, DWORD PTR [esp+esi*8-123456]
|
||||
adcx eax, DWORD PTR [eax]
|
||||
|
||||
adcx rax, QWORD PTR [r11+399]
|
||||
adcx rdx, r9
|
||||
adcx rdx, QWORD PTR [rsp+rsi*8-123456]
|
||||
adcx rax, [rbx]
|
||||
|
||||
adox eax, DWORD PTR [edx+399]
|
||||
adox edx, ecx
|
||||
adox edx, DWORD PTR [esp+esi*8-123456]
|
||||
adox eax, DWORD PTR [eax]
|
||||
|
||||
adox rax, QWORD PTR [r11+399]
|
||||
adox rdx, r9
|
||||
adox rdx, QWORD PTR [rsp+rsi*8-123456]
|
||||
adox rax, QWORD PTR [rbx]
|
||||
@ -31,8 +31,7 @@ Disassembly of section .text:
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx
|
||||
[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
|
||||
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%rsi,2\)
|
||||
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
|
||||
[ ]*[a-f0-9]+: 0f 01 da vmload
|
||||
[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
|
||||
|
||||
41
gas/testsuite/gas/i386/x86-64-arch-2-prefetchw.d
Normal file
41
gas/testsuite/gas/i386/x86-64-arch-2-prefetchw.d
Normal file
@ -0,0 +1,41 @@
|
||||
#source: x86-64-arch-2.s
|
||||
#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+sse4a+svme+lzcnt+padlock+bmi+tbm+prfchw
|
||||
#objdump: -dw
|
||||
#name: x86-64 arch 2 (prefetchw)
|
||||
|
||||
.*: file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <.text>:
|
||||
[ ]*[a-f0-9]+: 0f 44 d8 cmove %eax,%ebx
|
||||
[ ]*[a-f0-9]+: 0f ae 38 clflush \(%rax\)
|
||||
[ ]*[a-f0-9]+: 0f 05 syscall
|
||||
[ ]*[a-f0-9]+: 0f fc dc paddb %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: f3 0f 58 dc addss %xmm4,%xmm3
|
||||
[ ]*[a-f0-9]+: f2 0f 58 dc addsd %xmm4,%xmm3
|
||||
[ ]*[a-f0-9]+: 66 0f d0 dc addsubpd %xmm4,%xmm3
|
||||
[ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3
|
||||
[ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3
|
||||
[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx
|
||||
[ ]*[a-f0-9]+: c5 fc 77 vzeroall
|
||||
[ ]*[a-f0-9]+: 0f 01 c4 vmxoff
|
||||
[ ]*[a-f0-9]+: 0f 37 getsec
|
||||
[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
|
||||
[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \(%rcx\)
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%rcx\),%xmm0,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 49 44 d4 08 vpclmulqdq \$0x8,%xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx
|
||||
[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
|
||||
[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%rsi,2\)
|
||||
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
|
||||
[ ]*[a-f0-9]+: 0f 01 da vmload
|
||||
[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
|
||||
[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng
|
||||
[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
|
||||
[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx
|
||||
#pass
|
||||
@ -30,8 +30,7 @@ Disassembly of section .text:
|
||||
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx
|
||||
[ ]*[a-f0-9]+: 0f 01 f9 rdtscp
|
||||
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0d 0c 75 00 10 00 00 prefetchw 0x1000\(,%rsi,2\)
|
||||
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
|
||||
[ ]*[a-f0-9]+: 0f 01 da vmload
|
||||
[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
|
||||
|
||||
@ -46,10 +46,8 @@ movbe (%rcx),%ebx
|
||||
invept (%rcx),%rbx
|
||||
# RDTSCP
|
||||
rdtscp
|
||||
# 3DNow
|
||||
pmulhrw %mm4,%mm3
|
||||
# 3DNow Extensions
|
||||
pswapd %mm4,%mm3
|
||||
# 3DNow or PRFCHW
|
||||
prefetchw 0x1000(,%rsi,2)
|
||||
# SSE4a
|
||||
insertq %xmm2,%xmm1
|
||||
# SVME
|
||||
|
||||
23
gas/testsuite/gas/i386/x86-64-rdseed-intel.d
Normal file
23
gas/testsuite/gas/i386/x86-64-rdseed-intel.d
Normal file
@ -0,0 +1,23 @@
|
||||
#objdump: -drwMintel
|
||||
#name: x86-64 RdSeed(Intel mode)
|
||||
#source: x86-64-rdseed.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f c7 f8 rdseed ax
|
||||
[ ]*[a-f0-9]+: 0f c7 f8 rdseed eax
|
||||
[ ]*[a-f0-9]+: 48 0f c7 f8 rdseed rax
|
||||
[ ]*[a-f0-9]+: 66 41 0f c7 fb rdseed r11w
|
||||
[ ]*[a-f0-9]+: 41 0f c7 fb rdseed r11d
|
||||
[ ]*[a-f0-9]+: 49 0f c7 fb rdseed r11
|
||||
[ ]*[a-f0-9]+: 66 0f c7 fb rdseed bx
|
||||
[ ]*[a-f0-9]+: 0f c7 fb rdseed ebx
|
||||
[ ]*[a-f0-9]+: 48 0f c7 fb rdseed rbx
|
||||
[ ]*[a-f0-9]+: 66 41 0f c7 fb rdseed r11w
|
||||
[ ]*[a-f0-9]+: 41 0f c7 fb rdseed r11d
|
||||
[ ]*[a-f0-9]+: 49 0f c7 fb rdseed r11
|
||||
#pass
|
||||
22
gas/testsuite/gas/i386/x86-64-rdseed.d
Normal file
22
gas/testsuite/gas/i386/x86-64-rdseed.d
Normal file
@ -0,0 +1,22 @@
|
||||
#objdump: -dw
|
||||
#name: x86-64 RdSeed
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f c7 f8 rdseed %ax
|
||||
[ ]*[a-f0-9]+: 0f c7 f8 rdseed %eax
|
||||
[ ]*[a-f0-9]+: 48 0f c7 f8 rdseed %rax
|
||||
[ ]*[a-f0-9]+: 66 41 0f c7 fb rdseed %r11w
|
||||
[ ]*[a-f0-9]+: 41 0f c7 fb rdseed %r11d
|
||||
[ ]*[a-f0-9]+: 49 0f c7 fb rdseed %r11
|
||||
[ ]*[a-f0-9]+: 66 0f c7 fb rdseed %bx
|
||||
[ ]*[a-f0-9]+: 0f c7 fb rdseed %ebx
|
||||
[ ]*[a-f0-9]+: 48 0f c7 fb rdseed %rbx
|
||||
[ ]*[a-f0-9]+: 66 41 0f c7 fb rdseed %r11w
|
||||
[ ]*[a-f0-9]+: 41 0f c7 fb rdseed %r11d
|
||||
[ ]*[a-f0-9]+: 49 0f c7 fb rdseed %r11
|
||||
#pass
|
||||
18
gas/testsuite/gas/i386/x86-64-rdseed.s
Normal file
18
gas/testsuite/gas/i386/x86-64-rdseed.s
Normal file
@ -0,0 +1,18 @@
|
||||
# Check 64-bit new RdSeed instruction.
|
||||
|
||||
.text
|
||||
foo:
|
||||
rdseed %ax
|
||||
rdseed %eax
|
||||
rdseed %rax
|
||||
rdseed %r11w
|
||||
rdseed %r11d
|
||||
rdseed %r11
|
||||
|
||||
.intel_syntax noprefix
|
||||
rdseed bx
|
||||
rdseed ebx
|
||||
rdseed rbx
|
||||
rdseed r11w
|
||||
rdseed r11d
|
||||
rdseed r11
|
||||
@ -1,3 +1,18 @@
|
||||
2012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
||||
|
||||
* i386-dis.c (PREFIX_0F38F6): New.
|
||||
(prefix_table): Add adcx, adox instructions.
|
||||
(three_byte_table): Use PREFIX_0F38F6.
|
||||
(mod_table): Add rdseed instruction.
|
||||
* i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
|
||||
(cpu_flags): Likewise.
|
||||
* i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
|
||||
(i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
|
||||
* i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
|
||||
prefetchw.
|
||||
* i386-tbl.h: Regenerate.
|
||||
* i386-init.h: Likewise.
|
||||
|
||||
2012-07-05 Thomas Schwinge <thomas@codesourcery.com>
|
||||
|
||||
* mips-dis.c: Remove gratuitous newline.
|
||||
|
||||
@ -851,6 +851,7 @@ enum
|
||||
PREFIX_0F38DF,
|
||||
PREFIX_0F38F0,
|
||||
PREFIX_0F38F1,
|
||||
PREFIX_0F38F6,
|
||||
PREFIX_0F3A08,
|
||||
PREFIX_0F3A09,
|
||||
PREFIX_0F3A0A,
|
||||
@ -3485,6 +3486,14 @@ static const struct dis386 prefix_table[][4] = {
|
||||
{ "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
|
||||
},
|
||||
|
||||
/* PREFIX_0F38F6 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "adoxS", { Gdq, Edq} },
|
||||
{ "adcxS", { Gdq, Edq} },
|
||||
{ Bad_Opcode },
|
||||
},
|
||||
|
||||
/* PREFIX_0F3A08 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
@ -6055,7 +6064,7 @@ static const struct dis386 three_byte_table[][256] = {
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_0F38F6) },
|
||||
{ Bad_Opcode },
|
||||
/* f8 */
|
||||
{ Bad_Opcode },
|
||||
@ -10323,6 +10332,7 @@ static const struct dis386 mod_table[][2] = {
|
||||
{
|
||||
/* MOD_0FC7_REG_7 */
|
||||
{ "vmptrst", { Mq } },
|
||||
{ "rdseed", { Ev } },
|
||||
},
|
||||
{
|
||||
/* MOD_0FD7 */
|
||||
|
||||
@ -192,6 +192,12 @@ static initializer cpu_flag_init[] =
|
||||
"unknown" },
|
||||
{ "CPU_K1OM_FLAGS",
|
||||
"unknown" },
|
||||
{ "CPU_ADX_FLAGS",
|
||||
"CpuADX" },
|
||||
{ "CPU_RDSEED_FLAGS",
|
||||
"CpuRdSeed" },
|
||||
{ "CPU_PRFCHW_FLAGS",
|
||||
"CpuPRFCHW" },
|
||||
};
|
||||
|
||||
static initializer operand_type_init[] =
|
||||
@ -359,6 +365,9 @@ static bitfield cpu_flags[] =
|
||||
BITFIELD (CpuRTM),
|
||||
BITFIELD (CpuINVPCID),
|
||||
BITFIELD (CpuVMFUNC),
|
||||
BITFIELD (CpuRDSEED),
|
||||
BITFIELD (CpuADX),
|
||||
BITFIELD (CpuPRFCHW),
|
||||
BITFIELD (Cpu64),
|
||||
BITFIELD (CpuNo64),
|
||||
#ifdef CpuUnused
|
||||
|
||||
@ -22,377 +22,470 @@
|
||||
#define CPU_UNKNOWN_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_PENTIUMPRO_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_COREI7_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_BDVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_BDVER2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_8087_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_287_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_387_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ANY87_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSH_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_NOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SYSCALL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ANY_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_XSAVEOPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_FMA4_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_XOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_LWP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_BMI_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_TBM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_RDTSCP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_FSGSBASE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_RDRND_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_F16C_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_BMI2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_LZCNT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_HLE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_RTM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_INVPCID_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_VMFUNC_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ANY_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_L1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
1, 1 } }
|
||||
|
||||
#define CPU_K1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
1, 1 } }
|
||||
|
||||
#define CPU_ADX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_RDSEED_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_PRFCHW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
||||
@ -144,6 +144,12 @@ enum
|
||||
CpuVMFUNC,
|
||||
/* 64bit support available, used by -march= in assembler. */
|
||||
CpuLM,
|
||||
/* RDRSEED instruction required. */
|
||||
CpuRDSEED,
|
||||
/* Multi-presisionn add-carry instructions are required. */
|
||||
CpuADX,
|
||||
/* Supports prefetchw instruction. */
|
||||
CpuPRFCHW,
|
||||
/* 64bit support required */
|
||||
Cpu64,
|
||||
/* Not supported in the 64bit mode */
|
||||
@ -223,6 +229,9 @@ typedef union i386_cpu_flags
|
||||
unsigned int cpuinvpcid:1;
|
||||
unsigned int cpuvmfunc:1;
|
||||
unsigned int cpulm:1;
|
||||
unsigned int cpurdseed:1;
|
||||
unsigned int cpuadx:1;
|
||||
unsigned int cpuprfchw:1;
|
||||
unsigned int cpu64:1;
|
||||
unsigned int cpuno64:1;
|
||||
#ifdef CpuUnused
|
||||
|
||||
@ -2966,7 +2966,7 @@ tzmsk, 2, 0x01, 0x4, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=
|
||||
// AMD 3DNow! instructions.
|
||||
|
||||
prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
prefetchw, 1, 0xf0d, 0x1, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
prefetchw, 1, 0xf0d, 0x1, 2, Cpu3dnow|CpuPRFCHW, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
femms, 0, 0xf0e, None, 2, Cpu3dnow, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
pavgusb, 2, 0xf0f, 0xbf, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX }
|
||||
pf2id, 2, 0xf0f, 0x1d, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX }
|
||||
@ -3053,3 +3053,8 @@ xcryptcfb, 0, 0xf30fa7, 0xe0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_
|
||||
xcryptofb, 0, 0xf30fa7, 0xe8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk|ImmExt, { 0 }
|
||||
// Alias for xstore-rng.
|
||||
xstore, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk|ImmExt, { 0 }
|
||||
|
||||
// Multy-precision Add Carry, rdseed instructions.
|
||||
adcx, 2, 0x660f38f6, None, 3, CpuADX, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
|
||||
adox, 2, 0xf30f38f6, None, 3, CpuADX, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
|
||||
rdseed, 1, 0xfc7, 0x7, 2, CpuRdSeed, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
|
||||
|
||||
8070
opcodes/i386-tbl.h
8070
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user