Add hwsync extended mnemonic.
This commit adds a new extended menmonic for "sync 0" (same as "sync"). The ISA documentation doesn't explicitly mention hwsync as an extended mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as the operation that gets performed when the sync's L field is 0. This is only enabled for POWER4 and later. opcodes/ * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic. gas/testsuite/ * gas/ppc/a2.d: Fixup test case due to new extended mnemonic. * gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests. * gas/ppc/power4.d: Likewise.
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@ -544,9 +544,9 @@ Disassembly of section \.text:
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810: (7e 95 01 90|90 01 95 7e) subfze r20,r21
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814: (7e 95 05 91|91 05 95 7e) subfzeo\. r20,r21
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818: (7e 95 05 90|90 05 95 7e) subfzeo r20,r21
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81c: (7c 00 04 ac|ac 04 00 7c) sync
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820: (7c 00 04 ac|ac 04 00 7c) sync
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824: (7c 00 04 ac|ac 04 00 7c) sync
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81c: (7c 00 04 ac|ac 04 00 7c) hwsync
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820: (7c 00 04 ac|ac 04 00 7c) hwsync
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824: (7c 00 04 ac|ac 04 00 7c) hwsync
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828: (7c 20 04 ac|ac 04 20 7c) lwsync
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82c: (7c aa 58 88|88 58 aa 7c) tdlge r10,r11
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830: (08 aa 00 64|64 00 aa 08) tdlgei r10,100
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@ -10,7 +10,7 @@ start address 0x0+
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Sections:
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Idx Name +Size +VMA +LMA +File off +Algn
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+0 \.text +0+cc +0+ +0+ +.*
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+0 \.text +0+e8 +0+ +0+ +.*
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+CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
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+1 \.data +0+20 +0+ +0+ +.*
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+CONTENTS, ALLOC, LOAD, DATA
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@ -99,3 +99,10 @@ Disassembly of section \.text:
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.*: (f8 05 00 12|12 00 05 f8) stq r0,16\(r5\)
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.*: (f8 45 00 12|12 00 45 f8) stq r2,16\(r5\)
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.*: (7c 00 03 e4|e4 03 00 7c) slbia
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.*: (7c 00 04 ac|ac 04 00 7c) hwsync
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.*: (7c 00 04 ac|ac 04 00 7c) hwsync
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.*: (7c 00 04 ac|ac 04 00 7c) hwsync
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.*: (7c 20 04 ac|ac 04 20 7c) lwsync
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.*: (7c 20 04 ac|ac 04 20 7c) lwsync
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.*: (7c 40 04 ac|ac 04 40 7c) ptesync
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.*: (7c 40 04 ac|ac 04 40 7c) ptesync
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@ -72,6 +72,13 @@ dsym1:
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stq 0,16(5)
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stq 2,16(5)
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slbia
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hwsync
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sync
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sync 0
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lwsync
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sync 1
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ptesync
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sync 2
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.section ".data"
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usym0: .llong 0xcafebabe
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@ -5465,6 +5465,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"lswi", X(31,597), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RAX, NBI}},
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{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
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{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
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{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
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{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
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{"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}},
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