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include/elf:

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* arm.h: Import complete list of official relocation names
	and numbers from AAELF.  Define FAKE_RELOCs for old names.
	Remove a few old names no longer used anywhere.

bfd:
	* elf32-arm.c: Wherever possible, use official reloc names
	from AAELF.
	(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
	(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
	(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
	(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
	(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
	(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
	elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
	Add many new relocations from AAELF.
	(elf32_arm_howto_from_type): Update to match.
	(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
	R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
	R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
	(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
	(elf32_arm_final_link_relocate): Add support for
	R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6.  Remove
	case entries redundant with default.

	* reloc.c: Reorganize ARM relocations.  Add Thumb
	assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
	BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
	Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
	BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
	Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
	* bfd-in2.h, libbfd.h: Regenerate.

opcodes:
	* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
	instructions.  Adjust disassembly of some opcodes to match
	unified syntax.
	(thumb32_opcodes): New table.
	(print_insn_thumb): Rename print_insn_thumb16; don't handle
	two-halfword branches here.
	(print_insn_thumb32): New function.
	(print_insn): Choose among print_insn_arm, print_insn_thumb16,
	and print_insn_thumb32.  Be consistent about order of
	halfwords when printing 32-bit instructions.

gas:
	* hash.c (hash_lookup): Add len parameter.  All callers changed.
	(hash_find_n): New interface.
	* hash.h: Prototype hash_find_n.
	* sb.c: Include as.h.
	(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
	(sb_scrub_and_add_sb): New interface.
	* sb.h: Prototype sb_scrub_and_add_sb.
	* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.

	* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
	reference to BFD_RELOC_ARM_GOT12 which is never generated.
	* config/tc-arm.c: Rewrite, adding Thumb-2 support.

gas/testsuite:
	* gas/arm/arm.exp: Convert all existing "gas_test" tests to
	"run_dump_test" tests.  Run more tests unconditionally.  Run new tests.
	* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
	* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
	* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
	Adjust to work as a dump test.
	* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
	* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
	* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
	New files.

	* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
	diagnostics that don't happen in the first pass anymore.

	* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
	* gas/arm/vfp-bad.l:
	Update expected diagnostics.
	* gas/arm/pic.d: Update expected reloc name.
	* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
	* gas/arm/r15-bad.s: Avoid two-argument mul.
	* gas/arm/req.s: Adjust comments.
	* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
	use of PC.

	* gas/arm/macro-1.d, gas/arm/macro1.s
	* gas/arm/t16-bad.l, gas/arm/t16-bad.s
	* gas/arm/tcompat.d, gas/arm/tcompat.s
	* gas/arm/tcompat2.d, gas/arm/tcompat2.s
	* gas/arm/thumb32.d, gas/arm/thumb32.s
	New test pair.

ld/testsuite:
	* ld-arm/mixed-app.d: Adjust expected disassembly a little.
This commit is contained in:
Zack Weinberg 2005-05-18 05:40:12 +00:00
parent 76ff342d25
commit c19d120533
65 changed files with 15482 additions and 14265 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
bfd/ChangeLog
View File

@ -1,3 +1,32 @@
2005-05-17 Zack Weinberg <zack@codesourcery.com>
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
2005-05-17 Daniel Jacobowitz <dan@codesourcery.com>
* elf.c (_bfd_elf_write_object_contents): Check for non-NULL

101
bfd/bfd-in2.h
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@ -2757,44 +2757,23 @@ not stored in the instruction. The 2nd lowest bit comes from a 1 bit
field in the instruction. */
BFD_RELOC_THUMB_PCREL_BLX,
/* These relocs are only used within the ARM assembler. They are not
(at present) written to any object files. */
BFD_RELOC_ARM_IMMEDIATE,
BFD_RELOC_ARM_ADRL_IMMEDIATE,
/* Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
The lowest bit must be zero and is not stored in the instruction.
Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
"nn" one smaller in all cases. Note further that BRANCH23
corresponds to R_ARM_THM_CALL. */
BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_PCREL_BRANCH9,
BFD_RELOC_THUMB_PCREL_BRANCH12,
BFD_RELOC_THUMB_PCREL_BRANCH20,
BFD_RELOC_THUMB_PCREL_BRANCH23,
BFD_RELOC_THUMB_PCREL_BRANCH25,
/* 12-bit immediate offset, used in ARM-format ldr and str instructions. */
BFD_RELOC_ARM_OFFSET_IMM,
BFD_RELOC_ARM_SHIFT_IMM,
BFD_RELOC_ARM_SMI,
BFD_RELOC_ARM_SWI,
BFD_RELOC_ARM_MULTI,
BFD_RELOC_ARM_CP_OFF_IMM,
BFD_RELOC_ARM_CP_OFF_IMM_S2,
BFD_RELOC_ARM_ADR_IMM,
BFD_RELOC_ARM_LDR_IMM,
BFD_RELOC_ARM_LITERAL,
BFD_RELOC_ARM_IN_POOL,
BFD_RELOC_ARM_OFFSET_IMM8,
BFD_RELOC_ARM_HWLITERAL,
BFD_RELOC_ARM_THUMB_ADD,
BFD_RELOC_ARM_THUMB_IMM,
BFD_RELOC_ARM_THUMB_SHIFT,
/* 5-bit immediate offset, used in Thumb-format ldr and str instructions. */
BFD_RELOC_ARM_THUMB_OFFSET,
BFD_RELOC_ARM_GOT12,
BFD_RELOC_ARM_GOT32,
BFD_RELOC_ARM_JUMP_SLOT,
BFD_RELOC_ARM_COPY,
BFD_RELOC_ARM_GLOB_DAT,
BFD_RELOC_ARM_PLT32,
BFD_RELOC_ARM_RELATIVE,
BFD_RELOC_ARM_GOTOFF,
BFD_RELOC_ARM_GOTPC,
BFD_RELOC_ARM_TLS_GD32,
BFD_RELOC_ARM_TLS_LDO32,
BFD_RELOC_ARM_TLS_LDM32,
BFD_RELOC_ARM_TLS_DTPOFF32,
BFD_RELOC_ARM_TLS_DTPMOD32,
BFD_RELOC_ARM_TLS_TPOFF32,
BFD_RELOC_ARM_TLS_IE32,
BFD_RELOC_ARM_TLS_LE32,
/* Pc-relative or absolute relocation depending on target. Used for
entries in .init_array sections. */
@ -2806,7 +2785,7 @@ entries in .init_array sections. */
/* Data segment base relative address. */
BFD_RELOC_ARM_SBREL32,
/* This reloc is used for References to RTTI dta from exception handling
/* This reloc is used for references to RTTI data from exception handling
tables. The actual definition depends on the target. It may be a
pc-relative or some form of GOT-indirect relocation. */
BFD_RELOC_ARM_TARGET2,
@ -2814,6 +2793,48 @@ pc-relative or some form of GOT-indirect relocation. */
/* 31-bit PC relative address. */
BFD_RELOC_ARM_PREL31,
/* Relocations for setting up GOTs and PLTs for shared libraries. */
BFD_RELOC_ARM_JUMP_SLOT,
BFD_RELOC_ARM_GLOB_DAT,
BFD_RELOC_ARM_GOT32,
BFD_RELOC_ARM_PLT32,
BFD_RELOC_ARM_RELATIVE,
BFD_RELOC_ARM_GOTOFF,
BFD_RELOC_ARM_GOTPC,
/* ARM thread-local storage relocations. */
BFD_RELOC_ARM_TLS_GD32,
BFD_RELOC_ARM_TLS_LDO32,
BFD_RELOC_ARM_TLS_LDM32,
BFD_RELOC_ARM_TLS_DTPOFF32,
BFD_RELOC_ARM_TLS_DTPMOD32,
BFD_RELOC_ARM_TLS_TPOFF32,
BFD_RELOC_ARM_TLS_IE32,
BFD_RELOC_ARM_TLS_LE32,
/* These relocs are only used within the ARM assembler. They are not
(at present) written to any object files. */
BFD_RELOC_ARM_IMMEDIATE,
BFD_RELOC_ARM_ADRL_IMMEDIATE,
BFD_RELOC_ARM_T32_IMMEDIATE,
BFD_RELOC_ARM_SHIFT_IMM,
BFD_RELOC_ARM_SMI,
BFD_RELOC_ARM_SWI,
BFD_RELOC_ARM_MULTI,
BFD_RELOC_ARM_CP_OFF_IMM,
BFD_RELOC_ARM_CP_OFF_IMM_S2,
BFD_RELOC_ARM_ADR_IMM,
BFD_RELOC_ARM_LDR_IMM,
BFD_RELOC_ARM_LITERAL,
BFD_RELOC_ARM_IN_POOL,
BFD_RELOC_ARM_OFFSET_IMM8,
BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM,
BFD_RELOC_ARM_HWLITERAL,
BFD_RELOC_ARM_THUMB_ADD,
BFD_RELOC_ARM_THUMB_IMM,
BFD_RELOC_ARM_THUMB_SHIFT,
/* Renesas / SuperH SH relocs. Not all of these appear in object files. */
BFD_RELOC_SH_PCDISP8BY2,
BFD_RELOC_SH_PCDISP12BY2,
@ -2906,12 +2927,6 @@ pc-relative or some form of GOT-indirect relocation. */
BFD_RELOC_SH_TLS_DTPOFF32,
BFD_RELOC_SH_TLS_TPOFF32,
/* Thumb 23-, 12- and 9-bit pc-relative branches. The lowest bit must
be zero and is not stored in the instruction. */
BFD_RELOC_THUMB_PCREL_BRANCH9,
BFD_RELOC_THUMB_PCREL_BRANCH12,
BFD_RELOC_THUMB_PCREL_BRANCH23,
/* ARC Cores relocs.
ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
not stored in the instruction. The high 20 bits are installed in bits 26

1040
bfd/elf32-arm.c
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File diff suppressed because it is too large Load Diff

60
bfd/libbfd.h
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@ -1152,30 +1152,22 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARM_PCREL_BRANCH",
"BFD_RELOC_ARM_PCREL_BLX",
"BFD_RELOC_THUMB_PCREL_BLX",
"BFD_RELOC_ARM_IMMEDIATE",
"BFD_RELOC_ARM_ADRL_IMMEDIATE",
"BFD_RELOC_THUMB_PCREL_BRANCH7",
"BFD_RELOC_THUMB_PCREL_BRANCH9",
"BFD_RELOC_THUMB_PCREL_BRANCH12",
"BFD_RELOC_THUMB_PCREL_BRANCH20",
"BFD_RELOC_THUMB_PCREL_BRANCH23",
"BFD_RELOC_THUMB_PCREL_BRANCH25",
"BFD_RELOC_ARM_OFFSET_IMM",
"BFD_RELOC_ARM_SHIFT_IMM",
"BFD_RELOC_ARM_SMI",
"BFD_RELOC_ARM_SWI",
"BFD_RELOC_ARM_MULTI",
"BFD_RELOC_ARM_CP_OFF_IMM",
"BFD_RELOC_ARM_CP_OFF_IMM_S2",
"BFD_RELOC_ARM_ADR_IMM",
"BFD_RELOC_ARM_LDR_IMM",
"BFD_RELOC_ARM_LITERAL",
"BFD_RELOC_ARM_IN_POOL",
"BFD_RELOC_ARM_OFFSET_IMM8",
"BFD_RELOC_ARM_HWLITERAL",
"BFD_RELOC_ARM_THUMB_ADD",
"BFD_RELOC_ARM_THUMB_IMM",
"BFD_RELOC_ARM_THUMB_SHIFT",
"BFD_RELOC_ARM_THUMB_OFFSET",
"BFD_RELOC_ARM_GOT12",
"BFD_RELOC_ARM_GOT32",
"BFD_RELOC_ARM_TARGET1",
"BFD_RELOC_ARM_ROSEGREL32",
"BFD_RELOC_ARM_SBREL32",
"BFD_RELOC_ARM_TARGET2",
"BFD_RELOC_ARM_PREL31",
"BFD_RELOC_ARM_JUMP_SLOT",
"BFD_RELOC_ARM_COPY",
"BFD_RELOC_ARM_GLOB_DAT",
"BFD_RELOC_ARM_GOT32",
"BFD_RELOC_ARM_PLT32",
"BFD_RELOC_ARM_RELATIVE",
"BFD_RELOC_ARM_GOTOFF",
@ -1188,11 +1180,26 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARM_TLS_TPOFF32",
"BFD_RELOC_ARM_TLS_IE32",
"BFD_RELOC_ARM_TLS_LE32",
"BFD_RELOC_ARM_TARGET1",
"BFD_RELOC_ARM_ROSEGREL32",
"BFD_RELOC_ARM_SBREL32",
"BFD_RELOC_ARM_TARGET2",
"BFD_RELOC_ARM_PREL31",
"BFD_RELOC_ARM_IMMEDIATE",
"BFD_RELOC_ARM_ADRL_IMMEDIATE",
"BFD_RELOC_ARM_T32_IMMEDIATE",
"BFD_RELOC_ARM_SHIFT_IMM",
"BFD_RELOC_ARM_SMI",
"BFD_RELOC_ARM_SWI",
"BFD_RELOC_ARM_MULTI",
"BFD_RELOC_ARM_CP_OFF_IMM",
"BFD_RELOC_ARM_CP_OFF_IMM_S2",
"BFD_RELOC_ARM_ADR_IMM",
"BFD_RELOC_ARM_LDR_IMM",
"BFD_RELOC_ARM_LITERAL",
"BFD_RELOC_ARM_IN_POOL",
"BFD_RELOC_ARM_OFFSET_IMM8",
"BFD_RELOC_ARM_T32_OFFSET_U8",
"BFD_RELOC_ARM_T32_OFFSET_IMM",
"BFD_RELOC_ARM_HWLITERAL",
"BFD_RELOC_ARM_THUMB_ADD",
"BFD_RELOC_ARM_THUMB_IMM",
"BFD_RELOC_ARM_THUMB_SHIFT",
"BFD_RELOC_SH_PCDISP8BY2",
"BFD_RELOC_SH_PCDISP12BY2",
"BFD_RELOC_SH_IMM3",
@ -1283,9 +1290,6 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_SH_TLS_DTPMOD32",
"BFD_RELOC_SH_TLS_DTPOFF32",
"BFD_RELOC_SH_TLS_TPOFF32",
"BFD_RELOC_THUMB_PCREL_BRANCH9",
"BFD_RELOC_THUMB_PCREL_BRANCH12",
"BFD_RELOC_THUMB_PCREL_BRANCH23",
"BFD_RELOC_ARC_B22_PCREL",
"BFD_RELOC_ARC_B26",
"BFD_RELOC_D10V_10_PCREL_R",

165
bfd/reloc.c
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@ -2635,12 +2635,102 @@ ENUMDOC
Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
not stored in the instruction. The 2nd lowest bit comes from a 1 bit
field in the instruction.
ENUM
BFD_RELOC_THUMB_PCREL_BRANCH7
ENUMX
BFD_RELOC_THUMB_PCREL_BRANCH9
ENUMX
BFD_RELOC_THUMB_PCREL_BRANCH12
ENUMX
BFD_RELOC_THUMB_PCREL_BRANCH20
ENUMX
BFD_RELOC_THUMB_PCREL_BRANCH23
ENUMX
BFD_RELOC_THUMB_PCREL_BRANCH25
ENUMDOC
Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
The lowest bit must be zero and is not stored in the instruction.
Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
"nn" one smaller in all cases. Note further that BRANCH23
corresponds to R_ARM_THM_CALL.
ENUM
BFD_RELOC_ARM_OFFSET_IMM
ENUMDOC
12-bit immediate offset, used in ARM-format ldr and str instructions.
ENUM
BFD_RELOC_ARM_THUMB_OFFSET
ENUMDOC
5-bit immediate offset, used in Thumb-format ldr and str instructions.
ENUM
BFD_RELOC_ARM_TARGET1
ENUMDOC
Pc-relative or absolute relocation depending on target. Used for
entries in .init_array sections.
ENUM
BFD_RELOC_ARM_ROSEGREL32
ENUMDOC
Read-only segment base relative address.
ENUM
BFD_RELOC_ARM_SBREL32
ENUMDOC
Data segment base relative address.
ENUM
BFD_RELOC_ARM_TARGET2
ENUMDOC
This reloc is used for references to RTTI data from exception handling
tables. The actual definition depends on the target. It may be a
pc-relative or some form of GOT-indirect relocation.
ENUM
BFD_RELOC_ARM_PREL31
ENUMDOC
31-bit PC relative address.
ENUM
BFD_RELOC_ARM_JUMP_SLOT
ENUMX
BFD_RELOC_ARM_GLOB_DAT
ENUMX
BFD_RELOC_ARM_GOT32
ENUMX
BFD_RELOC_ARM_PLT32
ENUMX
BFD_RELOC_ARM_RELATIVE
ENUMX
BFD_RELOC_ARM_GOTOFF
ENUMX
BFD_RELOC_ARM_GOTPC
ENUMDOC
Relocations for setting up GOTs and PLTs for shared libraries.
ENUM
BFD_RELOC_ARM_TLS_GD32
ENUMX
BFD_RELOC_ARM_TLS_LDO32
ENUMX
BFD_RELOC_ARM_TLS_LDM32
ENUMX
BFD_RELOC_ARM_TLS_DTPOFF32
ENUMX
BFD_RELOC_ARM_TLS_DTPMOD32
ENUMX
BFD_RELOC_ARM_TLS_TPOFF32
ENUMX
BFD_RELOC_ARM_TLS_IE32
ENUMX
BFD_RELOC_ARM_TLS_LE32
ENUMDOC
ARM thread-local storage relocations.
ENUM
BFD_RELOC_ARM_IMMEDIATE
ENUMX
BFD_RELOC_ARM_ADRL_IMMEDIATE
ENUMX
BFD_RELOC_ARM_OFFSET_IMM
BFD_RELOC_ARM_T32_IMMEDIATE
ENUMX
BFD_RELOC_ARM_SHIFT_IMM
ENUMX
@ -2663,6 +2753,10 @@ ENUMX
BFD_RELOC_ARM_IN_POOL
ENUMX
BFD_RELOC_ARM_OFFSET_IMM8
ENUMX
BFD_RELOC_ARM_T32_OFFSET_U8
ENUMX
BFD_RELOC_ARM_T32_OFFSET_IMM
ENUMX
BFD_RELOC_ARM_HWLITERAL
ENUMX
@ -2671,68 +2765,9 @@ ENUMX
BFD_RELOC_ARM_THUMB_IMM
ENUMX
BFD_RELOC_ARM_THUMB_SHIFT
ENUMX
BFD_RELOC_ARM_THUMB_OFFSET
ENUMX
BFD_RELOC_ARM_GOT12
ENUMX
BFD_RELOC_ARM_GOT32
ENUMX
BFD_RELOC_ARM_JUMP_SLOT
ENUMX
BFD_RELOC_ARM_COPY
ENUMX
BFD_RELOC_ARM_GLOB_DAT
ENUMX
BFD_RELOC_ARM_PLT32
ENUMX
BFD_RELOC_ARM_RELATIVE
ENUMX
BFD_RELOC_ARM_GOTOFF
ENUMX
BFD_RELOC_ARM_GOTPC
ENUMX
BFD_RELOC_ARM_TLS_GD32
ENUMX
BFD_RELOC_ARM_TLS_LDO32
ENUMX
BFD_RELOC_ARM_TLS_LDM32
ENUMX
BFD_RELOC_ARM_TLS_DTPOFF32
ENUMX
BFD_RELOC_ARM_TLS_DTPMOD32
ENUMX
BFD_RELOC_ARM_TLS_TPOFF32
ENUMX
BFD_RELOC_ARM_TLS_IE32
ENUMX
BFD_RELOC_ARM_TLS_LE32
ENUMDOC
These relocs are only used within the ARM assembler. They are not
(at present) written to any object files.
ENUM
BFD_RELOC_ARM_TARGET1
ENUMDOC
Pc-relative or absolute relocation depending on target. Used for
entries in .init_array sections.
ENUM
BFD_RELOC_ARM_ROSEGREL32
ENUMDOC
Read-only segment base relative address.
ENUM
BFD_RELOC_ARM_SBREL32
ENUMDOC
Data segment base relative address.
ENUM
BFD_RELOC_ARM_TARGET2
ENUMDOC
This reloc is used for References to RTTI dta from exception handling
tables. The actual definition depends on the target. It may be a
pc-relative or some form of GOT-indirect relocation.
ENUM
BFD_RELOC_ARM_PREL31
ENUMDOC
31-bit PC relative address.
ENUM
BFD_RELOC_SH_PCDISP8BY2
@ -2917,16 +2952,6 @@ ENUMX
ENUMDOC
Renesas / SuperH SH relocs. Not all of these appear in object files.
ENUM
BFD_RELOC_THUMB_PCREL_BRANCH9
ENUMX
BFD_RELOC_THUMB_PCREL_BRANCH12
ENUMX
BFD_RELOC_THUMB_PCREL_BRANCH23
ENUMDOC
Thumb 23-, 12- and 9-bit pc-relative branches. The lowest bit must
be zero and is not stored in the instruction.
ENUM
BFD_RELOC_ARC_B22_PCREL
ENUMDOC

15
gas/ChangeLog
View File

@ -1,3 +1,18 @@
2005-05-17 Zack Weinberg <zack@codesourcery.com>
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
2005-05-17 Daniel Jacobowitz <dan@codesourcery.com>
* doc/Makefile.am (gasver.texi): Don't use $<.

23614
gas/config/tc-arm.c
View File

File diff suppressed because it is too large Load Diff

1
gas/config/tc-arm.h
View File

@ -140,7 +140,6 @@ struct fix;
#define TC_FORCE_RELOCATION_LOCAL(FIX) \
(!(FIX)->fx_pcrel \
|| (FIX)->fx_plt \
|| (FIX)->fx_r_type == BFD_RELOC_ARM_GOT12 \
|| (FIX)->fx_r_type == BFD_RELOC_ARM_GOT32 \
|| (FIX)->fx_r_type == BFD_RELOC_32 \
|| TC_FORCE_RELOCATION (FIX))

47
gas/hash.c
View File

@ -150,19 +150,13 @@ hash_die (struct hash_control *table)
Each time we look up a string, we move it to the start of the list
for its hash code, to take advantage of referential locality. */
static struct hash_entry *hash_lookup (struct hash_control *,
const char *,
struct hash_entry ***,
unsigned long *);
static struct hash_entry *
hash_lookup (struct hash_control *table, const char *key,
hash_lookup (struct hash_control *table, const char *key, size_t len,
struct hash_entry ***plist, unsigned long *phash)
{
register unsigned long hash;
unsigned int len;
register const unsigned char *s;
register unsigned int c;
unsigned long hash;
size_t n;
unsigned int c;
unsigned int index;
struct hash_entry **list;
struct hash_entry *p;
@ -173,13 +167,11 @@ hash_lookup (struct hash_control *table, const char *key,
#endif
hash = 0;
len = 0;
s = (const unsigned char *) key;
while ((c = *s++) != '\0')
for (n = 0; n < len; n++)
{
c = key[n];
hash += c + (c << 17);
hash ^= hash >> 2;
++len;
}
hash += len + (len << 17);
hash ^= hash >> 2;
@ -206,7 +198,7 @@ hash_lookup (struct hash_control *table, const char *key,
++table->string_compares;
#endif
if (strcmp (p->string, key) == 0)
if (strncmp (p->string, key, len) == 0 && p->string[len] == '\0')
{
if (prev != NULL)
{
@ -237,7 +229,7 @@ hash_insert (struct hash_control *table, const char *key, PTR value)
struct hash_entry **list;
unsigned long hash;
p = hash_lookup (table, key, &list, &hash);
p = hash_lookup (table, key, strlen (key), &list, &hash);
if (p != NULL)
return "exists";
@ -267,7 +259,7 @@ hash_jam (struct hash_control *table, const char *key, PTR value)
struct hash_entry **list;
unsigned long hash;
p = hash_lookup (table, key, &list, &hash);
p = hash_lookup (table, key, strlen (key), &list, &hash);
if (p != NULL)
{
#ifdef HASH_STATISTICS
@ -304,7 +296,7 @@ hash_replace (struct hash_control *table, const char *key, PTR value)
struct hash_entry *p;
PTR ret;
p = hash_lookup (table, key, NULL, NULL);
p = hash_lookup (table, key, strlen (key), NULL, NULL);
if (p == NULL)
return NULL;
@ -327,7 +319,22 @@ hash_find (struct hash_control *table, const char *key)
{
struct hash_entry *p;
p = hash_lookup (table, key, NULL, NULL);
p = hash_lookup (table, key, strlen (key), NULL, NULL);
if (p == NULL)
return NULL;
return p->data;
}
/* As hash_find, but KEY is of length LEN and is not guaranteed to be
NUL-terminated. */
PTR
hash_find_n (struct hash_control *table, const char *key, size_t len)
{
struct hash_entry *p;
p = hash_lookup (table, key, len, NULL, NULL);
if (p == NULL)
return NULL;
@ -343,7 +350,7 @@ hash_delete (struct hash_control *table, const char *key)
struct hash_entry *p;
struct hash_entry **list;
p = hash_lookup (table, key, &list, NULL);
p = hash_lookup (table, key, strlen (key), &list, NULL);
if (p == NULL)
return NULL;

5
gas/hash.h
View File

@ -63,6 +63,11 @@ extern PTR hash_replace (struct hash_control *, const char *key,
extern PTR hash_find (struct hash_control *, const char *key);
/* As hash_find, but KEY is of length LEN and is not guaranteed to be
NUL-terminated. */
extern PTR hash_find_n (struct hash_control *, const char *key, size_t len);
/* Delete an entry from a hash table. This returns the value stored
for that entry, or NULL if there is no such entry. */

2
gas/input-scrub.c
View File

@ -279,7 +279,7 @@ input_scrub_include_sb (sb *from, char *position, int is_expansion)
/* Add the sentinel required by read.c. */
sb_add_char (&from_sb, '\n');
}
sb_add_sb (&from_sb, from);
sb_scrub_and_add_sb (&from_sb, from);
sb_index = 1;
/* These variables are reset by input_scrub_push. Restore them

33
gas/sb.c
View File

@ -33,6 +33,7 @@
#endif
#include "libiberty.h"
#include "sb.h"
#include "as.h"
/* These routines are about manipulating strings.
@ -115,6 +116,38 @@ sb_add_sb (sb *ptr, sb *s)
ptr->len += s->len;
}
/* Helper for sb_scrub_and_add_sb. */
static sb *sb_to_scrub;
static char *scrub_position;
static int
scrub_from_sb (char *buf, int buflen)
{
int copy;
copy = sb_to_scrub->len - (scrub_position - sb_to_scrub->ptr);
if (copy > buflen)
copy = buflen;
memcpy (buf, scrub_position, copy);
scrub_position += copy;
return copy;
}
/* Run the sb at s through do_scrub_chars and add the result to the sb
at ptr. */
void
sb_scrub_and_add_sb (sb *ptr, sb *s)
{
sb_to_scrub = s;
scrub_position = s->ptr;
sb_check (ptr, s->len);
ptr->len += do_scrub_chars (scrub_from_sb, ptr->ptr + ptr->len, s->len);
sb_to_scrub = 0;
scrub_position = 0;
}
/* Make sure that the sb at ptr has room for another len characters,
and grow it if it doesn't. */

1
gas/sb.h
View File

@ -81,6 +81,7 @@ sb_list_vector;
extern void sb_new (sb *);
extern void sb_kill (sb *);
extern void sb_add_sb (sb *, sb *);
extern void sb_scrub_and_add_sb (sb *, sb *);
extern void sb_reset (sb *);
extern void sb_add_char (sb *, int);
extern void sb_add_string (sb *, const char *);

33
gas/testsuite/ChangeLog
View File

@ -1,3 +1,36 @@
2005-05-17 Zack Weinberg <zack@codesourcery.com>
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
2005-05-17 Jan Beulich <jbeulich@novell.com>
* gas/mmix/err-byte1.s: Adjust expected error text on line 10.

36
gas/testsuite/gas/arm/arch4t.d Normal file
View File

@ -0,0 +1,36 @@
# name: ARM architecture 4t instructions
# as: -march=armv4t
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
0+00 <[^>]+> e12fff10 ? bx r0
0+04 <[^>]+> 012fff11 ? bxeq r1
0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+>
0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\]
0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\]
0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]!
0+18 <[^>]+> 011510d3 ? ldreqsb r1, \[r5, -r3\]
0+1c <[^>]+> 109620b7 ? ldrneh r2, \[r6\], r7
0+20 <[^>]+> 309720f8 ? ldrccsh r2, \[r7\], r8
0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\]
0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\]
0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\]
0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+>
0+34 <[^>]+> 11c330b0 ? strneh r3, \[r3\]
0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 ; 0x2
0+3c <[^>]+> e121f003 ? msr CPSR_c, r3
0+40 <[^>]+> e122f004 ? msr CPSR_x, r4
0+44 <[^>]+> e124f005 ? msr CPSR_s, r5
0+48 <[^>]+> e128f006 ? msr CPSR_f, r6
0+4c <[^>]+> e129f007 ? msr CPSR_fc, r7
0+50 <[^>]+> e368f004 ? msr SPSR_f, #4 ; 0x4
0+54 <[^>]+> e161f008 ? msr SPSR_c, r8
0+58 <[^>]+> e162f009 ? msr SPSR_x, r9
0+5c <[^>]+> e164f00a ? msr SPSR_s, sl
0+60 <[^>]+> e168f00b ? msr SPSR_f, fp
0+64 <[^>]+> e169f00c ? msr SPSR_fc, ip
0+68 <[^>]+> e1a00000 ? nop \(mov r0,r0\)
0+6c <[^>]+> e1a00000 ? nop \(mov r0,r0\)

9
gas/testsuite/gas/arm/arch4t.s
View File

@ -1,6 +1,6 @@
.text
.align 0
.text
.align 0
l:
bx r0
bxeq r1
@ -33,3 +33,6 @@ foo:
msr SPSR_f, r11
msr SPSR_all, r12
bar:
@ section padding for a.out's benefit
nop
nop

24
gas/testsuite/gas/arm/arch6zk.d
View File

@ -6,21 +6,21 @@
Disassembly of section .text:
0+000 <[^>]*> f57ff01f ? clrex
0+004 <[^>]*> e1dc3f9f ? ldrexb r3, \[ip\]
0+008 <[^>]*> 11d3cf9f ? ldrexbne ip, \[r3\]
0+00c <[^>]*> e1bc3f9f ? ldrexd r3, \[ip\]
0+010 <[^>]*> 11b3cf9f ? ldrexdne ip, \[r3\]
0+014 <[^>]*> e1fc3f9f ? ldrexh r3, \[ip\]
0+018 <[^>]*> 11f3cf9f ? ldrexhne ip, \[r3\]
0+004 <[^>]*> e1dc4f9f ? ldrexb r4, \[ip\]
0+008 <[^>]*> 11d4cf9f ? ldrexbne ip, \[r4\]
0+00c <[^>]*> e1bc4f9f ? ldrexd r4, \[ip\]
0+010 <[^>]*> 11b4cf9f ? ldrexdne ip, \[r4\]
0+014 <[^>]*> e1fc4f9f ? ldrexh r4, \[ip\]
0+018 <[^>]*> 11f4cf9f ? ldrexhne ip, \[r4\]
0+01c <[^>]*> e320f080 ? nop \{128\}
0+020 <[^>]*> 1320f07f ? nopne \{127\}
0+024 <[^>]*> e320f004 ? sev
0+028 <[^>]*> e1c73f9c ? strexb r3, ip, \[r7\]
0+02c <[^>]*> 11c8cf93 ? strexbne ip, r3, \[r8\]
0+030 <[^>]*> e1a73f9c ? strexd r3, ip, \[r7\]
0+034 <[^>]*> 11a8cf93 ? strexdne ip, r3, \[r8\]
0+038 <[^>]*> e1e73f9c ? strexh r3, ip, \[r7\]
0+03c <[^>]*> 11e8cf93 ? strexhne ip, r3, \[r8\]
0+028 <[^>]*> e1c74f9c ? strexb r4, ip, \[r7\]
0+02c <[^>]*> 11c8cf94 ? strexbne ip, r4, \[r8\]
0+030 <[^>]*> e1a74f9c ? strexd r4, ip, \[r7\]
0+034 <[^>]*> 11a8cf94 ? strexdne ip, r4, \[r8\]
0+038 <[^>]*> e1e74f9c ? strexh r4, ip, \[r7\]
0+03c <[^>]*> 11e8cf94 ? strexhne ip, r4, \[r8\]
0+040 <[^>]*> e320f002 ? wfe
0+044 <[^>]*> e320f003 ? wfi
0+048 <[^>]*> e320f001 ? yield

28
gas/testsuite/gas/arm/arch6zk.s
View File

@ -4,21 +4,21 @@
label:
# ARMV6K instructions
clrex
ldrexb r3, [r12]
ldrexbne r12, [r3]
ldrexd r3, [r12]
ldrexdne r12, [r3]
ldrexh r3, [r12]
ldrexhne r12, [r3]
nop {128}
nopne {127}
ldrexb r4, [r12]
ldrexbne r12, [r4]
ldrexd r4, [r12]
ldrexdne r12, [r4]
ldrexh r4, [r12]
ldrexhne r12, [r4]
nop {128}
nopne {127}
sev
strexb r3, r12, [r7]
strexbne r12, r3, [r8]
strexd r3, r12, [r7]
strexdne r12, r3, [r8]
strexh r3, r12, [r7]
strexhne r12, r3, [r8]
strexb r4, r12, [r7]
strexbne r12, r4, [r8]
strexd r4, r12, [r7]
strexdne r12, r4, [r8]
strexh r4, r12, [r7]
strexhne r12, r4, [r8]
wfe
wfi
yield

50
gas/testsuite/gas/arm/arm.exp
View File

@ -28,14 +28,13 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
run_dump_test "copro"
}
gas_test "arm3.s" "-mcpu=arm3" $stdoptlist "Arm 3 instructions"
gas_test "arm6.s" "-mcpu=arm6" $stdoptlist "Arm 6 instructions"
gas_test "arm7dm.s" "-mcpu=arm7dm" $stdoptlist "Arm 7DM instructions"
gas_test "arch4t.s" "-march=armv4t" $stdoptlist "Arm architecture 4t instructions"
gas_test "immed.s" "" $stdoptlist "immediate expressions"
gas_test "float.s" "-mcpu=arm7tdmi -mfpu=fpa" $stdoptlist "Core floating point instructions"
gas_test "offset.s" "" $stdoptlist "OFFSET_IMM regression"
run_dump_test "arm3"
run_dump_test "arm6"
run_dump_test "arm7dm"
run_dump_test "arch4t"
run_dump_test "immed"
run_dump_test "float"
run_dump_test "offset"
run_dump_test "armv1"
run_dump_test "arch5tej"
run_dump_test "fpa-monadic"
@ -53,12 +52,18 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
run_dump_test "thumbv6"
run_dump_test "thumbv6k"
run_dump_test "arch6zk"
run_dump_test "tcompat"
run_dump_test "tcompat2"
run_dump_test "iwmmxt"
run_dump_test "macro1"
run_errors_test "vfp-bad" "-mfpu=vfp" "VFP errors"
run_errors_test "req" "-mcpu=arm7m" ".req errors"
run_errors_test "armv1-bad" "-mcpu=arm7m" "ARM v1 errors"
run_errors_test "r15-bad" "" "Invalid use of r15 errors"
run_errors_test "archv6t2-bad" "-march=armv6t2" "Invalid V6T2 instructions"
run_errors_test "t16-bad" "-march=armv6k" "Valid ARM, invalid Thumb"
run_errors_test "iwmmxt-bad" "-mcpu=iwmmxt" "iWMMXt errors"
if {[istarget *-*-*coff] || [istarget *-*-pe] || [istarget *-*-wince] ||
[istarget *-*-*aout*] || [istarget *-*-netbsd] || [istarget *-*-riscix*]} then {
@ -70,29 +75,20 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
run_dump_test "pic"
run_dump_test "mapping"
gas_test "bignum1.s" "" $stdoptlist "bignums"
run_dump_test "bignum1"
run_dump_test "unwind"
run_dump_test "tls"
}
# The arm-aout port does not support Thumb branch relocations.
if {! [istarget arm*-*-aout] && ![istarget arm-*-pe]} then {
# The arm-aout port does not support Thumb mode.
gas_test "thumb.s" "-mcpu=arm7t" $stdoptlist "Thumb instructions"
run_dump_test "thumb"
run_dump_test "thumb32"
}
# Not all arm targets are bi-endian, so only run this test on ones
# we know that are. FIXME: We should probably also key off armeb/armel.
if [istarget *-*-pe] {
run_dump_test "le-fpconst"
}
}
# Not all arm targets are bi-endian, so only run this test on ones
# we know that are. FIXME: We should probably also key off armeb/armel.
if [istarget arm-*-pe] {
run_dump_test "le-fpconst"
# Since big-endian numbers have the normal format, this doesn't exist.
#run_dump_test "be-fpconst"
}
if [istarget xscale-*] {
run_dump_test "iwmmxt"
run_errors_test "iwmmxt-bad" "-mcpu=iwmmxt" "iWMMXt errors"
}

11
gas/testsuite/gas/arm/arm3.d Normal file
View File

@ -0,0 +1,11 @@
# name: ARM 3 instructions
# as: -mcpu=arm3
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
0+0 <[^>]*> e1080091 ? swp r0, r1, \[r8\]
0+4 <[^>]*> e1432093 ? swpb r2, r3, \[r3\]
0+8 <[^>]*> a1444091 ? swpgeb r4, r1, \[r4\]
0+c <[^>]*> e1a00000 ? nop \(mov r0,r0\)

7
gas/testsuite/gas/arm/arm3.s
View File

@ -1,6 +1,7 @@
.text
.align 0
.text
.align 0
l:
swp r0, r1, [r8]
swpb r2, r3, [r3]
swpgeb r4, r1, [r4]
nop

19
gas/testsuite/gas/arm/arm6.d Normal file
View File

@ -0,0 +1,19 @@
# name: ARM 6 instructions
# as: -mcpu=arm6
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
0+00 <[^>]+> e10f8000 ? mrs r8, CPSR
0+04 <[^>]+> e14f2000 ? mrs r2, SPSR
0+08 <[^>]+> e129f001 ? msr CPSR_fc, r1
0+0c <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000
0+10 <[^>]+> e168f008 ? msr SPSR_f, r8
0+14 <[^>]+> e169f009 ? msr SPSR_fc, r9
0+18 <[^>]+> e10f8000 ? mrs r8, CPSR
0+1c <[^>]+> e14f2000 ? mrs r2, SPSR
0+20 <[^>]+> e129f001 ? msr CPSR_fc, r1
0+24 <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000
0+28 <[^>]+> e168f008 ? msr SPSR_f, r8
0+2c <[^>]+> e169f009 ? msr SPSR_fc, r9

7
gas/testsuite/gas/arm/arm6.s
View File

@ -1,6 +1,6 @@
.text
.align 0
.text
.align 0
l:
mrs r8, cpsr
mrs r2, spsr
@ -16,4 +16,3 @@
msrne CPSR_flg, #0xf0000000
msr SPSR_flg, r8
msr SPSR_all, r9

19
gas/testsuite/gas/arm/arm7dm.d Normal file
View File

@ -0,0 +1,19 @@
# name: ARM 7DM instructions
# as: -mcpu=arm7dm
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
0+00 <[^>]+> e0c10392 ? smull r0, r1, r2, r3
0+04 <[^>]+> e0810392 ? umull r0, r1, r2, r3
0+08 <[^>]+> e0e10392 ? smlal r0, r1, r2, r3
0+0c <[^>]+> e0a10394 ? umlal r0, r1, r4, r3
0+10 <[^>]+> 10c10493 ? smullne r0, r1, r3, r4
0+14 <[^>]+> e0d01b99 ? smulls r1, r0, r9, fp
0+18 <[^>]+> 00b92994 ? umlaleqs r2, r9, r4, r9
0+1c <[^>]+> a0eaee98 ? smlalge lr, sl, r8, lr
0+20 <[^>]+> e322f000 ? msr CPSR_x, #0 ; 0x0
0+24 <[^>]+> e1a00000 ? nop \(mov r0,r0\)
0+28 <[^>]+> e1a00000 ? nop \(mov r0,r0\)
0+2c <[^>]+> e1a00000 ? nop \(mov r0,r0\)

14
gas/testsuite/gas/arm/arm7dm.s
View File

@ -1,6 +1,6 @@
.text
.align 0
.text
.align 0
l:
smull r0, r1, r2, r3
umull r0, r1, r2, r3
smlal r0, r1, r2, r3
@ -11,4 +11,10 @@
umlaleqs r2, r9, r4, r9
smlalge r14, r10, r8, r14
msr CPSR_x, #0 @ This used to be illegal, but rev 2 of the ARM ARM allows it.
@ This used to be illegal, but rev 2 of the ARM ARM allows it.
msr CPSR_x, #0
@ padding for a.out's sake
nop
nop
nop

15
gas/testsuite/gas/arm/armv1-bad.l
View File

@ -1,12 +1,9 @@
[^:]*: Assembler messages:
[^:]*:4: Error: invalid pseudo operation -- `str r0,=0x00ff0000'
[^:]*:5: Error: bad expression -- `ldr r0,{r1}'
[^:]*:6: Error: address offset too large -- `ldr r0,\[r1,#4096\]'
[^:]*:7: Error: address offset too large -- `ldr r0,\[r1,#-4096\]'
[^:]*:8: Error: invalid constant -- `mov r0,#0x1ff'
[^:]*:9: Error: bad instruction `cmpl r0,r0'
[^:]*:10: Error: selected processor does not support `strh r0,\[r1\]'
[^:]*:11: Warning: writeback of base register is UNPREDICTABLE
[^:]*:12: Warning: writeback of base register when in register list is UNPREDICTABLE
[^:]*:13: Warning: writeback of base register is UNPREDICTABLE
[^:]*:15: Warning: if writeback register is in list, it must be the lowest reg in the list
[^:]*:6: Error: bad instruction `cmpl r0,r0'
[^:]*:7: Error: selected processor does not support `strh r0,\[r1\]'
[^:]*:8: Warning: writeback of base register is UNPREDICTABLE
[^:]*:9: Warning: writeback of base register when in register list is UNPREDICTABLE
[^:]*:10: Warning: writeback of base register is UNPREDICTABLE
[^:]*:12: Warning: if writeback register is in list, it must be the lowest reg in the list

3
gas/testsuite/gas/arm/armv1-bad.s
View File

@ -3,9 +3,6 @@
entry:
str r0, =0x00ff0000
ldr r0, {r1}
ldr r0, [r1, #4096]
ldr r0, [r1, #-4096]
mov r0, #0x1ff
cmpl r0, r0
strh r0, [r1]
ldmfa r4!, {r8, r9}^

8
gas/testsuite/gas/arm/bignum1.d Normal file
View File

@ -0,0 +1,8 @@
# name: bignums
# as:
# objdump: --full-contents
.*: +file format .*arm.*
Contents of section .data:
0000 [08]0000000 000000[08]0 11111111 11111111 \.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.

2
gas/testsuite/gas/arm/bignum1.s
View File

@ -1 +1,3 @@
.data
.8byte -9223372036854775808
.8byte 1229782938247303441

131
gas/testsuite/gas/arm/float.d Normal file
View File

@ -0,0 +1,131 @@
# name: Core floating point instructions
# as: -mcpu=arm7tdmi -mfpu=fpa
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
0+000 <[^>]+> ee088101 ? mvfe f0, f1
0+004 <[^>]+> 0e08b105 ? mvfeqe f3, f5
0+008 <[^>]+> 0e00c189 ? mvfeqd f4, #1\.0
0+00c <[^>]+> ee00c107 ? mvfs f4, f7
0+010 <[^>]+> ee008121 ? mvfsp f0, f1
0+014 <[^>]+> ee00b1c4 ? mvfdm f3, f4
0+018 <[^>]+> ee08f167 ? mvfez f7, f7
0+01c <[^>]+> ee09010a ? adfe f0, f1, #2\.0
0+020 <[^>]+> 0e0a110e ? adfeqe f1, f2, #0\.5
0+024 <[^>]+> ee043145 ? adfsm f3, f4, f5
0+028 <[^>]+> ee20018a ? sufd f0, f0, #2\.0
0+02c <[^>]+> ee22110f ? sufs f1, f2, #10\.0
0+030 <[^>]+> 1e2c3165 ? sufneez f3, f4, f5
0+034 <[^>]+> ee311108 ? rsfs f1, f1, #0\.0
0+038 <[^>]+> ee3031ad ? rsfdp f3, f0, #5\.0
0+03c <[^>]+> de367180 ? rsfled f7, f6, f0
0+040 <[^>]+> ee100180 ? mufd f0, f0, f0
0+044 <[^>]+> ee1a116b ? mufez f1, f2, #3\.0
0+048 <[^>]+> ee10010c ? mufs f0, f0, #4\.0
0+04c <[^>]+> ee400189 ? dvfd f0, f0, #1\.0
0+050 <[^>]+> ee49016f ? dvfez f0, f1, #10\.0
0+054 <[^>]+> 4e443145 ? dvfmism f3, f4, f5
0+058 <[^>]+> ee59010f ? rdfe f0, f1, #10\.0
0+05c <[^>]+> ee573109 ? rdfs f3, f7, #1\.0
0+060 <[^>]+> 3e5441a3 ? rdfccdp f4, f4, f3
0+064 <[^>]+> ee620183 ? powd f0, f2, f3
0+068 <[^>]+> ee63110f ? pows f1, f3, #10\.0
0+06c <[^>]+> 2e6f4169 ? powcsez f4, f7, #1\.0
0+070 <[^>]+> ee767107 ? rpws f7, f6, f7
0+074 <[^>]+> 0e710182 ? rpweqd f0, f1, f2
0+078 <[^>]+> ee7a2143 ? rpwem f2, f2, f3
0+07c <[^>]+> ee82118b ? rmfd f1, f2, #3\.0
0+080 <[^>]+> 6e843104 ? rmfvss f3, f4, f4
0+084 <[^>]+> ee8f4120 ? rmfep f4, f7, f0
0+088 <[^>]+> ee910102 ? fmls f0, f1, f2
0+08c <[^>]+> 0e931105 ? fmleqs f1, f3, f5
0+090 <[^>]+> 5e964160 ? fmlplsz f4, f6, f0
0+094 <[^>]+> eea3110f ? fdvs f1, f3, #10\.0
0+098 <[^>]+> eea10122 ? fdvsp f0, f1, f2
0+09c <[^>]+> 2ea44144 ? fdvcssm f4, f4, f4
0+0a0 <[^>]+> eeb11109 ? frds f1, f1, #1\.0
0+0a4 <[^>]+> ceb12100 ? frdgts f2, f1, f0
0+0a8 <[^>]+> ceb44165 ? frdgtsz f4, f4, f5
0+0ac <[^>]+> eec10182 ? pold f0, f1, f2
0+0b0 <[^>]+> eec6416b ? polsz f4, f6, #3\.0
0+0b4 <[^>]+> 0ece5107 ? poleqe f5, f6, f7
0+0b8 <[^>]+> ee108101 ? mnfs f0, f1
0+0bc <[^>]+> ee10818b ? mnfd f0, #3\.0
0+0c0 <[^>]+> ee18816c ? mnfez f0, #4\.0
0+0c4 <[^>]+> 0e188165 ? mnfeqez f0, f5
0+0c8 <[^>]+> ee108124 ? mnfsp f0, f4
0+0cc <[^>]+> ee1091c7 ? mnfdm f1, f7
0+0d0 <[^>]+> ee208181 ? absd f0, f1
0+0d4 <[^>]+> ee20912b ? abssp f1, #3\.0
0+0d8 <[^>]+> 0e28c105 ? abseqe f4, f5
0+0dc <[^>]+> ee309102 ? rnds f1, f2
0+0e0 <[^>]+> ee30b184 ? rndd f3, f4
0+0e4 <[^>]+> 0e38e16c ? rndeqez f6, #4\.0
0+0e8 <[^>]+> ee40d105 ? sqts f5, f5
0+0ec <[^>]+> ee40e1a6 ? sqtdp f6, f6
0+0f0 <[^>]+> 5e48f166 ? sqtplez f7, f6
0+0f4 <[^>]+> ee50810f ? logs f0, #10\.0
0+0f8 <[^>]+> ee58810f ? loge f0, #10\.0
0+0fc <[^>]+> 1e5081e1 ? lognedz f0, f1
0+100 <[^>]+> ee689102 ? lgne f1, f2
0+104 <[^>]+> ee6091e3 ? lgndz f1, f3
0+108 <[^>]+> 7e60b104 ? lgnvcs f3, f4
0+10c <[^>]+> ee709103 ? exps f1, f3
0+110 <[^>]+> ee78b14f ? expem f3, #10\.0
0+114 <[^>]+> 5e70e187 ? exppld f6, f7
0+118 <[^>]+> ee808181 ? sind f0, f1
0+11c <[^>]+> ee809142 ? sinsm f1, f2
0+120 <[^>]+> ce88c10d ? singte f4, #5\.0
0+124 <[^>]+> ee909183 ? cosd f1, f3
0+128 <[^>]+> ee98c145 ? cosem f4, f5
0+12c <[^>]+> 1e90e1a1 ? cosnedp f6, f1
0+130 <[^>]+> eea89105 ? tane f1, f5
0+134 <[^>]+> eea0c167 ? tansz f4, f7
0+138 <[^>]+> aea091ec ? tangedz f1, #4\.0
0+13c <[^>]+> eeb8c105 ? asne f4, f5
0+140 <[^>]+> eeb0e12e ? asnsp f6, #0\.5
0+144 <[^>]+> 4eb0d1e5 ? asnmidz f5, f5
0+148 <[^>]+> eec0d106 ? acss f5, f6
0+14c <[^>]+> eec0e180 ? acsd f6, f0
0+150 <[^>]+> 2ec8914e ? acscsem f1, #0\.5
0+154 <[^>]+> eed88105 ? atne f0, f5
0+158 <[^>]+> eed0916d ? atnsz f1, #5\.0
0+15c <[^>]+> bed0b182 ? atnltd f3, f2
0+160 <[^>]+> eee8d104 ? urde f5, f4
0+164 <[^>]+> eef8e105 ? nrme f6, f5
0+168 <[^>]+> 5ef0f1e5 ? nrmpldz f7, f5
0+16c <[^>]+> ee008130 ? fltsp f0, r8
0+170 <[^>]+> ee090110 ? flte f1, r0
0+174 <[^>]+> 0e0571f0 ? flteqdz f5, r7
0+178 <[^>]+> ee100111 ? fix r0, f1
0+17c <[^>]+> ee101177 ? fixz r1, f7
0+180 <[^>]+> 2e105155 ? fixcsm r5, f5
0+184 <[^>]+> ee400110 ? wfc r0
0+188 <[^>]+> ee201110 ? wfs r1
0+18c <[^>]+> 0e302110 ? rfseq r2
0+190 <[^>]+> ee504110 ? rfc r4
0+194 <[^>]+> ee90f119 ? cmf f0, #1\.0
0+198 <[^>]+> ee91f112 ? cmf f1, f2
0+19c <[^>]+> 0e90f111 ? cmfeq f0, f1
0+1a0 <[^>]+> eeb0f11b ? cnf f0, #3\.0
0+1a4 <[^>]+> eeb1f11e ? cnf f1, #0\.5
0+1a8 <[^>]+> 6eb3f114 ? cnfvs f3, f4
0+1ac <[^>]+> eed0f111 ? cmfe f0, f1
0+1b0 <[^>]+> 0ed1f112 ? cmfeeq f1, f2
0+1b4 <[^>]+> 0ed3f11d ? cmfeeq f3, #5\.0
0+1b8 <[^>]+> eef1f113 ? cnfe f1, f3
0+1bc <[^>]+> 0ef3f114 ? cnfeeq f3, f4
0+1c0 <[^>]+> 0ef4f117 ? cnfeeq f4, f7
0+1c4 <[^>]+> eef4f11d ? cnfe f4, #5\.0
0+1c8 <[^>]+> ed900200 ? lfm f0, 4, \[r0\]
0+1cc <[^>]+> ed900200 ? lfm f0, 4, \[r0\]
0+1d0 <[^>]+> ed911210 ? lfm f1, 4, \[r1, #64\]
0+1d4 <[^>]+> edae22ff ? sfm f2, 4, \[lr, #1020\]!
0+1d8 <[^>]+> 0c68f2ff ? sfmeq f7, 3, \[r8\], #-1020
0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\]
0+1e0 <[^>]+> eca8f203 ? sfm f7, 1, \[r8\], #12
0+1e4 <[^>]+> 0d16520c ? lfmeq f5, 4, \[r6, #-48\]
0+1e8 <[^>]+> 1d42c209 ? sfmne f4, 3, \[r2, #-36\]
0+1ec <[^>]+> 1d62c209 ? sfmne f4, 3, \[r2, #-36\]!

5
gas/testsuite/gas/arm/float.s
View File

@ -1,5 +1,6 @@
.text
.align 0
.text
.align 0
l:
mvfe f0, f1
mvfeqe f3, f5
mvfeqd f4, #1.0

16
gas/testsuite/gas/arm/immed.d Normal file
View File

@ -0,0 +1,16 @@
# name: immediate expressions
# as:
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
0+0000 <[^>]+> e3a00000 ? mov r0, #0 ; 0x0
0+0004 <[^>]+> e3e00003 ? mvn r0, #3 ; 0x3
0+0008 <[^>]+> e51f0010 ? ldr r0, \[pc, #-16\] ; 0+0 <[^>]+>
0+000c <[^>]+> e51f0014 ? ldr r0, \[pc, #-20\] ; 0+0 <[^>]+>
\.\.\.
0+1010 <[^>]+> e3a00008 ? mov r0, #8 ; 0x8
0+1014 <[^>]+> e59f00e4 ? ldr r0, \[pc, #228\] ; 0+1100 <[^>]+>
0+1018 <[^>]+> e1a00000 ? nop \(mov r0,r0\)
0+101c <[^>]+> e1a00000 ? nop \(mov r0,r0\)

4
gas/testsuite/gas/arm/immed.s
View File

@ -9,3 +9,7 @@ bar:
.space 4096
mov r0, #(. - bar - 8) & 0xff
ldr r0, [pc, # (bar - . -8) & 0xff]
@ section padding for a.out's benefit
nop
nop

16
gas/testsuite/gas/arm/iwmmxt-bad.l
View File

@ -1,9 +1,9 @@
[^:]*: Assembler messages:
[^:]*:1: Error: conditional execution not supported with control register
[^:]*:2: Error: non-word size not supported with control register
[^:]*:3: Error: non-word size not supported with control register
[^:]*:4: Error: non-word size not supported with control register
[^:]*:5: Error: conditional execution not supported with control register
[^:]*:6: Error: non-word size not supported with control register
[^:]*:7: Error: non-word size not supported with control register
[^:]*:8: Error: non-word size not supported with control register
[^:]*:1: Error: instruction cannot be conditional -- `wldrwgt wcgr0,\[r1\]'
[^:]*:2: Error: iWMMXt data register expected -- `wldrb wcgr0,\[r1\]'
[^:]*:3: Error: iWMMXt data register expected -- `wldrh wcgr0,\[r1\]'
[^:]*:4: Error: iWMMXt data register expected -- `wldrd wcgr0,\[r1\]'
[^:]*:5: Error: instruction cannot be conditional -- `wstrwgt wcgr0,\[r1\]'
[^:]*:6: Error: iWMMXt data register expected -- `wstrb wcgr0,\[r1\]'
[^:]*:7: Error: iWMMXt data register expected -- `wstrh wcgr0,\[r1\]'
[^:]*:8: Error: iWMMXt data register expected -- `wstrd wcgr0,\[r1\]'

3
gas/testsuite/gas/arm/iwmmxt.d
View File

@ -166,3 +166,6 @@ Disassembly of section .text:
0+278 <[^>]*> 0e9540ea[ ]+wunpckilweq[ ]+wr4, wr5, wr10
0+27c <[^>]*> 1e143005[ ]+wxorne[ ]+wr3, wr4, wr5
0+280 <[^>]*> ae377007[ ]+wandnge[ ]+wr7, wr7, wr7
0+284 <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\)
0+288 <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\)
0+28c <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\)

5
gas/testsuite/gas/arm/iwmmxt.s
View File

@ -202,3 +202,8 @@ iwmmxt:
wxorne wr3, wr4, wr5
wzeroge wr7
@ a.out-required section size padding
nop
nop
nop

12
gas/testsuite/gas/arm/macro1.d Normal file
View File

@ -0,0 +1,12 @@
# name: Macro scrubbing
# as:
# objdump: -dr --prefix-addresses --show-raw-insn
[^:]+: +file format .*arm.*
Disassembly of section .text:
0+0 <[^>]*> e8bd8030 ? ldmia sp!, {r4, r5, pc}
0+4 <[^>]*> e1a00000 ? nop \(mov r0,r0\)
0+8 <[^>]*> e1a00000 ? nop \(mov r0,r0\)
0+c <[^>]*> e1a00000 ? nop \(mov r0,r0\)

12
gas/testsuite/gas/arm/macro1.s Normal file
View File

@ -0,0 +1,12 @@
@ Test that macro expansions are properly scrubbed.
.macro popret regs
ldmia sp!, {\regs, pc}
.endm
.text
l:
popret "r4, r5"
@ section padding for a.out's sake
nop
nop
nop

78
gas/testsuite/gas/arm/maverick.d
View File

@ -13,121 +13,121 @@ Disassembly of section .text:
0*8 <load_store\+0x8> 7d ?1c ?24 ?ef ? * cfldrsvc mvf2, ?\[ip, #-956\]
0*c <load_store\+0xc> bd ?1a ?04 ?ff ? * cfldrslt mvf0, ?\[sl, #-1020\]
0*10 <load_store\+0x10> 3d ?11 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1, #-156\]
0*14 <load_store\+0x14> ed ?bf ?d4 ?68 ? * cfldrs mvf13, ?\[pc, #416\]!
0*14 <load_store\+0x14> ed ?b9 ?d4 ?68 ? * cfldrs mvf13, ?\[r9, #416\]!
0*18 <load_store\+0x18> 2d ?30 ?94 ?ff ? * cfldrscs mvf9, ?\[r0, #-1020\]!
0*1c <load_store\+0x1c> 9d ?31 ?44 ?27 ? * cfldrsls mvf4, ?\[r1, #-156\]!
0*20 <load_store\+0x20> dd ?bf ?74 ?68 ? * cfldrsle mvf7, ?\[pc, #416\]!
0*20 <load_store\+0x20> dd ?b9 ?74 ?68 ? * cfldrsle mvf7, ?\[r9, #416\]!
0*24 <load_store\+0x24> 6d ?30 ?b4 ?ff ? * cfldrsvs mvf11, ?\[r0, #-1020\]!
0*28 <load_store\+0x28> 3c ?31 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1\], #-156
0*2c <load_store\+0x2c> ec ?bf ?d4 ?68 ? * cfldrs mvf13, ?\[pc\], #416
0*2c <load_store\+0x2c> ec ?b9 ?d4 ?68 ? * cfldrs mvf13, ?\[r9\], #416
0*30 <load_store\+0x30> 2c ?30 ?94 ?ff ? * cfldrscs mvf9, ?\[r0\], #-1020
0*34 <load_store\+0x34> 9c ?31 ?44 ?27 ? * cfldrsls mvf4, ?\[r1\], #-156
0*38 <load_store\+0x38> dc ?bf ?74 ?68 ? * cfldrsle mvf7, ?\[pc\], #416
0*38 <load_store\+0x38> dc ?b9 ?74 ?68 ? * cfldrsle mvf7, ?\[r9\], #416
0*3c <load_store\+0x3c> 6d ?50 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0, #-1020\]
0*40 <load_store\+0x40> 3d ?51 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1, #-156\]
0*44 <load_store\+0x44> ed ?df ?d4 ?68 ? * cfldrd mvd13, ?\[pc, #416\]
0*44 <load_store\+0x44> ed ?d9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9, #416\]
0*48 <load_store\+0x48> 2d ?50 ?94 ?ff ? * cfldrdcs mvd9, ?\[r0, #-1020\]
0*4c <load_store\+0x4c> 9d ?51 ?44 ?27 ? * cfldrdls mvd4, ?\[r1, #-156\]
0*50 <load_store\+0x50> dd ?ff ?74 ?68 ? * cfldrdle mvd7, ?\[pc, #416\]!
0*50 <load_store\+0x50> dd ?f9 ?74 ?68 ? * cfldrdle mvd7, ?\[r9, #416\]!
0*54 <load_store\+0x54> 6d ?70 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0, #-1020\]!
0*58 <load_store\+0x58> 3d ?71 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1, #-156\]!
0*5c <load_store\+0x5c> ed ?ff ?d4 ?68 ? * cfldrd mvd13, ?\[pc, #416\]!
0*5c <load_store\+0x5c> ed ?f9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9, #416\]!
0*60 <load_store\+0x60> 2d ?70 ?94 ?ff ? * cfldrdcs mvd9, ?\[r0, #-1020\]!
0*64 <load_store\+0x64> 9c ?71 ?44 ?27 ? * cfldrdls mvd4, ?\[r1\], #-156
0*68 <load_store\+0x68> dc ?ff ?74 ?68 ? * cfldrdle mvd7, ?\[pc\], #416
0*68 <load_store\+0x68> dc ?f9 ?74 ?68 ? * cfldrdle mvd7, ?\[r9\], #416
0*6c <load_store\+0x6c> 6c ?70 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0\], #-1020
0*70 <load_store\+0x70> 3c ?71 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1\], #-156
0*74 <load_store\+0x74> ec ?ff ?d4 ?68 ? * cfldrd mvd13, ?\[pc\], #416
0*74 <load_store\+0x74> ec ?f9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9\], #416
0*78 <load_store\+0x78> 2d ?10 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0, #-1020\]
0*7c <load_store\+0x7c> 9d ?11 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1, #-156\]
0*80 <load_store\+0x80> dd ?9f ?75 ?68 ? * cfldr32le mvfx7, ?\[pc, #416\]
0*80 <load_store\+0x80> dd ?99 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9, #416\]
0*84 <load_store\+0x84> 6d ?10 ?b5 ?ff ? * cfldr32vs mvfx11, ?\[r0, #-1020\]
0*88 <load_store\+0x88> 3d ?11 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1, #-156\]
0*8c <load_store\+0x8c> ed ?bf ?d5 ?68 ? * cfldr32 mvfx13, ?\[pc, #416\]!
0*8c <load_store\+0x8c> ed ?b9 ?d5 ?68 ? * cfldr32 mvfx13, ?\[r9, #416\]!
0*90 <load_store\+0x90> 2d ?30 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0, #-1020\]!
0*94 <load_store\+0x94> 9d ?31 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1, #-156\]!
0*98 <load_store\+0x98> dd ?bf ?75 ?68 ? * cfldr32le mvfx7, ?\[pc, #416\]!
0*98 <load_store\+0x98> dd ?b9 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9, #416\]!
0*9c <load_store\+0x9c> 6d ?30 ?b5 ?ff ? * cfldr32vs mvfx11, ?\[r0, #-1020\]!
0*a0 <load_store\+0xa0> 3c ?31 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1\], #-156
0*a4 <load_store\+0xa4> ec ?bf ?d5 ?68 ? * cfldr32 mvfx13, ?\[pc\], #416
0*a4 <load_store\+0xa4> ec ?b9 ?d5 ?68 ? * cfldr32 mvfx13, ?\[r9\], #416
0*a8 <load_store\+0xa8> 2c ?30 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0\], #-1020
0*ac <load_store\+0xac> 9c ?31 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1\], #-156
0*b0 <load_store\+0xb0> dc ?bf ?75 ?68 ? * cfldr32le mvfx7, ?\[pc\], #416
0*b0 <load_store\+0xb0> dc ?b9 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9\], #416
0*b4 <load_store\+0xb4> 6d ?50 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0, #-1020\]
0*b8 <load_store\+0xb8> 3d ?51 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1, #-156\]
0*bc <load_store\+0xbc> ed ?df ?d5 ?68 ? * cfldr64 mvdx13, ?\[pc, #416\]
0*bc <load_store\+0xbc> ed ?d9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9, #416\]
0*c0 <load_store\+0xc0> 2d ?50 ?95 ?ff ? * cfldr64cs mvdx9, ?\[r0, #-1020\]
0*c4 <load_store\+0xc4> 9d ?51 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1, #-156\]
0*c8 <load_store\+0xc8> dd ?ff ?75 ?68 ? * cfldr64le mvdx7, ?\[pc, #416\]!
0*c8 <load_store\+0xc8> dd ?f9 ?75 ?68 ? * cfldr64le mvdx7, ?\[r9, #416\]!
0*cc <load_store\+0xcc> 6d ?70 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0, #-1020\]!
0*d0 <load_store\+0xd0> 3d ?71 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1, #-156\]!
0*d4 <load_store\+0xd4> ed ?ff ?d5 ?68 ? * cfldr64 mvdx13, ?\[pc, #416\]!
0*d4 <load_store\+0xd4> ed ?f9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9, #416\]!
0*d8 <load_store\+0xd8> 2d ?70 ?95 ?ff ? * cfldr64cs mvdx9, ?\[r0, #-1020\]!
0*dc <load_store\+0xdc> 9c ?71 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1\], #-156
0*e0 <load_store\+0xe0> dc ?ff ?75 ?68 ? * cfldr64le mvdx7, ?\[pc\], #416
0*e0 <load_store\+0xe0> dc ?f9 ?75 ?68 ? * cfldr64le mvdx7, ?\[r9\], #416
0*e4 <load_store\+0xe4> 6c ?70 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0\], #-1020
0*e8 <load_store\+0xe8> 3c ?71 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1\], #-156
0*ec <load_store\+0xec> ec ?ff ?d5 ?68 ? * cfldr64 mvdx13, ?\[pc\], #416
0*ec <load_store\+0xec> ec ?f9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9\], #416
0*f0 <load_store\+0xf0> 2d ?00 ?94 ?ff ? * cfstrscs mvf9, ?\[r0, #-1020\]
0*f4 <load_store\+0xf4> 9d ?01 ?44 ?27 ? * cfstrsls mvf4, ?\[r1, #-156\]
0*f8 <load_store\+0xf8> dd ?8f ?74 ?68 ? * cfstrsle mvf7, ?\[pc, #416\]
0*f8 <load_store\+0xf8> dd ?89 ?74 ?68 ? * cfstrsle mvf7, ?\[r9, #416\]
0*fc <load_store\+0xfc> 6d ?00 ?b4 ?ff ? * cfstrsvs mvf11, ?\[r0, #-1020\]
0*100 <load_store\+0x100> 3d ?01 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1, #-156\]
0*104 <load_store\+0x104> ed ?af ?d4 ?68 ? * cfstrs mvf13, ?\[pc, #416\]!
0*104 <load_store\+0x104> ed ?a9 ?d4 ?68 ? * cfstrs mvf13, ?\[r9, #416\]!
0*108 <load_store\+0x108> 2d ?20 ?94 ?ff ? * cfstrscs mvf9, ?\[r0, #-1020\]!
0*10c <load_store\+0x10c> 9d ?21 ?44 ?27 ? * cfstrsls mvf4, ?\[r1, #-156\]!
0*110 <load_store\+0x110> dd ?af ?74 ?68 ? * cfstrsle mvf7, ?\[pc, #416\]!
0*110 <load_store\+0x110> dd ?a9 ?74 ?68 ? * cfstrsle mvf7, ?\[r9, #416\]!
0*114 <load_store\+0x114> 6d ?20 ?b4 ?ff ? * cfstrsvs mvf11, ?\[r0, #-1020\]!
0*118 <load_store\+0x118> 3c ?21 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1\], #-156
0*11c <load_store\+0x11c> ec ?af ?d4 ?68 ? * cfstrs mvf13, ?\[pc\], #416
0*11c <load_store\+0x11c> ec ?a9 ?d4 ?68 ? * cfstrs mvf13, ?\[r9\], #416
0*120 <load_store\+0x120> 2c ?20 ?94 ?ff ? * cfstrscs mvf9, ?\[r0\], #-1020
0*124 <load_store\+0x124> 9c ?21 ?44 ?27 ? * cfstrsls mvf4, ?\[r1\], #-156
0*128 <load_store\+0x128> dc ?af ?74 ?68 ? * cfstrsle mvf7, ?\[pc\], #416
0*128 <load_store\+0x128> dc ?a9 ?74 ?68 ? * cfstrsle mvf7, ?\[r9\], #416
0*12c <load_store\+0x12c> 6d ?40 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0, #-1020\]
0*130 <load_store\+0x130> 3d ?41 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1, #-156\]
0*134 <load_store\+0x134> ed ?cf ?d4 ?68 ? * cfstrd mvd13, ?\[pc, #416\]
0*134 <load_store\+0x134> ed ?c9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9, #416\]
0*138 <load_store\+0x138> 2d ?40 ?94 ?ff ? * cfstrdcs mvd9, ?\[r0, #-1020\]
0*13c <load_store\+0x13c> 9d ?41 ?44 ?27 ? * cfstrdls mvd4, ?\[r1, #-156\]
0*140 <load_store\+0x140> dd ?ef ?74 ?68 ? * cfstrdle mvd7, ?\[pc, #416\]!
0*140 <load_store\+0x140> dd ?e9 ?74 ?68 ? * cfstrdle mvd7, ?\[r9, #416\]!
0*144 <load_store\+0x144> 6d ?60 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0, #-1020\]!
0*148 <load_store\+0x148> 3d ?61 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1, #-156\]!
0*14c <load_store\+0x14c> ed ?ef ?d4 ?68 ? * cfstrd mvd13, ?\[pc, #416\]!
0*14c <load_store\+0x14c> ed ?e9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9, #416\]!
0*150 <load_store\+0x150> 2d ?60 ?94 ?ff ? * cfstrdcs mvd9, ?\[r0, #-1020\]!
0*154 <load_store\+0x154> 9c ?61 ?44 ?27 ? * cfstrdls mvd4, ?\[r1\], #-156
0*158 <load_store\+0x158> dc ?ef ?74 ?68 ? * cfstrdle mvd7, ?\[pc\], #416
0*158 <load_store\+0x158> dc ?e9 ?74 ?68 ? * cfstrdle mvd7, ?\[r9\], #416
0*15c <load_store\+0x15c> 6c ?60 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0\], #-1020
0*160 <load_store\+0x160> 3c ?61 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1\], #-156
0*164 <load_store\+0x164> ec ?ef ?d4 ?68 ? * cfstrd mvd13, ?\[pc\], #416
0*164 <load_store\+0x164> ec ?e9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9\], #416
0*168 <load_store\+0x168> 2d ?00 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0, #-1020\]
0*16c <load_store\+0x16c> 9d ?01 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1, #-156\]
0*170 <load_store\+0x170> dd ?8f ?75 ?68 ? * cfstr32le mvfx7, ?\[pc, #416\]
0*170 <load_store\+0x170> dd ?89 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9, #416\]
0*174 <load_store\+0x174> 6d ?00 ?b5 ?ff ? * cfstr32vs mvfx11, ?\[r0, #-1020\]
0*178 <load_store\+0x178> 3d ?01 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1, #-156\]
0*17c <load_store\+0x17c> ed ?af ?d5 ?68 ? * cfstr32 mvfx13, ?\[pc, #416\]!
0*17c <load_store\+0x17c> ed ?a9 ?d5 ?68 ? * cfstr32 mvfx13, ?\[r9, #416\]!
0*180 <load_store\+0x180> 2d ?20 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0, #-1020\]!
0*184 <load_store\+0x184> 9d ?21 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1, #-156\]!
0*188 <load_store\+0x188> dd ?af ?75 ?68 ? * cfstr32le mvfx7, ?\[pc, #416\]!
0*188 <load_store\+0x188> dd ?a9 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9, #416\]!
0*18c <load_store\+0x18c> 6d ?20 ?b5 ?ff ? * cfstr32vs mvfx11, ?\[r0, #-1020\]!
0*190 <load_store\+0x190> 3c ?21 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1\], #-156
0*194 <load_store\+0x194> ec ?af ?d5 ?68 ? * cfstr32 mvfx13, ?\[pc\], #416
0*194 <load_store\+0x194> ec ?a9 ?d5 ?68 ? * cfstr32 mvfx13, ?\[r9\], #416
0*198 <load_store\+0x198> 2c ?20 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0\], #-1020
0*19c <load_store\+0x19c> 9c ?21 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1\], #-156
0*1a0 <load_store\+0x1a0> dc ?af ?75 ?68 ? * cfstr32le mvfx7, ?\[pc\], #416
0*1a0 <load_store\+0x1a0> dc ?a9 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9\], #416
0*1a4 <load_store\+0x1a4> 6d ?40 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0, #-1020\]
0*1a8 <load_store\+0x1a8> 3d ?41 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1, #-156\]
0*1ac <load_store\+0x1ac> ed ?cf ?d5 ?68 ? * cfstr64 mvdx13, ?\[pc, #416\]
0*1ac <load_store\+0x1ac> ed ?c9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9, #416\]
0*1b0 <load_store\+0x1b0> 2d ?40 ?95 ?ff ? * cfstr64cs mvdx9, ?\[r0, #-1020\]
0*1b4 <load_store\+0x1b4> 9d ?41 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1, #-156\]
0*1b8 <load_store\+0x1b8> dd ?ef ?75 ?68 ? * cfstr64le mvdx7, ?\[pc, #416\]!
0*1b8 <load_store\+0x1b8> dd ?e9 ?75 ?68 ? * cfstr64le mvdx7, ?\[r9, #416\]!
0*1bc <load_store\+0x1bc> 6d ?60 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0, #-1020\]!
0*1c0 <load_store\+0x1c0> 3d ?61 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1, #-156\]!
0*1c4 <load_store\+0x1c4> ed ?ef ?d5 ?68 ? * cfstr64 mvdx13, ?\[pc, #416\]!
0*1c4 <load_store\+0x1c4> ed ?e9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9, #416\]!
0*1c8 <load_store\+0x1c8> 2d ?60 ?95 ?ff ? * cfstr64cs mvdx9, ?\[r0, #-1020\]!
0*1cc <load_store\+0x1cc> 9c ?61 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1\], #-156
0*1d0 <load_store\+0x1d0> dc ?ef ?75 ?68 ? * cfstr64le mvdx7, ?\[pc\], #416
0*1d0 <load_store\+0x1d0> dc ?e9 ?75 ?68 ? * cfstr64le mvdx7, ?\[r9\], #416
0*1d4 <load_store\+0x1d4> 6c ?60 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0\], #-1020
0*1d8 <load_store\+0x1d8> 3c ?61 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1\], #-156
0*1dc <load_store\+0x1dc> ec ?ef ?d5 ?68 ? * cfstr64 mvdx13, ?\[pc\], #416
0*1dc <load_store\+0x1dc> ec ?e9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9\], #416
# move:
0*1e0 <move> 2e ?09 ?04 ?50 ? * cfmvsrcs mvf9, ?r0
0*1e4 <move\+0x4> 5e ?0f ?74 ?50 ? * cfmvsrpl mvf15, ?r7

78
gas/testsuite/gas/arm/maverick.s
View File

@ -6,121 +6,121 @@ load_store:
cfldrsvc mvf2, [r12, #-956]
cfldrslt mvf0, [sl, #-1020]
cfldrscc mvf12, [r1, #-156]
cfldrs mvf13, [r15, #416]!
cfldrs mvf13, [r9, #416]!
cfldrscs mvf9, [r0, #-1020]!
cfldrsls mvf4, [r1, #-156]!
cfldrsle mvf7, [pc, #416]!
cfldrsle mvf7, [r9, #416]!
cfldrsvs mvf11, [r0, #-1020]!
cfldrscc mvf12, [r1], #-156
cfldrs mvf13, [r15], #416
cfldrs mvf13, [r9], #416
cfldrscs mvf9, [r0], #-1020
cfldrsls mvf4, [r1], #-156
cfldrsle mvf7, [pc], #416
cfldrsle mvf7, [r9], #416
cfldrdvs mvd11, [r0, #-1020]
cfldrdcc mvd12, [r1, #-156]
cfldrd mvd13, [r15, #416]
cfldrd mvd13, [r9, #416]
cfldrdcs mvd9, [r0, #-1020]
cfldrdls mvd4, [r1, #-156]
cfldrdle mvd7, [pc, #416]!
cfldrdle mvd7, [r9, #416]!
cfldrdvs mvd11, [r0, #-1020]!
cfldrdcc mvd12, [r1, #-156]!
cfldrd mvd13, [r15, #416]!
cfldrd mvd13, [r9, #416]!
cfldrdcs mvd9, [r0, #-1020]!
cfldrdls mvd4, [r1], #-156
cfldrdle mvd7, [pc], #416
cfldrdle mvd7, [r9], #416
cfldrdvs mvd11, [r0], #-1020
cfldrdcc mvd12, [r1], #-156
cfldrd mvd13, [r15], #416
cfldrd mvd13, [r9], #416
cfldr32cs mvfx9, [r0, #-1020]
cfldr32ls mvfx4, [r1, #-156]
cfldr32le mvfx7, [pc, #416]
cfldr32le mvfx7, [r9, #416]
cfldr32vs mvfx11, [r0, #-1020]
cfldr32cc mvfx12, [r1, #-156]
cfldr32 mvfx13, [r15, #416]!
cfldr32 mvfx13, [r9, #416]!
cfldr32cs mvfx9, [r0, #-1020]!
cfldr32ls mvfx4, [r1, #-156]!
cfldr32le mvfx7, [pc, #416]!
cfldr32le mvfx7, [r9, #416]!
cfldr32vs mvfx11, [r0, #-1020]!
cfldr32cc mvfx12, [r1], #-156
cfldr32 mvfx13, [r15], #416
cfldr32 mvfx13, [r9], #416
cfldr32cs mvfx9, [r0], #-1020
cfldr32ls mvfx4, [r1], #-156
cfldr32le mvfx7, [pc], #416
cfldr32le mvfx7, [r9], #416
cfldr64vs mvdx11, [r0, #-1020]
cfldr64cc mvdx12, [r1, #-156]
cfldr64 mvdx13, [r15, #416]
cfldr64 mvdx13, [r9, #416]
cfldr64cs mvdx9, [r0, #-1020]
cfldr64ls mvdx4, [r1, #-156]
cfldr64le mvdx7, [pc, #416]!
cfldr64le mvdx7, [r9, #416]!
cfldr64vs mvdx11, [r0, #-1020]!
cfldr64cc mvdx12, [r1, #-156]!
cfldr64 mvdx13, [r15, #416]!
cfldr64 mvdx13, [r9, #416]!
cfldr64cs mvdx9, [r0, #-1020]!
cfldr64ls mvdx4, [r1], #-156
cfldr64le mvdx7, [pc], #416
cfldr64le mvdx7, [r9], #416
cfldr64vs mvdx11, [r0], #-1020
cfldr64cc mvdx12, [r1], #-156
cfldr64 mvdx13, [r15], #416
cfldr64 mvdx13, [r9], #416
cfstrscs mvf9, [r0, #-1020]
cfstrsls mvf4, [r1, #-156]
cfstrsle mvf7, [pc, #416]
cfstrsle mvf7, [r9, #416]
cfstrsvs mvf11, [r0, #-1020]
cfstrscc mvf12, [r1, #-156]
cfstrs mvf13, [r15, #416]!
cfstrs mvf13, [r9, #416]!
cfstrscs mvf9, [r0, #-1020]!
cfstrsls mvf4, [r1, #-156]!
cfstrsle mvf7, [pc, #416]!
cfstrsle mvf7, [r9, #416]!
cfstrsvs mvf11, [r0, #-1020]!
cfstrscc mvf12, [r1], #-156
cfstrs mvf13, [r15], #416
cfstrs mvf13, [r9], #416
cfstrscs mvf9, [r0], #-1020
cfstrsls mvf4, [r1], #-156
cfstrsle mvf7, [pc], #416
cfstrsle mvf7, [r9], #416
cfstrdvs mvd11, [r0, #-1020]
cfstrdcc mvd12, [r1, #-156]
cfstrd mvd13, [r15, #416]
cfstrd mvd13, [r9, #416]
cfstrdcs mvd9, [r0, #-1020]
cfstrdls mvd4, [r1, #-156]
cfstrdle mvd7, [pc, #416]!
cfstrdle mvd7, [r9, #416]!
cfstrdvs mvd11, [r0, #-1020]!
cfstrdcc mvd12, [r1, #-156]!
cfstrd mvd13, [r15, #416]!
cfstrd mvd13, [r9, #416]!
cfstrdcs mvd9, [r0, #-1020]!
cfstrdls mvd4, [r1], #-156
cfstrdle mvd7, [pc], #416
cfstrdle mvd7, [r9], #416
cfstrdvs mvd11, [r0], #-1020
cfstrdcc mvd12, [r1], #-156
cfstrd mvd13, [r15], #416
cfstrd mvd13, [r9], #416
cfstr32cs mvfx9, [r0, #-1020]
cfstr32ls mvfx4, [r1, #-156]
cfstr32le mvfx7, [pc, #416]
cfstr32le mvfx7, [r9, #416]
cfstr32vs mvfx11, [r0, #-1020]
cfstr32cc mvfx12, [r1, #-156]
cfstr32 mvfx13, [r15, #416]!
cfstr32 mvfx13, [r9, #416]!
cfstr32cs mvfx9, [r0, #-1020]!
cfstr32ls mvfx4, [r1, #-156]!
cfstr32le mvfx7, [pc, #416]!
cfstr32le mvfx7, [r9, #416]!
cfstr32vs mvfx11, [r0, #-1020]!
cfstr32cc mvfx12, [r1], #-156
cfstr32 mvfx13, [r15], #416
cfstr32 mvfx13, [r9], #416
cfstr32cs mvfx9, [r0], #-1020
cfstr32ls mvfx4, [r1], #-156
cfstr32le mvfx7, [pc], #416
cfstr32le mvfx7, [r9], #416
cfstr64vs mvdx11, [r0, #-1020]
cfstr64cc mvdx12, [r1, #-156]
cfstr64 mvdx13, [r15, #416]
cfstr64 mvdx13, [r9, #416]
cfstr64cs mvdx9, [r0, #-1020]
cfstr64ls mvdx4, [r1, #-156]
cfstr64le mvdx7, [pc, #416]!
cfstr64le mvdx7, [r9, #416]!
cfstr64vs mvdx11, [r0, #-1020]!
cfstr64cc mvdx12, [r1, #-156]!
cfstr64 mvdx13, [r15, #416]!
cfstr64 mvdx13, [r9, #416]!
cfstr64cs mvdx9, [r0, #-1020]!
cfstr64ls mvdx4, [r1], #-156
cfstr64le mvdx7, [pc], #416
cfstr64le mvdx7, [r9], #416
cfstr64vs mvdx11, [r0], #-1020
cfstr64cc mvdx12, [r1], #-156
cfstr64 mvdx13, [r15], #416
cfstr64 mvdx13, [r9], #416
move:
cfmvsrcs mvf9, r0
cfmvsrpl mvf15, r7

11
gas/testsuite/gas/arm/offset.d Normal file
View File

@ -0,0 +1,11 @@
# name: OFFSET_IMM regression
# as:
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
0+0 <[^>]+> e51f0004 ? ldr r0, \[pc, #-4\] ; 0+4 <[^>]+>
0+4 <[^>]+> e1a00000 ? nop \(mov r0,r0\)
0+8 <[^>]+> e1a00000 ? nop \(mov r0,r0\)
0+c <[^>]+> e1a00000 ? nop \(mov r0,r0\)

17
gas/testsuite/gas/arm/offset.s
View File

@ -1,5 +1,14 @@
@ test for OFFSET_IMM reloc against global symbols
@ test that an OFFSET_IMM reloc against a global symbol is
@ still resolved by the assembler, as long as the symbol is in
@ the same section as the reference
.text
.globl l
.globl foo
l:
ldr r0, foo
foo:
nop
.globl foo
foo: .word 0
ldr r0, foo
@ pad section for a.out's benefit
nop
nop

2
gas/testsuite/gas/arm/pic.d
View File

@ -13,7 +13,7 @@ Disassembly of section .text:
\.\.\.
8: R_ARM_ABS32 sym
c: R_ARM_GOT32 sym
10: R_ARM_GOTOFF sym
10: R_ARM_GOTOFF32 sym
14: R_ARM_GOTPC _GLOBAL_OFFSET_TABLE_
18: R_ARM_TARGET1 foo2
1c: R_ARM_SBREL32 foo3

8
gas/testsuite/gas/arm/r15-bad.l
View File

@ -1,6 +1,6 @@
[^:]*: Assembler messages:
[^:]*:5: Error: r15 not allowed here -- `mul r15,r1'
[^:]*:6: Error: r15 not allowed here -- `mul r1,r15'
[^:]*:5: Error: r15 not allowed here -- `mul r15,r1,r2'
[^:]*:6: Error: r15 not allowed here -- `mul r1,r15,r2'
[^:]*:7: Error: r15 not allowed here -- `mla r15,r2,r3,r4'
[^:]*:8: Error: r15 not allowed here -- `mla r1,r15,r3,r4'
[^:]*:9: Error: r15 not allowed here -- `mla r1,r2,r15,r4'
@ -59,6 +59,6 @@
[^:]*:62: Error: r15 not allowed here -- `pkhtb r1,r2,r15'
[^:]*:63: Error: r15 not allowed here -- `ldrex r15,[[]r2[]]'
[^:]*:64: Error: r15 not allowed here -- `ldrex r1,[[]r15[]]'
[^:]*:65: Error: r15 not allowed in swap -- `swp r15,r2,[[]r3[]]'
[^:]*:66: Error: r15 not allowed in swap -- `swp r1,r15,[[]r3[]]'
[^:]*:65: Error: r15 not allowed here -- `swp r15,r2,[[]r3[]]'
[^:]*:66: Error: r15 not allowed here -- `swp r1,r15,[[]r3[]]'
[^:]*:67: Error: r15 not allowed here -- `swp r1,r2,[[]r15[]]'

4
gas/testsuite/gas/arm/r15-bad.s
View File

@ -2,8 +2,8 @@
.align 0
label:
mul r15, r1
mul r1, r15
mul r15, r1, r2
mul r1, r15, r2
mla r15, r2, r3, r4
mla r1, r15, r3, r4
mla r1, r2, r15, r4

4
gas/testsuite/gas/arm/req.l
View File

@ -1,3 +1,3 @@
[^:]*: Assembler messages:
[^:]*:18: Error: register expected, not 'foo,foo,foo' -- `add foo,foo,foo'
[^:]*:24: Error: register expected, not 'r0,r0,r0' -- `add r0,r0,r0'
[^:]*:18: Error: ARM register expected -- `add foo,foo,foo'
[^:]*:21: Warning: ignoring attempt to undefine built-in register 'r0'

6
gas/testsuite/gas/arm/req.s
View File

@ -2,7 +2,7 @@
.global test_dot_req_and_unreq
test_dot_req_and_unreq:
# Check that builtin register alias 'r0' works.
# Check that builtin register alias 'r0' works.
add r0, r0, r0
# Create an alias for r0.
@ -17,9 +17,9 @@ test_dot_req_and_unreq:
# And make sure that it no longer works.
add foo, foo, foo
# Finally remove the builtin alias for r0.
# Attempt to remove the builtin alias for r0.
.unreq r0
# And make sure that this no longer works.
# That is ignored, so this should still work.
add r0, r0, r0

186
gas/testsuite/gas/arm/t16-bad.l Normal file
View File

@ -0,0 +1,186 @@
[^:]*: Assembler messages:
[^:]*:36: Error: lo register required -- `tst r8,r0'
[^:]*:36: Error: lo register required -- `tst r0,r8'
[^:]*:36: Error: unshifted register required -- `tst r0,#12'
[^:]*:36: Error: unshifted register required -- `tst r0,r1,lsl#2'
[^:]*:36: Error: unshifted register required -- `tst r0,r1,lsl r3'
[^:]*:37: Error: lo register required -- `cmn r8,r0'
[^:]*:37: Error: lo register required -- `cmn r0,r8'
[^:]*:37: Error: unshifted register required -- `cmn r0,#12'
[^:]*:37: Error: unshifted register required -- `cmn r0,r1,lsl#2'
[^:]*:37: Error: unshifted register required -- `cmn r0,r1,lsl r3'
[^:]*:38: Error: lo register required -- `mvn r8,r0'
[^:]*:38: Error: lo register required -- `mvn r0,r8'
[^:]*:38: Error: unshifted register required -- `mvn r0,#12'
[^:]*:38: Error: unshifted register required -- `mvn r0,r1,lsl#2'
[^:]*:38: Error: unshifted register required -- `mvn r0,r1,lsl r3'
[^:]*:39: Error: lo register required -- `neg r8,r0'
[^:]*:39: Error: lo register required -- `neg r0,r8'
[^:]*:40: Error: lo register required -- `rev r8,r0'
[^:]*:40: Error: lo register required -- `rev r0,r8'
[^:]*:41: Error: lo register required -- `rev16 r8,r0'
[^:]*:41: Error: lo register required -- `rev16 r0,r8'
[^:]*:42: Error: lo register required -- `revsh r8,r0'
[^:]*:42: Error: lo register required -- `revsh r0,r8'
[^:]*:43: Error: lo register required -- `sxtb r8,r0'
[^:]*:43: Error: lo register required -- `sxtb r0,r8'
[^:]*:43: Error: Thumb encoding does not support rotation -- `sxtb r0,r1,ror#8'
[^:]*:44: Error: lo register required -- `sxth r8,r0'
[^:]*:44: Error: lo register required -- `sxth r0,r8'
[^:]*:44: Error: Thumb encoding does not support rotation -- `sxth r0,r1,ror#8'
[^:]*:45: Error: lo register required -- `uxtb r8,r0'
[^:]*:45: Error: lo register required -- `uxtb r0,r8'
[^:]*:45: Error: Thumb encoding does not support rotation -- `uxtb r0,r1,ror#8'
[^:]*:46: Error: lo register required -- `uxth r8,r0'
[^:]*:46: Error: lo register required -- `uxth r0,r8'
[^:]*:46: Error: Thumb encoding does not support rotation -- `uxth r0,r1,ror#8'
[^:]*:48: Error: dest must overlap one source register -- `adc r1,r2,r3'
[^:]*:48: Error: lo register required -- `adc r8,r0'
[^:]*:48: Error: lo register required -- `adc r0,r8'
[^:]*:48: Error: unshifted register required -- `adc r0,#12'
[^:]*:48: Error: unshifted register required -- `adc r0,r1,lsl#2'
[^:]*:48: Error: unshifted register required -- `adc r0,r1,lsl r3'
[^:]*:49: Error: dest must overlap one source register -- `and r1,r2,r3'
[^:]*:49: Error: lo register required -- `and r8,r0'
[^:]*:49: Error: lo register required -- `and r0,r8'
[^:]*:49: Error: unshifted register required -- `and r0,#12'
[^:]*:49: Error: unshifted register required -- `and r0,r1,lsl#2'
[^:]*:49: Error: unshifted register required -- `and r0,r1,lsl r3'
[^:]*:50: Error: dest and source1 must be the same register -- `bic r1,r2,r3'
[^:]*:50: Error: lo register required -- `bic r8,r0'
[^:]*:50: Error: lo register required -- `bic r0,r8'
[^:]*:50: Error: unshifted register required -- `bic r0,#12'
[^:]*:50: Error: unshifted register required -- `bic r0,r1,lsl#2'
[^:]*:50: Error: unshifted register required -- `bic r0,r1,lsl r3'
[^:]*:51: Error: dest must overlap one source register -- `eor r1,r2,r3'
[^:]*:51: Error: lo register required -- `eor r8,r0'
[^:]*:51: Error: lo register required -- `eor r0,r8'
[^:]*:51: Error: unshifted register required -- `eor r0,#12'
[^:]*:51: Error: unshifted register required -- `eor r0,r1,lsl#2'
[^:]*:51: Error: unshifted register required -- `eor r0,r1,lsl r3'
[^:]*:52: Error: dest must overlap one source register -- `orr r1,r2,r3'
[^:]*:52: Error: lo register required -- `orr r8,r0'
[^:]*:52: Error: lo register required -- `orr r0,r8'
[^:]*:52: Error: unshifted register required -- `orr r0,#12'
[^:]*:52: Error: unshifted register required -- `orr r0,r1,lsl#2'
[^:]*:52: Error: unshifted register required -- `orr r0,r1,lsl r3'
[^:]*:53: Error: dest and source1 must be the same register -- `sbc r1,r2,r3'
[^:]*:53: Error: lo register required -- `sbc r8,r0'
[^:]*:53: Error: lo register required -- `sbc r0,r8'
[^:]*:53: Error: unshifted register required -- `sbc r0,#12'
[^:]*:53: Error: unshifted register required -- `sbc r0,r1,lsl#2'
[^:]*:53: Error: unshifted register required -- `sbc r0,r1,lsl r3'
[^:]*:54: Error: dest must overlap one source register -- `mul r1,r2,r3'
[^:]*:54: Error: lo register required -- `mul r8,r0'
[^:]*:54: Error: lo register required -- `mul r0,r8'
[^:]*:62: Error: lo register required -- `asr r8,r0,#12'
[^:]*:62: Error: lo register required -- `asr r0,r8,#12'
[^:]*:62: Error: lo register required -- `asr r8,r0'
[^:]*:62: Error: lo register required -- `asr r0,r8'
[^:]*:63: Error: lo register required -- `lsl r8,r0,#12'
[^:]*:63: Error: lo register required -- `lsl r0,r8,#12'
[^:]*:63: Error: lo register required -- `lsl r8,r0'
[^:]*:63: Error: lo register required -- `lsl r0,r8'
[^:]*:64: Error: lo register required -- `lsr r8,r0,#12'
[^:]*:64: Error: lo register required -- `lsr r0,r8,#12'
[^:]*:64: Error: lo register required -- `lsr r8,r0'
[^:]*:64: Error: lo register required -- `lsr r0,r8'
[^:]*:65: Error: lo register required -- `ror r8,r0,#12'
[^:]*:65: Error: lo register required -- `ror r0,r8,#12'
[^:]*:65: Error: lo register required -- `ror r8,r0'
[^:]*:65: Error: lo register required -- `ror r0,r8'
[^:]*:66: Error: ror #imm not supported -- `ror r0,r1,#12'
[^:]*:69: Error: unshifted register required -- `add r0,r1,lsl#2'
[^:]*:70: Error: unshifted register required -- `add r0,r1,lsl r3'
[^:]*:71: Error: lo register required -- `add r8,r0,#1'
[^:]*:72: Error: lo register required -- `add r0,r8,#1'
[^:]*:73: Error: lo register required -- `add r8,#10'
[^:]*:74: Error: dest must overlap one source register -- `add r8,r1,r2'
[^:]*:75: Error: dest must overlap one source register -- `add r1,r8,r2'
[^:]*:76: Error: dest must overlap one source register -- `add r1,r2,r8'
[^:]*:77: Error: lo register required -- `add r8,pc,#4'
[^:]*:78: Error: lo register required -- `add r8,sp,#4'
[^:]*:80: Error: lo register required -- `sub r8,r0'
[^:]*:80: Error: lo register required -- `sub r0,r8'
[^:]*:80: Error: unshifted register required -- `sub r0,r1,lsl#2'
[^:]*:80: Error: unshifted register required -- `sub r0,r1,lsl r3'
[^:]*:81: Error: lo register required -- `sub r8,r0,#1'
[^:]*:82: Error: lo register required -- `sub r0,r8,#1'
[^:]*:83: Error: lo register required -- `sub r8,#10'
[^:]*:84: Error: lo register required -- `sub r8,r1,r2'
[^:]*:85: Error: lo register required -- `sub r1,r8,r2'
[^:]*:86: Error: lo register required -- `sub r1,r2,r8'
[^:]*:90: Error: only lo regs allowed with immediate -- `cmp r8,#255'
[^:]*:94: Error: only lo regs allowed with immediate -- `mov r8,#255'
[^:]*:106: Error: lo register required -- `ldr r8,\[r0\]'
[^:]*:106: Error: lo register required -- `ldr r0,\[r8\]'
[^:]*:106: Error: lo register required -- `ldr r0,\[r0,r8\]'
[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,#4\]!'
[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],#4'
[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,-r2\]'
[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],r2'
[^:]*:107: Error: lo register required -- `ldrb r8,\[r0\]'
[^:]*:107: Error: lo register required -- `ldrb r0,\[r8\]'
[^:]*:107: Error: lo register required -- `ldrb r0,\[r0,r8\]'
[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,#4\]!'
[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],#4'
[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,-r2\]'
[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],r2'
[^:]*:108: Error: lo register required -- `ldrh r8,\[r0\]'
[^:]*:108: Error: lo register required -- `ldrh r0,\[r8\]'
[^:]*:108: Error: lo register required -- `ldrh r0,\[r0,r8\]'
[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,#4\]!'
[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],#4'
[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,-r2\]'
[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],r2'
[^:]*:109: Error: lo register required -- `ldrsb r8,\[r0\]'
[^:]*:109: Error: lo register required -- `ldrsb r0,\[r8\]'
[^:]*:109: Error: lo register required -- `ldrsb r0,\[r0,r8\]'
[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,#4\]!'
[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],#4'
[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,-r2\]'
[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],r2'
[^:]*:110: Error: lo register required -- `ldrsh r8,\[r0\]'
[^:]*:110: Error: lo register required -- `ldrsh r0,\[r8\]'
[^:]*:110: Error: lo register required -- `ldrsh r0,\[r0,r8\]'
[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1,#4\]!'
[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1\],#4'
[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1,-r2\]'
[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1\],r2'
[^:]*:111: Error: lo register required -- `str r8,\[r0\]'
[^:]*:111: Error: lo register required -- `str r0,\[r8\]'
[^:]*:111: Error: lo register required -- `str r0,\[r0,r8\]'
[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1,#4\]!'
[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1\],#4'
[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1,-r2\]'
[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1\],r2'
[^:]*:112: Error: lo register required -- `strb r8,\[r0\]'
[^:]*:112: Error: lo register required -- `strb r0,\[r8\]'
[^:]*:112: Error: lo register required -- `strb r0,\[r0,r8\]'
[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1,#4\]!'
[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1\],#4'
[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1,-r2\]'
[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1\],r2'
[^:]*:113: Error: lo register required -- `strh r8,\[r0\]'
[^:]*:113: Error: lo register required -- `strh r0,\[r8\]'
[^:]*:113: Error: lo register required -- `strh r0,\[r0,r8\]'
[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1,#4\]!'
[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],#4'
[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1,-r2\]'
[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],r2'
[^:]*:115: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,r2,lsl#1\]'
[^:]*:116: Error: Thumb does not support this addressing mode -- `str r0,\[r1,r2,lsl#1\]'
[^:]*:119: Error: lo register required -- `ldmia r8!,{r1,r2}'
[^:]*:120: Error: lo register required -- `ldmia r7!,{r8}'
[^:]*:121: Warning: this instruction will write back the base register
[^:]*:122: Warning: this instruction will not write back the base register
[^:]*:124: Error: lo register required -- `stmia r8!,{r1,r2}'
[^:]*:125: Error: lo register required -- `stmia r7!,{r8}'
[^:]*:126: Warning: this instruction will write back the base register
[^:]*:127: Warning: value stored for r7 is UNPREDICTABLE
[^:]*:129: Error: invalid register list to push/pop instruction -- `push {r8,r9}'
[^:]*:130: Error: invalid register list to push/pop instruction -- `pop {r8,r9}'
[^:]*:133: Error: immediate value out of range -- `bkpt #257'
[^:]*:134: Error: Thumb does not support the 2-argument form of this instruction -- `cpsie ai,#5'
[^:]*:135: Error: Thumb does not support the 2-argument form of this instruction -- `cpsid ai,#5'
[^:]*:138: Error: Thumb does not support conditional execution

138
gas/testsuite/gas/arm/t16-bad.s Normal file
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@ -0,0 +1,138 @@
@ Things you can't do with 16-bit Thumb instructions, but you can
@ do with the equivalent ARM instruction. Does not include errors
@ caught by fixup processing (e.g. out-of-range immediates).
.text
.code 16
.thumb_func
l:
@ Arithmetic instruction templates
.macro ar2 opc
\opc r8,r0
\opc r0,r8
.endm
.macro ar2sh opc
ar2 \opc
\opc r0,#12
\opc r0,r1,lsl #2
\opc r0,r1,lsl r3
.endm
.macro ar2r opc
ar2 \opc
\opc r0,r1,ror #8
.endm
.macro ar3 opc
\opc r1,r2,r3
\opc r8,r0
\opc r0,r8
.endm
.macro ar3sh opc
ar3 \opc
\opc r0,#12
\opc r0,r1,lsl #2
\opc r0,r1,lsl r3
.endm
ar2sh tst
ar2sh cmn
ar2sh mvn
ar2 neg
ar2 rev
ar2 rev16
ar2 revsh
ar2r sxtb
ar2r sxth
ar2r uxtb
ar2r uxth
ar3sh adc
ar3sh and
ar3sh bic
ar3sh eor
ar3sh orr
ar3sh sbc
ar3 mul
@ Shift instruction template
.macro shift opc
\opc r8,r0,#12 @ form 1
\opc r0,r8,#12
ar2 \opc @ form 2
.endm
shift asr
shift lsl
shift lsr
shift ror
ror r0,r1,#12
@ add/sub/mov/cmp are idiosyncratic
add r0,r1,lsl #2
add r0,r1,lsl r3
add r8,r0,#1 @ form 1
add r0,r8,#1
add r8,#10 @ form 2
add r8,r1,r2 @ form 3
add r1,r8,r2
add r1,r2,r8
add r8,pc,#4 @ form 5
add r8,sp,#4 @ form 6
ar3sh sub
sub r8,r0,#1 @ form 1
sub r0,r8,#1
sub r8,#10 @ form 2
sub r8,r1,r2 @ form 3
sub r1,r8,r2
sub r1,r2,r8
cmp r0,r1,lsl #2
cmp r0,r1,lsl r3
cmp r8,#255
mov r0,r1,lsl #2
mov r0,r1,lsl r3
mov r8,#255
@ Load/store template
.macro ldst opc
\opc r8,[r0]
\opc r0,[r8]
\opc r0,[r0,r8]
\opc r0,[r1,#4]!
\opc r0,[r1],#4
\opc r0,[r1,-r2]
\opc r0,[r1],r2
.endm
ldst ldr
ldst ldrb
ldst ldrh
ldst ldrsb
ldst ldrsh
ldst str
ldst strb
ldst strh
ldr r0,[r1,r2,lsl #1]
str r0,[r1,r2,lsl #1]
@ Load/store multiple
ldmia r8!,{r1,r2}
ldmia r7!,{r8}
ldmia r7,{r1,r2}
ldmia r7!,{r1,r7}
stmia r8!,{r1,r2}
stmia r7!,{r8}
stmia r7,{r1,r2}
stmia r7!,{r1,r7}
push {r8,r9}
pop {r8,r9}
@ Miscellaneous
bkpt #257
cpsie ai,#5
cpsid ai,#5
@ Conditional suffixes
addeq r0,r1,r2

50
gas/testsuite/gas/arm/tcompat.d Normal file
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@ -0,0 +1,50 @@
#name: ARM Thumb-compat pseudos
#objdump: -dr --prefix-addresses --show-raw-insn
#as:
# Test the ARM pseudo instructions that exist for Thumb source compatibility
.*: +file format .*arm.*
Disassembly of section .text:
0+00 <[^>]*> 91a00000 ? movls r0, r0
0+04 <[^>]*> e1a09000 ? mov r9, r0
0+08 <[^>]*> e1a00009 ? mov r0, r9
0+0c <[^>]*> e1a0c00e ? mov ip, lr
0+10 <[^>]*> 91b09019 ? movlss r9, r9, lsl r0
0+14 <[^>]*> 91a00910 ? movls r0, r0, lsl r9
0+18 <[^>]*> e1b00880 ? movs r0, r0, lsl #17
0+1c <[^>]*> e1a00889 ? mov r0, r9, lsl #17
0+20 <[^>]*> 91b09039 ? movlss r9, r9, lsr r0
0+24 <[^>]*> 91a00930 ? movls r0, r0, lsr r9
0+28 <[^>]*> e1b008a0 ? movs r0, r0, lsr #17
0+2c <[^>]*> e1a008a9 ? mov r0, r9, lsr #17
0+30 <[^>]*> 91b09059 ? movlss r9, r9, asr r0
0+34 <[^>]*> 91a00950 ? movls r0, r0, asr r9
0+38 <[^>]*> e1b008c0 ? movs r0, r0, asr #17
0+3c <[^>]*> e1a008c9 ? mov r0, r9, asr #17
0+40 <[^>]*> 91b09079 ? movlss r9, r9, ror r0
0+44 <[^>]*> 91a00970 ? movls r0, r0, ror r9
0+48 <[^>]*> e1b008e0 ? movs r0, r0, ror #17
0+4c <[^>]*> e1a008e9 ? mov r0, r9, ror #17
0+50 <[^>]*> e2690000 ? rsb r0, r9, #0 ; 0x0
0+54 <[^>]*> e2709000 ? rsbs r9, r0, #0 ; 0x0
0+58 <[^>]*> 92600000 ? rsbls r0, r0, #0 ; 0x0
0+5c <[^>]*> 92799000 ? rsblss r9, r9, #0 ; 0x0
0+60 <[^>]*> e92d000e ? stmdb sp!, {r1, r2, r3}
0+64 <[^>]*> 992d8154 ? stmlsdb sp!, {r2, r4, r6, r8, pc}
0+68 <[^>]*> e8bd000e ? ldmia sp!, {r1, r2, r3}
0+6c <[^>]*> 98bd8154 ? ldmlsia sp!, {r2, r4, r6, r8, pc}
0+70 <[^>]*> e0000001 ? and r0, r0, r1
0+74 <[^>]*> e0200001 ? eor r0, r0, r1
0+78 <[^>]*> e0400001 ? sub r0, r0, r1
0+7c <[^>]*> e0600001 ? rsb r0, r0, r1
0+80 <[^>]*> e0800001 ? add r0, r0, r1
0+84 <[^>]*> e0a00001 ? adc r0, r0, r1
0+88 <[^>]*> e0c00001 ? sbc r0, r0, r1
0+8c <[^>]*> e0e00001 ? rsc r0, r0, r1
0+90 <[^>]*> e1800001 ? orr r0, r0, r1
0+94 <[^>]*> e1c00001 ? bic r0, r0, r1
0+98 <[^>]*> e0000091 ? mul r0, r1, r0
0+9c <[^>]*> e1a00000 ? nop \(mov r0,r0\)

45
gas/testsuite/gas/arm/tcompat.s Normal file
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@ -0,0 +1,45 @@
@ ARM instructions defined for source compatibility with Thumb.
.macro shift op opls ops oplss
\oplss r9,r0
\opls r0,r0,r9
\ops r0,#17
\op r0,r9,#17
.endm
.text
.global l
l:
cpyls r0,r0
cpy r9,r0
cpy r0,r9
cpy ip,lr
shift lsl lslls lsls lsllss
shift lsr lsrls lsrs lsrlss
shift asr asrls asrs asrlss
shift ror rorls rors rorlss
neg r0,r9
negs r9,r0
negls r0,r0
neglss r9,r9
push {r1,r2,r3}
pushls {r2,r4,r6,r8,pc}
pop {r1,r2,r3}
popls {r2,r4,r6,r8,pc}
@ Two-argument forms of ARM arithmetic instructions.
and r0,r1
eor r0,r1
sub r0,r1
rsb r0,r1
add r0,r1
adc r0,r1
sbc r0,r1
rsc r0,r1
orr r0,r1
bic r0,r1
mul r0,r1
nop

26
gas/testsuite/gas/arm/tcompat2.d Normal file
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@ -0,0 +1,26 @@
#name: Thumb ARM-compat pseudos
#objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb
#as:
# Test the Thumb pseudo instructions that exist for ARM source compatibility
.*: +file format .*arm.*
Disassembly of section .text:
0+00 <[^>]*> 4148 * adcs r0, r1
0+02 <[^>]*> 4148 * adcs r0, r1
0+04 <[^>]*> 4008 * ands r0, r1
0+06 <[^>]*> 4008 * ands r0, r1
0+08 <[^>]*> 4048 * eors r0, r1
0+0a <[^>]*> 4048 * eors r0, r1
0+0c <[^>]*> 4348 * muls r0, r1
0+0e <[^>]*> 4348 * muls r0, r1
0+10 <[^>]*> 4308 * orrs r0, r1
0+12 <[^>]*> 4308 * orrs r0, r1
0+14 <[^>]*> 4388 * bics r0, r1
0+16 <[^>]*> 4188 * sbcs r0, r1
0+18 <[^>]*> 46c0 * nop \(mov r8, r8\)
0+1a <[^>]*> 46c0 * nop \(mov r8, r8\)
0+1c <[^>]*> 46c0 * nop \(mov r8, r8\)
0+1e <[^>]*> 46c0 * nop \(mov r8, r8\)

32
gas/testsuite/gas/arm/tcompat2.s Normal file
View File

@ -0,0 +1,32 @@
@ Three-argument forms of Thumb arithmetic instructions.
@ Commutative instructions allow either the second or third
@ operand to equal the first.
.text
.global m
.thumb_func
m:
adc r0,r0,r1
adc r0,r1,r0
and r0,r0,r1
and r0,r1,r0
eor r0,r0,r1
eor r0,r1,r0
mul r0,r0,r1
mul r0,r1,r0
orr r0,r0,r1
orr r0,r1,r0
bic r0,r0,r1
sbc r0,r0,r1
@ section padding for a.out's sake
nop
nop
nop
nop

189
gas/testsuite/gas/arm/thumb.d Normal file
View File

@ -0,0 +1,189 @@
# name: Thumb instructions
# as: -mcpu=arm7t
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section \.text:
0+000 <[^>]+> 00ca lsls r2, r1, #3
0+002 <[^>]+> 0fe3 lsrs r3, r4, #31
0+004 <[^>]+> 1147 asrs r7, r0, #5
0+006 <[^>]+> 0011 lsls r1, r2, #0
0+008 <[^>]+> 0023 lsls r3, r4, #0
0+00a <[^>]+> 002c lsls r4, r5, #0
0+00c <[^>]+> 083e lsrs r6, r7, #32
0+00e <[^>]+> 1008 asrs r0, r1, #32
0+010 <[^>]+> 18d1 adds r1, r2, r3
0+012 <[^>]+> 1ca2 adds r2, r4, #2
0+014 <[^>]+> 1beb sub r3, r5, r7
0+016 <[^>]+> 1fe2 sub r2, r4, #7
0+018 <[^>]+> 24ff movs r4, #255
0+01a <[^>]+> 2bfa cmp r3, #250
0+01c <[^>]+> 367b adds r6, #123
0+01e <[^>]+> 3d80 subs r5, #128
0+020 <[^>]+> 402b ands r3, r5
0+022 <[^>]+> 4074 eors r4, r6
0+024 <[^>]+> 4081 lsls r1, r0
0+026 <[^>]+> 40da lsrs r2, r3
0+028 <[^>]+> 4134 asrs r4, r6
0+02a <[^>]+> 417d adcs r5, r7
0+02c <[^>]+> 41a0 sbcs r0, r4
0+02e <[^>]+> 41e1 rors r1, r4
0+030 <[^>]+> 422a tst r2, r5
0+032 <[^>]+> 4249 negs r1, r1
0+034 <[^>]+> 429a cmp r2, r3
0+036 <[^>]+> 42e1 cmn r1, r4
0+038 <[^>]+> 4318 orrs r0, r3
0+03a <[^>]+> 436c muls r4, r5
0+03c <[^>]+> 43bd bics r5, r7
0+03e <[^>]+> 43ed mvns r5, r5
0+040 <[^>]+> 4469 add r1, sp
0+042 <[^>]+> 4494 add ip, r2
0+044 <[^>]+> 44c9 add r9, r9
0+046 <[^>]+> 4571 cmp r1, lr
0+048 <[^>]+> 4580 cmp r8, r0
0+04a <[^>]+> 45f4 cmp ip, lr
0+04c <[^>]+> 4648 mov r0, r9
0+04e <[^>]+> 46a1 mov r9, r4
0+050 <[^>]+> 46c0 nop \(mov r8, r8\)
0+052 <[^>]+> 4738 bx r7
0+054 <[^>]+> 4740 bx r8
0+056 <[^>]+> 0000 lsls r0, r0, #0
0+058 <[^>]+> 4778 bx pc
0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] \(0+0dc <[^>]+>\)
0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] \(0+068 <[^>]+>\)
0+05e <[^>]+> 5088 str r0, \[r1, r2\]
0+060 <[^>]+> 5511 strb r1, \[r2, r4\]
0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\]
0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\]
\.\.\.
0+068 <[^>]+> 52d1 strh r1, \[r2, r3\]
0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\]
0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\]
0+06e <[^>]+> 5f42 ldrsh r2, \[r0, r5\]
0+070 <[^>]+> 67db str r3, \[r3, #124\]
0+072 <[^>]+> 6fe1 ldr r1, \[r4, #124\]
0+074 <[^>]+> 682d ldr r5, \[r5, #0\]
0+076 <[^>]+> 77e9 strb r1, \[r5, #31\]
0+078 <[^>]+> 7161 strb r1, \[r4, #5\]
0+07a <[^>]+> 7032 strb r2, \[r6, #0\]
0+07c <[^>]+> 87ec strh r4, \[r5, #62\]
0+07e <[^>]+> 8885 ldrh r5, \[r0, #4\]
0+080 <[^>]+> 8813 ldrh r3, \[r2, #0\]
0+082 <[^>]+> 93ff str r3, \[sp, #1020\]
0+084 <[^>]+> 990b ldr r1, \[sp, #44\]
0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\]
0+088 <[^>]+> a7ff add r7, pc, #1020 \(adr r7,0+488 <[^>]+>\)
0+08a <[^>]+> ac80 add r4, sp, #512
0+08c <[^>]+> b043 add sp, #268
0+08e <[^>]+> b09a sub sp, #104
0+090 <[^>]+> b0c3 sub sp, #268
0+092 <[^>]+> b01b add sp, #108
0+094 <[^>]+> b417 push {r0, r1, r2, r4}
0+096 <[^>]+> b5f9 push {r0, r3, r4, r5, r6, r7, lr}
0+098 <[^>]+> bc98 pop {r3, r4, r7}
0+09a <[^>]+> bdff pop {r0, r1, r2, r3, r4, r5, r6, r7, pc}
0+09c <[^>]+> c3f3 stmia r3!, {r0, r1, r4, r5, r6, r7}
0+09e <[^>]+> c8fe ldmia r0!, {r1, r2, r3, r4, r5, r6, r7}
0+0a0 <[^>]+> d0e2 beq.n 0+068 <[^>]+>
0+0a2 <[^>]+> d1e1 bne.n 0+068 <[^>]+>
0+0a4 <[^>]+> d2e0 bcs.n 0+068 <[^>]+>
0+0a6 <[^>]+> d3df bcc.n 0+068 <[^>]+>
0+0a8 <[^>]+> d4de bmi.n 0+068 <[^>]+>
0+0aa <[^>]+> d5dd bpl.n 0+068 <[^>]+>
0+0ac <[^>]+> d6dc bvs.n 0+068 <[^>]+>
0+0ae <[^>]+> d7db bvc.n 0+068 <[^>]+>
0+0b0 <[^>]+> d8da bhi.n 0+068 <[^>]+>
0+0b2 <[^>]+> d9d9 bls.n 0+068 <[^>]+>
0+0b4 <[^>]+> dad8 bge.n 0+068 <[^>]+>
0+0b6 <[^>]+> dcd7 bgt.n 0+068 <[^>]+>
0+0b8 <[^>]+> dbd6 blt.n 0+068 <[^>]+>
0+0ba <[^>]+> dcd5 bgt.n 0+068 <[^>]+>
0+0bc <[^>]+> ddd4 ble.n 0+068 <[^>]+>
0+0be <[^>]+> d8d3 bhi.n 0+068 <[^>]+>
0+0c0 <[^>]+> d3d2 bcc.n 0+068 <[^>]+>
0+0c2 <[^>]+> d3d1 bcc.n 0+068 <[^>]+>
0+0c4 <[^>]+> e7d0 b.n 0+068 <[^>]+>
0+0c6 <[^>]+> 00ac lsls r4, r5, #2
0+0c8 <[^>]+> 1c9a adds r2, r3, #2
0+0ca <[^>]+> b07f add sp, #508
0+0cc <[^>]+> b0ff sub sp, #508
0+0ce <[^>]+> a8ff add r0, sp, #1020
0+0d0 <[^>]+> a0ff add r0, pc, #1020 \(adr r0,0+4d0 <[^>]+>\)
0+0d2 <[^>]+> b01a add sp, #104
0+0d4 <[^>]+> b09a sub sp, #104
0+0d6 <[^>]+> a81a add r0, sp, #104
0+0d8 <[^>]+> a01a add r0, pc, #104 \(adr r0,0+144 <[^>]+>\)
0+0da <[^>]+> 3168 adds r1, #104
0+0dc <[^>]+> 2668 movs r6, #104
0+0de <[^>]+> 2f68 cmp r7, #104
0+0e0 <[^>]+> 46c0 nop \(mov r8, r8\)
0+0e2 <[^>]+> 46c0 nop \(mov r8, r8\)
0+0e4 <[^>]+> ea000037 b 0+0e4 <[^>]+>
e4: R_ARM_PC24 \.text
0+0e8 <[^>]+> eafffffe b 0+000 <[^>]+>
e8: R_ARM_PC24 \.wombat
0+0ec <[^>]+> eb000037 bl 0+0e4 <[^>]+>
ec: R_ARM_PC24 \.text
0+0f0 <[^>]+> ebfffffe bl 0+000 <[^>]+>
f0: R_ARM_PC24 \.wombat
0+0f4 <[^>]+> e12fff10 bx r0
0+0f8 <[^>]+> ef123456 swi 0x00123456
0+0fc <[^>]+> a004 add r0, pc, #16 \(adr r0,0+110 <[^>]+>\)
0+0fe <[^>]+> e77f b.n 0+000 <[^>]+>
0+100 <[^>]+> e7fe b.n 0+000 <[^>]+>
100: R_ARM_THM_JUMP11 \.wombat
0+102 <[^>]+> f7ff fffe bl 0+000 <[^>]+>
102: R_ARM_THM_CALL \.text
0+106 <[^>]+> f7ff fffe bl 0+000 <[^>]+>
106: R_ARM_THM_CALL \.wombat
0+10a <[^>]+> 4700 bx r0
0+10c <[^>]+> dfff swi 255
\.\.\.
0+110 <[^>]+> d0fe beq.n 0+000 <[^>]+>
110: R_ARM_THM_JUMP8 \.wombat
0+112 <[^>]+> d1fe bne.n 0+000 <[^>]+>
112: R_ARM_THM_JUMP8 \.wombat
0+114 <[^>]+> d2fe bcs.n 0+000 <[^>]+>
114: R_ARM_THM_JUMP8 \.wombat
0+116 <[^>]+> d3fe bcc.n 0+000 <[^>]+>
116: R_ARM_THM_JUMP8 \.wombat
0+118 <[^>]+> d4fe bmi.n 0+000 <[^>]+>
118: R_ARM_THM_JUMP8 \.wombat
0+11a <[^>]+> d5fe bpl.n 0+000 <[^>]+>
11a: R_ARM_THM_JUMP8 \.wombat
0+11c <[^>]+> d6fe bvs.n 0+000 <[^>]+>
11c: R_ARM_THM_JUMP8 \.wombat
0+11e <[^>]+> d7fe bvc.n 0+000 <[^>]+>
11e: R_ARM_THM_JUMP8 \.wombat
0+120 <[^>]+> d8fe bhi.n 0+000 <[^>]+>
120: R_ARM_THM_JUMP8 \.wombat
0+122 <[^>]+> d9fe bls.n 0+000 <[^>]+>
122: R_ARM_THM_JUMP8 \.wombat
0+124 <[^>]+> dafe bge.n 0+000 <[^>]+>
124: R_ARM_THM_JUMP8 \.wombat
0+126 <[^>]+> dcfe bgt.n 0+000 <[^>]+>
126: R_ARM_THM_JUMP8 \.wombat
0+128 <[^>]+> dbfe blt.n 0+000 <[^>]+>
128: R_ARM_THM_JUMP8 \.wombat
0+12a <[^>]+> dcfe bgt.n 0+000 <[^>]+>
12a: R_ARM_THM_JUMP8 \.wombat
0+12c <[^>]+> ddfe ble.n 0+000 <[^>]+>
12c: R_ARM_THM_JUMP8 \.wombat
0+12e <[^>]+> d8fe bhi.n 0+000 <[^>]+>
12e: R_ARM_THM_JUMP8 \.wombat
0+130 <[^>]+> d3fe bcc.n 0+000 <[^>]+>
130: R_ARM_THM_JUMP8 \.wombat
0+132 <[^>]+> d3fe bcc.n 0+000 <[^>]+>
132: R_ARM_THM_JUMP8 \.wombat
0+134 <[^>]+> f000 fc9a bl 0+938 <[^>]+>
134: R_ARM_THM_CALL \.text
\.\.\.
0+938 <[^>]+> f000 f898 bl 0+134 <[^>]+>
938: R_ARM_THM_CALL \.text
0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+944 <[^>]+>\)
0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+944 <[^>]+>\)
0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+948 <[^>]+>\)
0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+948 <[^>]+>\)
0+944 <[^>]+> 46c0 nop \(mov r8, r8\)
0+946 <[^>]+> 46c0 nop \(mov r8, r8\)

8
gas/testsuite/gas/arm/thumb.s
View File

@ -192,3 +192,11 @@ forwardonly:
.space (1 << 11) @ leave space to force long offsets
.local:
bl .back
ldr r0, .target
ldr r0, .target
ldr r0, [pc, #4]
ldr r0, [pc, #4]
.target:
nop @ pad for a.out
nop

995
gas/testsuite/gas/arm/thumb32.d Normal file
View File

@ -0,0 +1,995 @@
# name: 32-bit Thumb instructions
# as: -march=armv6kt2
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
0+000 <[^>]+> f041 0000 orr\.w r0, r1, #0 ; 0x0
0+004 <[^>]+> f041 00a5 orr\.w r0, r1, #165 ; 0xa5
0+008 <[^>]+> f041 10a5 orr\.w r0, r1, #10813605 ; 0xa500a5
0+00c <[^>]+> f041 20a5 orr\.w r0, r1, #2768282880 ; 0xa500a500
0+010 <[^>]+> f041 30a5 orr\.w r0, r1, #2779096485 ; 0xa5a5a5a5
0+014 <[^>]+> f041 4000 orr\.w r0, r1, #2147483648 ; 0x80000000
0+018 <[^>]+> f041 4080 orr\.w r0, r1, #1073741824 ; 0x40000000
0+01c <[^>]+> f041 4020 orr\.w r0, r1, #2684354560 ; 0xa0000000
0+020 <[^>]+> f041 40a0 orr\.w r0, r1, #1342177280 ; 0x50000000
0+024 <[^>]+> f041 5020 orr\.w r0, r1, #671088640 ; 0x28000000
0+028 <[^>]+> f041 4014 orr\.w r0, r1, #2483027968 ; 0x94000000
0+02c <[^>]+> f041 4094 orr\.w r0, r1, #1241513984 ; 0x4a000000
0+030 <[^>]+> f041 4025 orr\.w r0, r1, #2768240640 ; 0xa5000000
0+034 <[^>]+> f041 40a5 orr\.w r0, r1, #1384120320 ; 0x52800000
0+038 <[^>]+> f041 5025 orr\.w r0, r1, #692060160 ; 0x29400000
0+03c <[^>]+> f041 50a5 orr\.w r0, r1, #346030080 ; 0x14a00000
0+040 <[^>]+> f041 6025 orr\.w r0, r1, #173015040 ; 0xa500000
0+044 <[^>]+> f041 60a5 orr\.w r0, r1, #86507520 ; 0x5280000
0+048 <[^>]+> f041 7025 orr\.w r0, r1, #43253760 ; 0x2940000
0+04c <[^>]+> f041 70a5 orr\.w r0, r1, #21626880 ; 0x14a0000
0+050 <[^>]+> f441 0025 orr\.w r0, r1, #10813440 ; 0xa50000
0+054 <[^>]+> f441 00a5 orr\.w r0, r1, #5406720 ; 0x528000
0+058 <[^>]+> f441 1025 orr\.w r0, r1, #2703360 ; 0x294000
0+05c <[^>]+> f441 10a5 orr\.w r0, r1, #1351680 ; 0x14a000
0+060 <[^>]+> f441 2025 orr\.w r0, r1, #675840 ; 0xa5000
0+064 <[^>]+> f441 20a5 orr\.w r0, r1, #337920 ; 0x52800
0+068 <[^>]+> f441 3025 orr\.w r0, r1, #168960 ; 0x29400
0+06c <[^>]+> f441 30a5 orr\.w r0, r1, #84480 ; 0x14a00
0+070 <[^>]+> f441 4025 orr\.w r0, r1, #42240 ; 0xa500
0+074 <[^>]+> f441 40a5 orr\.w r0, r1, #21120 ; 0x5280
0+078 <[^>]+> f441 5025 orr\.w r0, r1, #10560 ; 0x2940
0+07c <[^>]+> f441 50a5 orr\.w r0, r1, #5280 ; 0x14a0
0+080 <[^>]+> f441 6025 orr\.w r0, r1, #2640 ; 0xa50
0+084 <[^>]+> f441 60a5 orr\.w r0, r1, #1320 ; 0x528
0+088 <[^>]+> f441 7025 orr\.w r0, r1, #660 ; 0x294
0+08c <[^>]+> f441 70a5 orr\.w r0, r1, #330 ; 0x14a
0+090 <[^>]+> f110 0000 adds\.w r0, r0, #0 ; 0x0
0+094 <[^>]+> f110 0500 adds\.w r5, r0, #0 ; 0x0
0+098 <[^>]+> f115 0000 adds\.w r0, r5, #0 ; 0x0
0+09c <[^>]+> f110 0005 adds\.w r0, r0, #5 ; 0x5
0+0a0 <[^>]+> f110 0081 adds\.w r0, r0, #129 ; 0x81
0+0a4 <[^>]+> f110 0081 adds\.w r0, r0, #129 ; 0x81
0+0a8 <[^>]+> f110 057e adds\.w r5, r0, #126 ; 0x7e
0+0ac <[^>]+> 1800 adds r0, r0, r0
0+0ae <[^>]+> 1805 adds r5, r0, r0
0+0b0 <[^>]+> 1828 adds r0, r5, r0
0+0b2 <[^>]+> 1940 adds r0, r0, r5
0+0b4 <[^>]+> 18d1 adds r1, r2, r3
0+0b6 <[^>]+> 4480 add r8, r0
0+0b8 <[^>]+> 4440 add r0, r8
0+0ba <[^>]+> 4440 add r0, r8
0+0bc <[^>]+> 4440 add r0, r8
0+0be <[^>]+> eb00 0800 add\.w r8, r0, r0
0+0c2 <[^>]+> 4401 add r1, r0
0+0c4 <[^>]+> 4408 add r0, r1
0+0c6 <[^>]+> f10f 0000 add\.w r0, pc, #0 ; 0x0
0+0ca <[^>]+> f10f 0500 add\.w r5, pc, #0 ; 0x0
0+0ce <[^>]+> f50f 7001 add\.w r0, pc, #516 ; 0x204
0+0d2 <[^>]+> f10d 0000 add\.w r0, sp, #0 ; 0x0
0+0d6 <[^>]+> f10d 0500 add\.w r5, sp, #0 ; 0x0
0+0da <[^>]+> f50d 7001 add\.w r0, sp, #516 ; 0x204
0+0de <[^>]+> f100 0d00 add\.w sp, r0, #0 ; 0x0
0+0e2 <[^>]+> f10d 0d00 add\.w sp, sp, #0 ; 0x0
0+0e6 <[^>]+> f500 7d82 add\.w sp, r0, #260 ; 0x104
0+0ea <[^>]+> f100 0000 add\.w r0, r0, #0 ; 0x0
0+0ee <[^>]+> f110 0000 adds\.w r0, r0, #0 ; 0x0
0+0f2 <[^>]+> f100 0900 add\.w r9, r0, #0 ; 0x0
0+0f6 <[^>]+> f109 0000 add\.w r0, r9, #0 ; 0x0
0+0fa <[^>]+> f100 0081 add\.w r0, r0, #129 ; 0x81
0+0fe <[^>]+> eb00 0000 add\.w r0, r0, r0
0+102 <[^>]+> eb10 0000 adds\.w r0, r0, r0
0+106 <[^>]+> eb00 0900 add\.w r9, r0, r0
0+10a <[^>]+> eb09 0000 add\.w r0, r9, r0
0+10e <[^>]+> eb00 0009 add\.w r0, r0, r9
0+112 <[^>]+> eb09 080a add\.w r8, r9, sl
0+116 <[^>]+> eb09 484a add\.w r8, r9, sl, lsl #17
0+11a <[^>]+> eb08 081a add\.w r8, r8, sl, lsr #32
0+11e <[^>]+> eb08 485a add\.w r8, r8, sl, lsr #17
0+122 <[^>]+> eb09 082a add\.w r8, r9, sl, asr #32
0+126 <[^>]+> eb09 486a add\.w r8, r9, sl, asr #17
0+12a <[^>]+> eb09 083a add\.w r8, r9, sl, rrx
0+12e <[^>]+> eb09 487a add\.w r8, r9, sl, ror #17
0+132 <[^>]+> f1b0 0000 subs\.w r0, r0, #0 ; 0x0
0+136 <[^>]+> f1b0 0500 subs\.w r5, r0, #0 ; 0x0
0+13a <[^>]+> f1b5 0000 subs\.w r0, r5, #0 ; 0x0
0+13e <[^>]+> f1b0 0005 subs\.w r0, r0, #5 ; 0x5
0+142 <[^>]+> f1b0 0081 subs\.w r0, r0, #129 ; 0x81
0+146 <[^>]+> f1b0 0508 subs\.w r5, r0, #8 ; 0x8
0+14a <[^>]+> 1a00 sub r0, r0, r0
0+14c <[^>]+> 1a05 sub r5, r0, r0
0+14e <[^>]+> 1a28 sub r0, r5, r0
0+150 <[^>]+> 1b40 sub r0, r0, r5
0+152 <[^>]+> f5a0 7d82 sub\.w sp, r0, #260 ; 0x104
0+156 <[^>]+> f5ad 7d82 sub\.w sp, sp, #260 ; 0x104
0+15a <[^>]+> ebb8 0800 subs\.w r8, r8, r0
0+15e <[^>]+> ebb0 0008 subs\.w r0, r0, r8
0+162 <[^>]+> f5b0 7082 subs\.w r0, r0, #260 ; 0x104
0+166 <[^>]+> 4140 adcs r0, r0
0+168 <[^>]+> 4145 adcs r5, r0
0+16a <[^>]+> 4168 adcs r0, r5
0+16c <[^>]+> 4168 adcs r0, r5
0+16e <[^>]+> 4168 adcs r0, r5
0+170 <[^>]+> eb45 0000 adc\.w r0, r5, r0
0+174 <[^>]+> eb41 0002 adc\.w r0, r1, r2
0+178 <[^>]+> eb40 0900 adc\.w r9, r0, r0
0+17c <[^>]+> eb49 0000 adc\.w r0, r9, r0
0+180 <[^>]+> eb40 0009 adc\.w r0, r0, r9
0+184 <[^>]+> eb50 0000 adcs\.w r0, r0, r0
0+188 <[^>]+> eb41 4062 adc\.w r0, r1, r2, asr #17
0+18c <[^>]+> f141 0081 adc\.w r0, r1, #129 ; 0x81
0+190 <[^>]+> 4000 ands r0, r0
0+192 <[^>]+> 4005 ands r5, r0
0+194 <[^>]+> 4028 ands r0, r5
0+196 <[^>]+> 4028 ands r0, r5
0+198 <[^>]+> 4028 ands r0, r5
0+19a <[^>]+> ea05 0000 and\.w r0, r5, r0
0+19e <[^>]+> ea01 0002 and\.w r0, r1, r2
0+1a2 <[^>]+> ea00 0900 and\.w r9, r0, r0
0+1a6 <[^>]+> ea09 0000 and\.w r0, r9, r0
0+1aa <[^>]+> ea00 0009 and\.w r0, r0, r9
0+1ae <[^>]+> ea10 0000 ands\.w r0, r0, r0
0+1b2 <[^>]+> ea01 4062 and\.w r0, r1, r2, asr #17
0+1b6 <[^>]+> f001 0081 and\.w r0, r1, #129 ; 0x81
0+1ba <[^>]+> 4380 bics r0, r0
0+1bc <[^>]+> 4385 bics r5, r0
0+1be <[^>]+> 43a8 bics r0, r5
0+1c0 <[^>]+> 43a8 bics r0, r5
0+1c2 <[^>]+> ea35 0000 bics\.w r0, r5, r0
0+1c6 <[^>]+> ea25 0000 bic\.w r0, r5, r0
0+1ca <[^>]+> ea21 0002 bic\.w r0, r1, r2
0+1ce <[^>]+> ea20 0900 bic\.w r9, r0, r0
0+1d2 <[^>]+> ea29 0000 bic\.w r0, r9, r0
0+1d6 <[^>]+> ea20 0009 bic\.w r0, r0, r9
0+1da <[^>]+> ea30 0000 bics\.w r0, r0, r0
0+1de <[^>]+> ea21 4062 bic\.w r0, r1, r2, asr #17
0+1e2 <[^>]+> f021 0081 bic\.w r0, r1, #129 ; 0x81
0+1e6 <[^>]+> 4040 eors r0, r0
0+1e8 <[^>]+> 4045 eors r5, r0
0+1ea <[^>]+> 4068 eors r0, r5
0+1ec <[^>]+> 4068 eors r0, r5
0+1ee <[^>]+> 4068 eors r0, r5
0+1f0 <[^>]+> ea85 0000 eor\.w r0, r5, r0
0+1f4 <[^>]+> ea81 0002 eor\.w r0, r1, r2
0+1f8 <[^>]+> ea80 0900 eor\.w r9, r0, r0
0+1fc <[^>]+> ea89 0000 eor\.w r0, r9, r0
0+200 <[^>]+> ea80 0009 eor\.w r0, r0, r9
0+204 <[^>]+> ea90 0000 eors\.w r0, r0, r0
0+208 <[^>]+> ea81 4062 eor\.w r0, r1, r2, asr #17
0+20c <[^>]+> f081 0081 eor\.w r0, r1, #129 ; 0x81
0+210 <[^>]+> 4300 orrs r0, r0
0+212 <[^>]+> 4305 orrs r5, r0
0+214 <[^>]+> 4328 orrs r0, r5
0+216 <[^>]+> 4328 orrs r0, r5
0+218 <[^>]+> 4328 orrs r0, r5
0+21a <[^>]+> ea45 0000 orr\.w r0, r5, r0
0+21e <[^>]+> ea41 0002 orr\.w r0, r1, r2
0+222 <[^>]+> ea40 0900 orr\.w r9, r0, r0
0+226 <[^>]+> ea49 0000 orr\.w r0, r9, r0
0+22a <[^>]+> ea40 0009 orr\.w r0, r0, r9
0+22e <[^>]+> ea50 0000 orrs\.w r0, r0, r0
0+232 <[^>]+> ea41 4062 orr\.w r0, r1, r2, asr #17
0+236 <[^>]+> f041 0081 orr\.w r0, r1, #129 ; 0x81
0+23a <[^>]+> ebd0 0000 rsbs r0, r0, r0
0+23e <[^>]+> ebd5 0500 rsbs r5, r5, r0
0+242 <[^>]+> ebd0 0005 rsbs r0, r0, r5
0+246 <[^>]+> ebd0 0005 rsbs r0, r0, r5
0+24a <[^>]+> ebd5 0000 rsbs r0, r5, r0
0+24e <[^>]+> ebc5 0000 rsb r0, r5, r0
0+252 <[^>]+> ebc1 0002 rsb r0, r1, r2
0+256 <[^>]+> ebc0 0900 rsb r9, r0, r0
0+25a <[^>]+> ebc9 0000 rsb r0, r9, r0
0+25e <[^>]+> ebc0 0009 rsb r0, r0, r9
0+262 <[^>]+> ebd0 0000 rsbs r0, r0, r0
0+266 <[^>]+> ebc1 4062 rsb r0, r1, r2, asr #17
0+26a <[^>]+> f1c1 0081 rsb r0, r1, #129 ; 0x81
0+26e <[^>]+> 4180 sbcs r0, r0
0+270 <[^>]+> 4185 sbcs r5, r0
0+272 <[^>]+> 41a8 sbcs r0, r5
0+274 <[^>]+> 41a8 sbcs r0, r5
0+276 <[^>]+> eb75 0000 sbcs\.w r0, r5, r0
0+27a <[^>]+> eb65 0000 sbc\.w r0, r5, r0
0+27e <[^>]+> eb61 0002 sbc\.w r0, r1, r2
0+282 <[^>]+> eb60 0900 sbc\.w r9, r0, r0
0+286 <[^>]+> eb69 0000 sbc\.w r0, r9, r0
0+28a <[^>]+> eb60 0009 sbc\.w r0, r0, r9
0+28e <[^>]+> eb70 0000 sbcs\.w r0, r0, r0
0+292 <[^>]+> eb61 4062 sbc\.w r0, r1, r2, asr #17
0+296 <[^>]+> f161 0081 sbc\.w r0, r1, #129 ; 0x81
0+29a <[^>]+> f36f 0000 bfc r0, #0, #1
0+29e <[^>]+> f36f 0900 bfc r9, #0, #1
0+2a2 <[^>]+> f36f 0900 bfc r9, #0, #1
0+2a6 <[^>]+> f36f 5055 bfc r0, #21, #1
0+2aa <[^>]+> f36f 0011 bfc r0, #0, #18
0+2ae <[^>]+> f360 0000 bfi r0, r0, #0, #1
0+2b2 <[^>]+> f360 0900 bfi r9, r0, #0, #1
0+2b6 <[^>]+> f369 0000 bfi r0, r9, #0, #1
0+2ba <[^>]+> f360 5055 bfi r0, r0, #21, #1
0+2be <[^>]+> f360 0011 bfi r0, r0, #0, #18
0+2c2 <[^>]+> f340 0000 sbfx r0, r0, #0, #1
0+2c6 <[^>]+> f3c0 0900 ubfx r9, r0, #0, #1
0+2ca <[^>]+> f349 0000 sbfx r0, r9, #0, #1
0+2ce <[^>]+> f3c0 5040 ubfx r0, r0, #21, #1
0+2d2 <[^>]+> f340 0011 sbfx r0, r0, #0, #18
0+2d6 <[^>]+> d0fe beq\.n 0+2d6 <[^>]+>
0+2d8 <[^>]+> d02a beq\.n 0+330 <[^>]+>
0+2da <[^>]+> d1fc bne\.n 0+2d6 <[^>]+>
0+2dc <[^>]+> d128 bne\.n 0+330 <[^>]+>
0+2de <[^>]+> d2fa bcs\.n 0+2d6 <[^>]+>
0+2e0 <[^>]+> d226 bcs\.n 0+330 <[^>]+>
0+2e2 <[^>]+> d2f8 bcs\.n 0+2d6 <[^>]+>
0+2e4 <[^>]+> d224 bcs\.n 0+330 <[^>]+>
0+2e6 <[^>]+> d3f6 bcc\.n 0+2d6 <[^>]+>
0+2e8 <[^>]+> d322 bcc\.n 0+330 <[^>]+>
0+2ea <[^>]+> d3f4 bcc\.n 0+2d6 <[^>]+>
0+2ec <[^>]+> d320 bcc\.n 0+330 <[^>]+>
0+2ee <[^>]+> d3f2 bcc\.n 0+2d6 <[^>]+>
0+2f0 <[^>]+> d31e bcc\.n 0+330 <[^>]+>
0+2f2 <[^>]+> d4f0 bmi\.n 0+2d6 <[^>]+>
0+2f4 <[^>]+> d41c bmi\.n 0+330 <[^>]+>
0+2f6 <[^>]+> d5ee bpl\.n 0+2d6 <[^>]+>
0+2f8 <[^>]+> d51a bpl\.n 0+330 <[^>]+>
0+2fa <[^>]+> d6ec bvs\.n 0+2d6 <[^>]+>
0+2fc <[^>]+> d618 bvs\.n 0+330 <[^>]+>
0+2fe <[^>]+> d7ea bvc\.n 0+2d6 <[^>]+>
0+300 <[^>]+> d716 bvc\.n 0+330 <[^>]+>
0+302 <[^>]+> d8e8 bhi\.n 0+2d6 <[^>]+>
0+304 <[^>]+> d814 bhi\.n 0+330 <[^>]+>
0+306 <[^>]+> d9e6 bls\.n 0+2d6 <[^>]+>
0+308 <[^>]+> d912 bls\.n 0+330 <[^>]+>
0+30a <[^>]+> d7e4 bvc\.n 0+2d6 <[^>]+>
0+30c <[^>]+> d710 bvc\.n 0+330 <[^>]+>
0+30e <[^>]+> d8e2 bhi\.n 0+2d6 <[^>]+>
0+310 <[^>]+> d80e bhi\.n 0+330 <[^>]+>
0+312 <[^>]+> d9e0 bls\.n 0+2d6 <[^>]+>
0+314 <[^>]+> d90c bls\.n 0+330 <[^>]+>
0+316 <[^>]+> dade bge\.n 0+2d6 <[^>]+>
0+318 <[^>]+> da0a bge\.n 0+330 <[^>]+>
0+31a <[^>]+> dbdc blt\.n 0+2d6 <[^>]+>
0+31c <[^>]+> db08 blt\.n 0+330 <[^>]+>
0+31e <[^>]+> dcda bgt\.n 0+2d6 <[^>]+>
0+320 <[^>]+> dc06 bgt\.n 0+330 <[^>]+>
0+322 <[^>]+> ddd8 ble\.n 0+2d6 <[^>]+>
0+324 <[^>]+> dd04 ble\.n 0+330 <[^>]+>
0+326 <[^>]+> e7d6 b\.n 0+2d6 <[^>]+>
0+328 <[^>]+> e002 b\.n 0+330 <[^>]+>
0+32a <[^>]+> e7d4 b\.n 0+2d6 <[^>]+>
0+32c <[^>]+> e000 b\.n 0+330 <[^>]+>
0+32e <[^>]+> 46c0 nop \(mov r8, r8\)
0+330 <[^>]+> f43f affe beq\.w 0+330 <[^>]+>
0+334 <[^>]+> f000 8058 beq\.w 0+3e8 <[^>]+>
0+338 <[^>]+> f47f affa bne\.w 0+330 <[^>]+>
0+33c <[^>]+> f040 8054 bne\.w 0+3e8 <[^>]+>
0+340 <[^>]+> f4bf aff6 bcs\.w 0+330 <[^>]+>
0+344 <[^>]+> f080 8050 bcs\.w 0+3e8 <[^>]+>
0+348 <[^>]+> f4bf aff2 bcs\.w 0+330 <[^>]+>
0+34c <[^>]+> f080 804c bcs\.w 0+3e8 <[^>]+>
0+350 <[^>]+> f4ff afee bcc\.w 0+330 <[^>]+>
0+354 <[^>]+> f0c0 8048 bcc\.w 0+3e8 <[^>]+>
0+358 <[^>]+> f4ff afea bcc\.w 0+330 <[^>]+>
0+35c <[^>]+> f0c0 8044 bcc\.w 0+3e8 <[^>]+>
0+360 <[^>]+> f4ff afe6 bcc\.w 0+330 <[^>]+>
0+364 <[^>]+> f0c0 8040 bcc\.w 0+3e8 <[^>]+>
0+368 <[^>]+> f53f afe2 bmi\.w 0+330 <[^>]+>
0+36c <[^>]+> f100 803c bmi\.w 0+3e8 <[^>]+>
0+370 <[^>]+> f57f afde bpl\.w 0+330 <[^>]+>
0+374 <[^>]+> f140 8038 bpl\.w 0+3e8 <[^>]+>
0+378 <[^>]+> f5bf afda bvs\.w 0+330 <[^>]+>
0+37c <[^>]+> f180 8034 bvs\.w 0+3e8 <[^>]+>
0+380 <[^>]+> f5ff afd6 bvc\.w 0+330 <[^>]+>
0+384 <[^>]+> f1c0 8030 bvc\.w 0+3e8 <[^>]+>
0+388 <[^>]+> f63f afd2 bhi\.w 0+330 <[^>]+>
0+38c <[^>]+> f200 802c bhi\.w 0+3e8 <[^>]+>
0+390 <[^>]+> f67f afce bls\.w 0+330 <[^>]+>
0+394 <[^>]+> f240 8028 bls\.w 0+3e8 <[^>]+>
0+398 <[^>]+> f5ff afca bvc\.w 0+330 <[^>]+>
0+39c <[^>]+> f1c0 8024 bvc\.w 0+3e8 <[^>]+>
0+3a0 <[^>]+> f63f afc6 bhi\.w 0+330 <[^>]+>
0+3a4 <[^>]+> f200 8020 bhi\.w 0+3e8 <[^>]+>
0+3a8 <[^>]+> f67f afc2 bls\.w 0+330 <[^>]+>
0+3ac <[^>]+> f240 801c bls\.w 0+3e8 <[^>]+>
0+3b0 <[^>]+> f6bf afbe bge\.w 0+330 <[^>]+>
0+3b4 <[^>]+> f280 8018 bge\.w 0+3e8 <[^>]+>
0+3b8 <[^>]+> f6ff afba blt\.w 0+330 <[^>]+>
0+3bc <[^>]+> f2c0 8014 blt\.w 0+3e8 <[^>]+>
0+3c0 <[^>]+> f73f afb6 bgt\.w 0+330 <[^>]+>
0+3c4 <[^>]+> f300 8010 bgt\.w 0+3e8 <[^>]+>
0+3c8 <[^>]+> f77f afb2 ble\.w 0+330 <[^>]+>
0+3cc <[^>]+> f340 800c ble\.w 0+3e8 <[^>]+>
0+3d0 <[^>]+> f7ff bfae b\.w 0+330 <[^>]+>
0+3d4 <[^>]+> f000 b808 b\.w 0+3e8 <[^>]+>
0+3d8 <[^>]+> f000 f996 bl 0+330 <[^>]+>
3d8: R_ARM_THM_CALL \.text
0+3dc <[^>]+> f000 f9f2 bl 0+3e8 <[^>]+>
3dc: R_ARM_THM_CALL \.text
0+3e0 <[^>]+> f000 e996 blx 0+330 <[^>]+>
3e0: R_ARM_THM_XPC22 \.text
0+3e4 <[^>]+> f000 e9f2 blx 0+3e8 <[^>]+>
3e4: R_ARM_THM_XPC22 \.text
0+3e8 <[^>]+> 4748 bx r9
0+3ea <[^>]+> 4780 blx r0
0+3ec <[^>]+> 47c8 blx r9
0+3ee <[^>]+> f3c0 8f00 bxj r0
0+3f2 <[^>]+> f3c9 8f00 bxj r9
0+3f6 <[^>]+> fab0 f080 clz r0, r0
0+3fa <[^>]+> fab0 f980 clz r9, r0
0+3fe <[^>]+> fab9 f089 clz r0, r9
0+402 <[^>]+> b661 cpsie f
0+404 <[^>]+> b672 cpsid i
0+406 <[^>]+> b664 cpsie a
0+408 <[^>]+> f3af 8620 cpsid\.w f
0+40c <[^>]+> f3af 8440 cpsie\.w i
0+410 <[^>]+> f3af 8680 cpsid\.w a
0+414 <[^>]+> f3af 8540 cpsie i, #0
0+418 <[^>]+> f3af 8751 cpsid i, #17
0+41c <[^>]+> f3af 8100 cps #0
0+420 <[^>]+> f3af 8111 cps #17
0+424 <[^>]+> 4600 mov r0, r0
0+426 <[^>]+> 4681 mov r9, r0
0+428 <[^>]+> 4648 mov r0, r9
0+42a <[^>]+> ea4f 0000 mov\.w r0, r0
0+42e <[^>]+> ea4f 0900 mov\.w r9, r0
0+432 <[^>]+> ea4f 0009 mov\.w r0, r9
0+436 <[^>]+> b910 cbnz r0, 0+43e <[^>]+>
0+438 <[^>]+> b105 cbz r5, 0+43c <[^>]+>
0+43a <[^>]+> bf00 nop
0+43c <[^>]+> bf10 yield
0+43e <[^>]+> bf20 wfe
0+440 <[^>]+> bf30 wfi
0+442 <[^>]+> bf40 sev
0+444 <[^>]+> f3af 8000 nop\.w
0+448 <[^>]+> f3af 8001 yield\.w
0+44c <[^>]+> f3af 8002 wfe\.w
0+450 <[^>]+> f3af 8003 wfi\.w
0+454 <[^>]+> f3af 9004 sev\.w
0+458 <[^>]+> bf90 nop \{9\}
0+45a <[^>]+> f3af 8081 nop\.w \{129\}
0+45e <[^>]+> bf08 it eq
0+460 <[^>]+> bf00 nop
0+462 <[^>]+> bf18 it ne
0+464 <[^>]+> bf00 nop
0+466 <[^>]+> bf28 it cs
0+468 <[^>]+> bf00 nop
0+46a <[^>]+> bf28 it cs
0+46c <[^>]+> bf00 nop
0+46e <[^>]+> bf38 it cc
0+470 <[^>]+> bf00 nop
0+472 <[^>]+> bf38 it cc
0+474 <[^>]+> bf00 nop
0+476 <[^>]+> bf38 it cc
0+478 <[^>]+> bf00 nop
0+47a <[^>]+> bf48 it mi
0+47c <[^>]+> bf00 nop
0+47e <[^>]+> bf58 it pl
0+480 <[^>]+> bf00 nop
0+482 <[^>]+> bf68 it vs
0+484 <[^>]+> bf00 nop
0+486 <[^>]+> bf78 it vc
0+488 <[^>]+> bf00 nop
0+48a <[^>]+> bf88 it hi
0+48c <[^>]+> bf00 nop
0+48e <[^>]+> bfa8 it ge
0+490 <[^>]+> bf00 nop
0+492 <[^>]+> bfb8 it lt
0+494 <[^>]+> bf00 nop
0+496 <[^>]+> bfc8 it gt
0+498 <[^>]+> bf00 nop
0+49a <[^>]+> bfd8 it le
0+49c <[^>]+> bf00 nop
0+49e <[^>]+> bfe8 it al
0+4a0 <[^>]+> bf00 nop
0+4a2 <[^>]+> bf04 itt eq
0+4a4 <[^>]+> bf00 nop
0+4a6 <[^>]+> bf00 nop
0+4a8 <[^>]+> bf0c ite eq
0+4aa <[^>]+> bf00 nop
0+4ac <[^>]+> bf00 nop
0+4ae <[^>]+> bf02 ittt eq
0+4b0 <[^>]+> bf00 nop
0+4b2 <[^>]+> bf00 nop
0+4b4 <[^>]+> bf00 nop
0+4b6 <[^>]+> bf0a itet eq
0+4b8 <[^>]+> bf00 nop
0+4ba <[^>]+> bf00 nop
0+4bc <[^>]+> bf00 nop
0+4be <[^>]+> bf06 itte eq
0+4c0 <[^>]+> bf00 nop
0+4c2 <[^>]+> bf00 nop
0+4c4 <[^>]+> bf00 nop
0+4c6 <[^>]+> bf0e itee eq
0+4c8 <[^>]+> bf00 nop
0+4ca <[^>]+> bf00 nop
0+4cc <[^>]+> bf00 nop
0+4ce <[^>]+> bf01 itttt eq
0+4d0 <[^>]+> bf00 nop
0+4d2 <[^>]+> bf00 nop
0+4d4 <[^>]+> bf00 nop
0+4d6 <[^>]+> bf00 nop
0+4d8 <[^>]+> bf09 itett eq
0+4da <[^>]+> bf00 nop
0+4dc <[^>]+> bf00 nop
0+4de <[^>]+> bf00 nop
0+4e0 <[^>]+> bf00 nop
0+4e2 <[^>]+> bf05 ittet eq
0+4e4 <[^>]+> bf00 nop
0+4e6 <[^>]+> bf00 nop
0+4e8 <[^>]+> bf00 nop
0+4ea <[^>]+> bf00 nop
0+4ec <[^>]+> bf03 ittte eq
0+4ee <[^>]+> bf00 nop
0+4f0 <[^>]+> bf00 nop
0+4f2 <[^>]+> bf00 nop
0+4f4 <[^>]+> bf00 nop
0+4f6 <[^>]+> bf07 ittee eq
0+4f8 <[^>]+> bf00 nop
0+4fa <[^>]+> bf00 nop
0+4fc <[^>]+> bf00 nop
0+4fe <[^>]+> bf00 nop
0+500 <[^>]+> bf0b itete eq
0+502 <[^>]+> bf00 nop
0+504 <[^>]+> bf00 nop
0+506 <[^>]+> bf00 nop
0+508 <[^>]+> bf00 nop
0+50a <[^>]+> bf0d iteet eq
0+50c <[^>]+> bf00 nop
0+50e <[^>]+> bf00 nop
0+510 <[^>]+> bf00 nop
0+512 <[^>]+> bf00 nop
0+514 <[^>]+> bf0f iteee eq
0+516 <[^>]+> bf00 nop
0+518 <[^>]+> bf00 nop
0+51a <[^>]+> bf00 nop
0+51c <[^>]+> bf00 nop
0+51e <[^>]+> bf1c itt ne
0+520 <[^>]+> bf00 nop
0+522 <[^>]+> bf00 nop
0+524 <[^>]+> bf14 ite ne
0+526 <[^>]+> bf00 nop
0+528 <[^>]+> bf00 nop
0+52a <[^>]+> bf1e ittt ne
0+52c <[^>]+> bf00 nop
0+52e <[^>]+> bf00 nop
0+530 <[^>]+> bf00 nop
0+532 <[^>]+> bf16 itet ne
0+534 <[^>]+> bf00 nop
0+536 <[^>]+> bf00 nop
0+538 <[^>]+> bf00 nop
0+53a <[^>]+> bf1a itte ne
0+53c <[^>]+> bf00 nop
0+53e <[^>]+> bf00 nop
0+540 <[^>]+> bf00 nop
0+542 <[^>]+> bf12 itee ne
0+544 <[^>]+> bf00 nop
0+546 <[^>]+> bf00 nop
0+548 <[^>]+> bf00 nop
0+54a <[^>]+> bf1f itttt ne
0+54c <[^>]+> bf00 nop
0+54e <[^>]+> bf00 nop
0+550 <[^>]+> bf00 nop
0+552 <[^>]+> bf00 nop
0+554 <[^>]+> bf17 itett ne
0+556 <[^>]+> bf00 nop
0+558 <[^>]+> bf00 nop
0+55a <[^>]+> bf00 nop
0+55c <[^>]+> bf00 nop
0+55e <[^>]+> bf1b ittet ne
0+560 <[^>]+> bf00 nop
0+562 <[^>]+> bf00 nop
0+564 <[^>]+> bf00 nop
0+566 <[^>]+> bf00 nop
0+568 <[^>]+> bf1d ittte ne
0+56a <[^>]+> bf00 nop
0+56c <[^>]+> bf00 nop
0+56e <[^>]+> bf00 nop
0+570 <[^>]+> bf00 nop
0+572 <[^>]+> bf19 ittee ne
0+574 <[^>]+> bf00 nop
0+576 <[^>]+> bf00 nop
0+578 <[^>]+> bf00 nop
0+57a <[^>]+> bf00 nop
0+57c <[^>]+> bf15 itete ne
0+57e <[^>]+> bf00 nop
0+580 <[^>]+> bf00 nop
0+582 <[^>]+> bf00 nop
0+584 <[^>]+> bf00 nop
0+586 <[^>]+> bf13 iteet ne
0+588 <[^>]+> bf00 nop
0+58a <[^>]+> bf00 nop
0+58c <[^>]+> bf00 nop
0+58e <[^>]+> bf00 nop
0+590 <[^>]+> bf11 iteee ne
0+592 <[^>]+> bf00 nop
0+594 <[^>]+> bf00 nop
0+596 <[^>]+> bf00 nop
0+598 <[^>]+> bf00 nop
0+59a <[^>]+> f895 1000 ldrb\.w r1, \[r5\]
0+59e <[^>]+> f895 1330 ldrb\.w r1, \[r5, #816\]
0+5a2 <[^>]+> f815 1c30 ldrb\.w r1, \[r5, #-48\]
0+5a6 <[^>]+> f815 1b30 ldrb\.w r1, \[r5, #48\]!
0+5aa <[^>]+> f815 1930 ldrb\.w r1, \[r5, #-48\]!
0+5ae <[^>]+> f815 1f30 ldrb\.w r1, \[r5\], #48
0+5b2 <[^>]+> f815 1d30 ldrb\.w r1, \[r5\], #-48
0+5b6 <[^>]+> 5d29 ldrb r1, \[r5, r4\]
0+5b8 <[^>]+> f819 100c ldrb\.w r1, \[r9, ip\]
0+5bc <[^>]+> f89f 10ac ldrb\.w r1, \[pc, #172\] ; 0+66c <[^>]+>
0+5c0 <[^>]+> f81f 102a ldrb\.w r1, \[pc, #-42\] ; 0+59a <[^>]+>
0+5c4 <[^>]+> f995 1000 ldrsb\.w r1, \[r5\]
0+5c8 <[^>]+> f995 1330 ldrsb\.w r1, \[r5, #816\]
0+5cc <[^>]+> f915 1c30 ldrsb\.w r1, \[r5, #-48\]
0+5d0 <[^>]+> f915 1b30 ldrsb\.w r1, \[r5, #48\]!
0+5d4 <[^>]+> f915 1930 ldrsb\.w r1, \[r5, #-48\]!
0+5d8 <[^>]+> f915 1f30 ldrsb\.w r1, \[r5\], #48
0+5dc <[^>]+> f915 1d30 ldrsb\.w r1, \[r5\], #-48
0+5e0 <[^>]+> 5729 ldrsb r1, \[r5, r4\]
0+5e2 <[^>]+> f919 100c ldrsb\.w r1, \[r9, ip\]
0+5e6 <[^>]+> f99f 1084 ldrsb\.w r1, \[pc, #132\] ; 0+66c <[^>]+>
0+5ea <[^>]+> f91f 1052 ldrsb\.w r1, \[pc, #-82\] ; 0+59a <[^>]+>
0+5ee <[^>]+> f8b5 1000 ldrh\.w r1, \[r5\]
0+5f2 <[^>]+> f8b5 1330 ldrh\.w r1, \[r5, #816\]
0+5f6 <[^>]+> f835 1c30 ldrh\.w r1, \[r5, #-48\]
0+5fa <[^>]+> f835 1b30 ldrh\.w r1, \[r5, #48\]!
0+5fe <[^>]+> f835 1930 ldrh\.w r1, \[r5, #-48\]!
0+602 <[^>]+> f835 1f30 ldrh\.w r1, \[r5\], #48
0+606 <[^>]+> f835 1d30 ldrh\.w r1, \[r5\], #-48
0+60a <[^>]+> 5b29 ldrh r1, \[r5, r4\]
0+60c <[^>]+> f839 100c ldrh\.w r1, \[r9, ip\]
0+610 <[^>]+> f8bf 1058 ldrh\.w r1, \[pc, #88\] ; 0+66c <[^>]+>
0+614 <[^>]+> f83f 107e ldrh\.w r1, \[pc, #-126\] ; 0+59a <[^>]+>
0+618 <[^>]+> f9b5 1000 ldrsh\.w r1, \[r5\]
0+61c <[^>]+> f9b5 1330 ldrsh\.w r1, \[r5, #816\]
0+620 <[^>]+> f935 1c30 ldrsh\.w r1, \[r5, #-48\]
0+624 <[^>]+> f935 1b30 ldrsh\.w r1, \[r5, #48\]!
0+628 <[^>]+> f935 1930 ldrsh\.w r1, \[r5, #-48\]!
0+62c <[^>]+> f935 1f30 ldrsh\.w r1, \[r5\], #48
0+630 <[^>]+> f935 1d30 ldrsh\.w r1, \[r5\], #-48
0+634 <[^>]+> 5f29 ldrsh r1, \[r5, r4\]
0+636 <[^>]+> f939 100c ldrsh\.w r1, \[r9, ip\]
0+63a <[^>]+> f9bf 1030 ldrsh\.w r1, \[pc, #48\] ; 0+66c <[^>]+>
0+63e <[^>]+> f93f 10a6 ldrsh\.w r1, \[pc, #-166\] ; 0+59a <[^>]+>
0+642 <[^>]+> f8d5 1000 ldr\.w r1, \[r5\]
0+646 <[^>]+> f8d5 1330 ldr\.w r1, \[r5, #816\]
0+64a <[^>]+> f855 1c30 ldr\.w r1, \[r5, #-48\]
0+64e <[^>]+> f855 1b30 ldr\.w r1, \[r5, #48\]!
0+652 <[^>]+> f855 1930 ldr\.w r1, \[r5, #-48\]!
0+656 <[^>]+> f855 1f30 ldr\.w r1, \[r5\], #48
0+65a <[^>]+> f855 1d30 ldr\.w r1, \[r5\], #-48
0+65e <[^>]+> 5929 ldr r1, \[r5, r4\]
0+660 <[^>]+> f859 100c ldr\.w r1, \[r9, ip\]
0+664 <[^>]+> f8df 1004 ldr\.w r1, \[pc, #4\] ; 0+66c <[^>]+>
0+668 <[^>]+> f85f 10d2 ldr\.w r1, \[pc, #-210\] ; 0+59a <[^>]+>
0+66c <[^>]+> f885 1000 strb\.w r1, \[r5\]
0+670 <[^>]+> f885 1330 strb\.w r1, \[r5, #816\]
0+674 <[^>]+> f805 1c30 strb\.w r1, \[r5, #-48\]
0+678 <[^>]+> f805 1b30 strb\.w r1, \[r5, #48\]!
0+67c <[^>]+> f805 1930 strb\.w r1, \[r5, #-48\]!
0+680 <[^>]+> f805 1f30 strb\.w r1, \[r5\], #48
0+684 <[^>]+> f805 1d30 strb\.w r1, \[r5\], #-48
0+688 <[^>]+> 5529 strb r1, \[r5, r4\]
0+68a <[^>]+> f809 100c strb\.w r1, \[r9, ip\]
0+68e <[^>]+> f88f 1086 strb\.w r1, \[pc, #134\] ; 0+716 <[^>]+>
0+692 <[^>]+> f80f 1028 strb\.w r1, \[pc, #-40\] ; 0+66c <[^>]+>
0+696 <[^>]+> f8a5 1000 strh\.w r1, \[r5\]
0+69a <[^>]+> f8a5 1330 strh\.w r1, \[r5, #816\]
0+69e <[^>]+> f825 1c30 strh\.w r1, \[r5, #-48\]
0+6a2 <[^>]+> f825 1b30 strh\.w r1, \[r5, #48\]!
0+6a6 <[^>]+> f825 1930 strh\.w r1, \[r5, #-48\]!
0+6aa <[^>]+> f825 1f30 strh\.w r1, \[r5\], #48
0+6ae <[^>]+> f825 1d30 strh\.w r1, \[r5\], #-48
0+6b2 <[^>]+> 5329 strh r1, \[r5, r4\]
0+6b4 <[^>]+> f829 100c strh\.w r1, \[r9, ip\]
0+6b8 <[^>]+> f8af 105a strh\.w r1, \[pc, #90\] ; 0+716 <[^>]+>
0+6bc <[^>]+> f82f 1054 strh\.w r1, \[pc, #-84\] ; 0+66c <[^>]+>
0+6c0 <[^>]+> f8c5 1000 str\.w r1, \[r5\]
0+6c4 <[^>]+> f8c5 1330 str\.w r1, \[r5, #816\]
0+6c8 <[^>]+> f845 1c30 str\.w r1, \[r5, #-48\]
0+6cc <[^>]+> f845 1b30 str\.w r1, \[r5, #48\]!
0+6d0 <[^>]+> f845 1930 str\.w r1, \[r5, #-48\]!
0+6d4 <[^>]+> f845 1f30 str\.w r1, \[r5\], #48
0+6d8 <[^>]+> f845 1d30 str\.w r1, \[r5\], #-48
0+6dc <[^>]+> 5129 str r1, \[r5, r4\]
0+6de <[^>]+> f849 100c str\.w r1, \[r9, ip\]
0+6e2 <[^>]+> f8cf 1032 str\.w r1, \[pc, #50\] ; 0+716 <[^>]+>
0+6e6 <[^>]+> f84f 107c str\.w r1, \[pc, #-124\] ; 0+66c <[^>]+>
0+6ea <[^>]+> f895 f000 pld \[r5\]
0+6ee <[^>]+> f895 f330 pld \[r5, #816\]
0+6f2 <[^>]+> f815 fc30 pld \[r5, #-48\]
0+6f6 <[^>]+> f815 fb30 pld \[r5, #48\]!
0+6fa <[^>]+> f815 f930 pld \[r5, #-48\]!
0+6fe <[^>]+> f815 ff30 pld \[r5\], #48
0+702 <[^>]+> f815 fd30 pld \[r5\], #-48
0+706 <[^>]+> f815 f000 pld \[r5, r0\]
0+70a <[^>]+> f819 f000 pld \[r9, r0\]
0+70e <[^>]+> f89f f006 pld \[pc, #6\] ; 0+716 <[^>]+>
0+712 <[^>]+> f81f f0a8 pld \[pc, #-168\] ; 0+66c <[^>]+>
0+716 <[^>]+> e9d5 2300 ldrd r2, r3, \[r5\]
0+71a <[^>]+> e9d5 230c ldrd r2, r3, \[r5, #48\]
0+71e <[^>]+> e955 230c ldrd r2, r3, \[r5, #-48\]
0+722 <[^>]+> e9c5 2300 strd r2, r3, \[r5\]
0+726 <[^>]+> e9c5 230c strd r2, r3, \[r5, #48\]
0+72a <[^>]+> e945 230c strd r2, r3, \[r5, #-48\]
0+72e <[^>]+> f835 1e00 ldrht r1, \[r5\]
0+732 <[^>]+> f835 1e30 ldrht r1, \[r5, #48\]
0+736 <[^>]+> f915 1e00 ldrsbt r1, \[r5\]
0+73a <[^>]+> f915 1e30 ldrsbt r1, \[r5, #48\]
0+73e <[^>]+> f835 1e00 ldrht r1, \[r5\]
0+742 <[^>]+> f835 1e30 ldrht r1, \[r5, #48\]
0+746 <[^>]+> f935 1e00 ldrsht r1, \[r5\]
0+74a <[^>]+> f935 1e30 ldrsht r1, \[r5, #48\]
0+74e <[^>]+> f855 1e00 ldrt r1, \[r5\]
0+752 <[^>]+> f855 1e30 ldrt r1, \[r5, #48\]
0+756 <[^>]+> e8d4 1f4f ldrexb r1, \[r4\]
0+75a <[^>]+> e8d4 1f5f ldrexh r1, \[r4\]
0+75e <[^>]+> e854 1f00 ldrex r1, \[r4\]
0+762 <[^>]+> e8d4 127f ldrexd r1, r2, \[r4\]
0+766 <[^>]+> e8c4 2f41 strexb r1, r2, \[r4\]
0+76a <[^>]+> e8c4 2f51 strexh r1, r2, \[r4\]
0+76e <[^>]+> e844 2100 strex r1, r2, \[r4\]
0+772 <[^>]+> e8c4 2371 strexd r1, r2, r3, \[r4\]
0+776 <[^>]+> e854 1f81 ldrex r1, \[r4, #516\]
0+77a <[^>]+> e844 2181 strex r1, r2, \[r4, #516\]
0+77e <[^>]+> c80e ldmia r0!, \{r1, r2, r3\}
0+780 <[^>]+> ca07 ldmia r2!, \{r0, r1, r2\}
0+782 <[^>]+> e892 0007 ldmia\.w r2, \{r0, r1, r2\}
0+786 <[^>]+> e899 0007 ldmia\.w r9, \{r0, r1, r2\}
0+78a <[^>]+> e890 0580 ldmia\.w r0, \{r7, r8, sl\}
0+78e <[^>]+> e8b0 0580 ldmia\.w r0!, \{r7, r8, sl\}
0+792 <[^>]+> c00e stmia r0!, \{r1, r2, r3\}
0+794 <[^>]+> c20b stmia r2!, \{r0, r1, r3\}
0+796 <[^>]+> e8a2 000b stmia\.w r2!, \{r0, r1, r3\}
0+79a <[^>]+> e889 0007 stmia\.w r9, \{r0, r1, r2\}
0+79e <[^>]+> e880 0580 stmia\.w r0, \{r7, r8, sl\}
0+7a2 <[^>]+> e8a0 0580 stmia\.w r0!, \{r7, r8, sl\}
0+7a6 <[^>]+> e900 0580 stmdb r0, \{r7, r8, sl\}
0+7aa <[^>]+> e910 0580 ldmdb r0, \{r7, r8, sl\}
0+7ae <[^>]+> fb00 0000 mla r0, r0, r0, r0
0+7b2 <[^>]+> fb00 0010 mls r0, r0, r0, r0
0+7b6 <[^>]+> fb00 0900 mla r9, r0, r0, r0
0+7ba <[^>]+> fb09 0000 mla r0, r9, r0, r0
0+7be <[^>]+> fb00 0009 mla r0, r0, r9, r0
0+7c2 <[^>]+> fb00 9000 mla r0, r0, r0, r9
0+7c6 <[^>]+> 4200 tst r0, r0
0+7c8 <[^>]+> 4200 tst r0, r0
0+7ca <[^>]+> 4205 tst r5, r0
0+7cc <[^>]+> 4228 tst r0, r5
0+7ce <[^>]+> ea10 4f65 tst\.w r0, r5, asr #17
0+7d2 <[^>]+> ea10 0f00 tst\.w r0, r0
0+7d6 <[^>]+> ea19 0f00 tst\.w r9, r0
0+7da <[^>]+> ea10 0f09 tst\.w r0, r9
0+7de <[^>]+> f010 0f81 tst\.w r0, #129 ; 0x81
0+7e2 <[^>]+> f015 0f81 tst\.w r5, #129 ; 0x81
0+7e6 <[^>]+> ea90 0f00 teq r0, r0
0+7ea <[^>]+> ea90 0f00 teq r0, r0
0+7ee <[^>]+> ea95 0f00 teq r5, r0
0+7f2 <[^>]+> ea90 0f05 teq r0, r5
0+7f6 <[^>]+> ea90 4f65 teq r0, r5, asr #17
0+7fa <[^>]+> ea90 0f00 teq r0, r0
0+7fe <[^>]+> ea99 0f00 teq r9, r0
0+802 <[^>]+> ea90 0f09 teq r0, r9
0+806 <[^>]+> f090 0f81 teq r0, #129 ; 0x81
0+80a <[^>]+> f095 0f81 teq r5, #129 ; 0x81
0+80e <[^>]+> 4280 cmp r0, r0
0+810 <[^>]+> 4280 cmp r0, r0
0+812 <[^>]+> 4285 cmp r5, r0
0+814 <[^>]+> 42a8 cmp r0, r5
0+816 <[^>]+> ebb0 4f65 cmp\.w r0, r5, asr #17
0+81a <[^>]+> ebb0 0f00 cmp\.w r0, r0
0+81e <[^>]+> 4581 cmp r9, r0
0+820 <[^>]+> ebb0 0f09 cmp\.w r0, r9
0+824 <[^>]+> f1b0 0f81 cmp\.w r0, #129 ; 0x81
0+828 <[^>]+> f1b5 0f81 cmp\.w r5, #129 ; 0x81
0+82c <[^>]+> 42c0 cmn r0, r0
0+82e <[^>]+> 42c0 cmn r0, r0
0+830 <[^>]+> 42c5 cmn r5, r0
0+832 <[^>]+> 42e8 cmn r0, r5
0+834 <[^>]+> eb10 4f65 cmn\.w r0, r5, asr #17
0+838 <[^>]+> eb10 0f00 cmn\.w r0, r0
0+83c <[^>]+> eb19 0f00 cmn\.w r9, r0
0+840 <[^>]+> eb10 0f09 cmn\.w r0, r9
0+844 <[^>]+> f110 0f81 cmn\.w r0, #129 ; 0x81
0+848 <[^>]+> f115 0f81 cmn\.w r5, #129 ; 0x81
0+84c <[^>]+> 1c00 adds r0, r0, #0
0+84e <[^>]+> 4600 mov r0, r0
0+850 <[^>]+> 1c05 adds r5, r0, #0
0+852 <[^>]+> 4628 mov r0, r5
0+854 <[^>]+> ea4f 4065 mov\.w r0, r5, asr #17
0+858 <[^>]+> ea4f 0000 mov\.w r0, r0
0+85c <[^>]+> ea5f 0900 movs\.w r9, r0
0+860 <[^>]+> ea5f 0009 movs\.w r0, r9
0+864 <[^>]+> f04f 0081 mov\.w r0, #129 ; 0x81
0+868 <[^>]+> f04f 0581 mov\.w r5, #129 ; 0x81
0+86c <[^>]+> 43c0 mvns r0, r0
0+86e <[^>]+> ea6f 0000 mvn\.w r0, r0
0+872 <[^>]+> 43c5 mvns r5, r0
0+874 <[^>]+> ea6f 0005 mvn\.w r0, r5
0+878 <[^>]+> ea6f 4065 mvn\.w r0, r5, asr #17
0+87c <[^>]+> ea6f 0000 mvn\.w r0, r0
0+880 <[^>]+> ea7f 0900 mvns\.w r9, r0
0+884 <[^>]+> ea7f 0009 mvns\.w r0, r9
0+888 <[^>]+> f06f 0081 mvn\.w r0, #129 ; 0x81
0+88c <[^>]+> f06f 0581 mvn\.w r5, #129 ; 0x81
0+890 <[^>]+> f240 0000 movw r0, #0 ; 0x0
0+894 <[^>]+> f2c0 0000 movt r0, #0 ; 0x0
0+898 <[^>]+> f240 0900 movw r9, #0 ; 0x0
0+89c <[^>]+> f249 0000 movw r0, #36864 ; 0x9000
0+8a0 <[^>]+> f640 0000 movw r0, #2048 ; 0x800
0+8a4 <[^>]+> f240 5000 movw r0, #1280 ; 0x500
0+8a8 <[^>]+> f240 0081 movw r0, #129 ; 0x81
0+8ac <[^>]+> f64f 70ff movw r0, #65535 ; 0xffff
0+8b0 <[^>]+> f3ef 8000 mrs r0, SPSR
0+8b4 <[^>]+> f3ff 8000 mrs r0, CPSR
0+8b8 <[^>]+> f3ef 8900 mrs r9, SPSR
0+8bc <[^>]+> f3ff 8900 mrs r9, CPSR
0+8c0 <[^>]+> f380 8100 msr SPSR_c, r0
0+8c4 <[^>]+> f390 8100 msr CPSR_c, r0
0+8c8 <[^>]+> f389 8100 msr SPSR_c, r9
0+8cc <[^>]+> f380 8200 msr SPSR_x, r0
0+8d0 <[^>]+> f380 8400 msr SPSR_s, r0
0+8d4 <[^>]+> f380 8800 msr SPSR_f, r0
0+8d8 <[^>]+> fb00 f000 mul\.w r0, r0, r0
0+8dc <[^>]+> fb09 f000 mul\.w r0, r9, r0
0+8e0 <[^>]+> fb00 f009 mul\.w r0, r0, r9
0+8e4 <[^>]+> fb00 f000 mul\.w r0, r0, r0
0+8e8 <[^>]+> fb00 f909 mul\.w r9, r0, r9
0+8ec <[^>]+> 4345 muls r5, r0
0+8ee <[^>]+> 4345 muls r5, r0
0+8f0 <[^>]+> 4368 muls r0, r5
0+8f2 <[^>]+> fb80 0100 smull r0, r1, r0, r0
0+8f6 <[^>]+> fba0 0100 umull r0, r1, r0, r0
0+8fa <[^>]+> fbc0 0100 smlal r0, r1, r0, r0
0+8fe <[^>]+> fbe0 0100 umlal r0, r1, r0, r0
0+902 <[^>]+> fb80 9000 smull r9, r0, r0, r0
0+906 <[^>]+> fb80 0900 smull r0, r9, r0, r0
0+90a <[^>]+> fb89 0100 smull r0, r1, r9, r0
0+90e <[^>]+> fb80 0109 smull r0, r1, r0, r9
0+912 <[^>]+> 4240 negs r0, r0
0+914 <[^>]+> 4268 negs r0, r5
0+916 <[^>]+> 4245 negs r5, r0
0+918 <[^>]+> f1d0 0000 rsbs r0, r0, #0 ; 0x0
0+91c <[^>]+> f1d0 0500 rsbs r5, r0, #0 ; 0x0
0+920 <[^>]+> f1d5 0000 rsbs r0, r5, #0 ; 0x0
0+924 <[^>]+> f1c9 0000 rsb r0, r9, #0 ; 0x0
0+928 <[^>]+> f1c0 0900 rsb r9, r0, #0 ; 0x0
0+92c <[^>]+> f1d9 0000 rsbs r0, r9, #0 ; 0x0
0+930 <[^>]+> f1d0 0900 rsbs r9, r0, #0 ; 0x0
0+934 <[^>]+> eac0 0000 pkhbt r0, r0, r0
0+938 <[^>]+> eac0 0900 pkhbt r9, r0, r0
0+93c <[^>]+> eac9 0000 pkhbt r0, r9, r0
0+940 <[^>]+> eac0 0009 pkhbt r0, r0, r9
0+944 <[^>]+> eac0 5000 pkhbt r0, r0, r0, lsl #20
0+948 <[^>]+> eac0 00c0 pkhbt r0, r0, r0, lsl #3
0+94c <[^>]+> eac2 0103 pkhbt r1, r2, r3
0+950 <[^>]+> eac2 4163 pkhtb r1, r2, r3, asr #17
0+954 <[^>]+> b401 push \{r0\}
0+956 <[^>]+> bc01 pop \{r0\}
0+958 <[^>]+> b502 push \{r1, lr\}
0+95a <[^>]+> bd02 pop \{r1, pc\}
0+95c <[^>]+> e8bd 1f00 ldmia\.w sp!, \{r8, r9, sl, fp, ip\}
0+960 <[^>]+> e8ad 1f00 stmia\.w sp!, \{r8, r9, sl, fp, ip\}
0+964 <[^>]+> fa92 f113 qadd16 r1, r2, r3
0+968 <[^>]+> fa82 f113 qadd8 r1, r2, r3
0+96c <[^>]+> faa2 f113 qaddsubx r1, r2, r3
0+970 <[^>]+> fad2 f113 qsub16 r1, r2, r3
0+974 <[^>]+> fac2 f113 qsub8 r1, r2, r3
0+978 <[^>]+> fae2 f113 qsubaddx r1, r2, r3
0+97c <[^>]+> fa92 f103 sadd16 r1, r2, r3
0+980 <[^>]+> fa82 f103 sadd8 r1, r2, r3
0+984 <[^>]+> faa2 f103 saddsubx r1, r2, r3
0+988 <[^>]+> fad2 f103 ssub16 r1, r2, r3
0+98c <[^>]+> fac2 f103 ssub8 r1, r2, r3
0+990 <[^>]+> fae2 f103 ssubaddx r1, r2, r3
0+994 <[^>]+> fa92 f123 shadd16 r1, r2, r3
0+998 <[^>]+> fa82 f123 shadd8 r1, r2, r3
0+99c <[^>]+> faa2 f123 shaddsubx r1, r2, r3
0+9a0 <[^>]+> fad2 f123 shsub16 r1, r2, r3
0+9a4 <[^>]+> fac2 f123 shsub8 r1, r2, r3
0+9a8 <[^>]+> fae2 f123 shsubaddx r1, r2, r3
0+9ac <[^>]+> fa92 f143 uadd16 r1, r2, r3
0+9b0 <[^>]+> fa82 f143 uadd8 r1, r2, r3
0+9b4 <[^>]+> faa2 f143 uaddsubx r1, r2, r3
0+9b8 <[^>]+> fad2 f143 usub16 r1, r2, r3
0+9bc <[^>]+> fac2 f143 usub8 r1, r2, r3
0+9c0 <[^>]+> fae2 f143 usubaddx r1, r2, r3
0+9c4 <[^>]+> fa92 f163 uhadd16 r1, r2, r3
0+9c8 <[^>]+> fa82 f163 uhadd8 r1, r2, r3
0+9cc <[^>]+> faa2 f163 uhaddsubx r1, r2, r3
0+9d0 <[^>]+> fad2 f163 uhsub16 r1, r2, r3
0+9d4 <[^>]+> fac2 f163 uhsub8 r1, r2, r3
0+9d8 <[^>]+> fae2 f163 uhsubaddx r1, r2, r3
0+9dc <[^>]+> fa92 f153 uqadd16 r1, r2, r3
0+9e0 <[^>]+> fa82 f153 uqadd8 r1, r2, r3
0+9e4 <[^>]+> faa2 f153 uqaddsubx r1, r2, r3
0+9e8 <[^>]+> fad2 f153 uqsub16 r1, r2, r3
0+9ec <[^>]+> fac2 f153 uqsub8 r1, r2, r3
0+9f0 <[^>]+> fae2 f153 uqsubaddx r1, r2, r3
0+9f4 <[^>]+> faa2 f183 sel r1, r2, r3
0+9f8 <[^>]+> ba00 rev r0, r0
0+9fa <[^>]+> fa90 f080 rev\.w r0, r0
0+9fe <[^>]+> ba28 rev r0, r5
0+a00 <[^>]+> ba05 rev r5, r0
0+a02 <[^>]+> fa99 f089 rev\.w r0, r9
0+a06 <[^>]+> fa90 f980 rev\.w r9, r0
0+a0a <[^>]+> ba40 rev16 r0, r0
0+a0c <[^>]+> fa90 f090 rev16\.w r0, r0
0+a10 <[^>]+> ba68 rev16 r0, r5
0+a12 <[^>]+> ba45 rev16 r5, r0
0+a14 <[^>]+> fa99 f099 rev16\.w r0, r9
0+a18 <[^>]+> fa90 f990 rev16\.w r9, r0
0+a1c <[^>]+> bac0 revsh r0, r0
0+a1e <[^>]+> fa90 f0b0 revsh\.w r0, r0
0+a22 <[^>]+> bae8 revsh r0, r5
0+a24 <[^>]+> bac5 revsh r5, r0
0+a26 <[^>]+> fa99 f0b9 revsh\.w r0, r9
0+a2a <[^>]+> fa90 f9b0 revsh\.w r9, r0
0+a2e <[^>]+> fa90 f0a0 rbit r0, r0
0+a32 <[^>]+> fa90 f0a0 rbit r0, r0
0+a36 <[^>]+> fa95 f0a0 rbit r0, r5
0+a3a <[^>]+> fa90 f5a0 rbit r5, r0
0+a3e <[^>]+> fa99 f0a0 rbit r0, r9
0+a42 <[^>]+> fa90 f9a0 rbit r9, r0
0+a46 <[^>]+> 0440 lsls r0, r0, #17
0+a48 <[^>]+> 0380 lsls r0, r0, #14
0+a4a <[^>]+> 0445 lsls r5, r0, #17
0+a4c <[^>]+> 03a8 lsls r0, r5, #14
0+a4e <[^>]+> 4080 lsls r0, r0
0+a50 <[^>]+> 40a8 lsls r0, r5
0+a52 <[^>]+> 40a8 lsls r0, r5
0+a54 <[^>]+> ea4f 4949 mov\.w r9, r9, lsl #17
0+a58 <[^>]+> ea4f 3989 mov\.w r9, r9, lsl #14
0+a5c <[^>]+> ea5f 4049 movs\.w r0, r9, lsl #17
0+a60 <[^>]+> ea4f 3980 mov\.w r9, r0, lsl #14
0+a64 <[^>]+> fa00 f000 lsl\.w r0, r0, r0
0+a68 <[^>]+> fa09 f909 lsl\.w r9, r9, r9
0+a6c <[^>]+> fa19 f900 lsls\.w r9, r9, r0
0+a70 <[^>]+> fa00 f009 lsl\.w r0, r0, r9
0+a74 <[^>]+> fa00 f005 lsl\.w r0, r0, r5
0+a78 <[^>]+> fa11 f002 lsls\.w r0, r1, r2
0+a7c <[^>]+> 0c40 lsrs r0, r0, #17
0+a7e <[^>]+> 0b80 lsrs r0, r0, #14
0+a80 <[^>]+> 0c45 lsrs r5, r0, #17
0+a82 <[^>]+> 0ba8 lsrs r0, r5, #14
0+a84 <[^>]+> 40c0 lsrs r0, r0
0+a86 <[^>]+> 40e8 lsrs r0, r5
0+a88 <[^>]+> 40e8 lsrs r0, r5
0+a8a <[^>]+> ea4f 4959 mov\.w r9, r9, lsr #17
0+a8e <[^>]+> ea4f 3999 mov\.w r9, r9, lsr #14
0+a92 <[^>]+> ea5f 4059 movs\.w r0, r9, lsr #17
0+a96 <[^>]+> ea4f 3990 mov\.w r9, r0, lsr #14
0+a9a <[^>]+> fa20 f000 lsr\.w r0, r0, r0
0+a9e <[^>]+> fa29 f909 lsr\.w r9, r9, r9
0+aa2 <[^>]+> fa39 f900 lsrs\.w r9, r9, r0
0+aa6 <[^>]+> fa20 f009 lsr\.w r0, r0, r9
0+aaa <[^>]+> fa20 f005 lsr\.w r0, r0, r5
0+aae <[^>]+> fa31 f002 lsrs\.w r0, r1, r2
0+ab2 <[^>]+> 1440 asrs r0, r0, #17
0+ab4 <[^>]+> 1380 asrs r0, r0, #14
0+ab6 <[^>]+> 1445 asrs r5, r0, #17
0+ab8 <[^>]+> 13a8 asrs r0, r5, #14
0+aba <[^>]+> 4100 asrs r0, r0
0+abc <[^>]+> 4128 asrs r0, r5
0+abe <[^>]+> 4128 asrs r0, r5
0+ac0 <[^>]+> ea4f 4969 mov\.w r9, r9, asr #17
0+ac4 <[^>]+> ea4f 39a9 mov\.w r9, r9, asr #14
0+ac8 <[^>]+> ea5f 4069 movs\.w r0, r9, asr #17
0+acc <[^>]+> ea4f 39a0 mov\.w r9, r0, asr #14
0+ad0 <[^>]+> fa40 f000 asr\.w r0, r0, r0
0+ad4 <[^>]+> fa49 f909 asr\.w r9, r9, r9
0+ad8 <[^>]+> fa59 f900 asrs\.w r9, r9, r0
0+adc <[^>]+> fa40 f009 asr\.w r0, r0, r9
0+ae0 <[^>]+> fa40 f005 asr\.w r0, r0, r5
0+ae4 <[^>]+> fa51 f002 asrs\.w r0, r1, r2
0+ae8 <[^>]+> ea5f 4070 movs\.w r0, r0, ror #17
0+aec <[^>]+> ea5f 30b0 movs\.w r0, r0, ror #14
0+af0 <[^>]+> ea5f 4570 movs\.w r5, r0, ror #17
0+af4 <[^>]+> ea5f 30b5 movs\.w r0, r5, ror #14
0+af8 <[^>]+> 41c0 rors r0, r0
0+afa <[^>]+> 41e8 rors r0, r5
0+afc <[^>]+> 41e8 rors r0, r5
0+afe <[^>]+> ea4f 4979 mov\.w r9, r9, ror #17
0+b02 <[^>]+> ea4f 39b9 mov\.w r9, r9, ror #14
0+b06 <[^>]+> ea5f 4079 movs\.w r0, r9, ror #17
0+b0a <[^>]+> ea4f 39b0 mov\.w r9, r0, ror #14
0+b0e <[^>]+> fa60 f000 ror\.w r0, r0, r0
0+b12 <[^>]+> fa69 f909 ror\.w r9, r9, r9
0+b16 <[^>]+> fa79 f900 rors\.w r9, r9, r0
0+b1a <[^>]+> fa60 f009 ror\.w r0, r0, r9
0+b1e <[^>]+> fa60 f005 ror\.w r0, r0, r5
0+b22 <[^>]+> fa71 f002 rors\.w r0, r1, r2
0+b26 <[^>]+> f7f0 8000 smi #0 ; 0x0
0+b2a <[^>]+> f7fd 8bca smi #43981 ; 0xabcd
0+b2e <[^>]+> fb10 0000 smlabb r0, r0, r0, r0
0+b32 <[^>]+> fb10 0900 smlabb r9, r0, r0, r0
0+b36 <[^>]+> fb19 0000 smlabb r0, r9, r0, r0
0+b3a <[^>]+> fb10 0009 smlabb r0, r0, r9, r0
0+b3e <[^>]+> fb10 9000 smlabb r0, r0, r0, r9
0+b42 <[^>]+> fb10 0020 smlatb r0, r0, r0, r0
0+b46 <[^>]+> fb10 0010 smlabt r0, r0, r0, r0
0+b4a <[^>]+> fb10 0030 smlatt r0, r0, r0, r0
0+b4e <[^>]+> fb30 0000 smlawb r0, r0, r0, r0
0+b52 <[^>]+> fb30 0010 smlawt r0, r0, r0, r0
0+b56 <[^>]+> fb20 0000 smlad r0, r0, r0, r0
0+b5a <[^>]+> fb20 0010 smladx r0, r0, r0, r0
0+b5e <[^>]+> fb40 0000 smlsd r0, r0, r0, r0
0+b62 <[^>]+> fb40 0010 smlsdx r0, r0, r0, r0
0+b66 <[^>]+> fb50 0000 smmla r0, r0, r0, r0
0+b6a <[^>]+> fb50 0010 smmlar r0, r0, r0, r0
0+b6e <[^>]+> fb60 0000 smmls r0, r0, r0, r0
0+b72 <[^>]+> fb60 0010 smmlsr r0, r0, r0, r0
0+b76 <[^>]+> fb70 0000 usada8 r0, r0, r0, r0
0+b7a <[^>]+> fbc0 0080 smlalbb r0, r0, r0, r0
0+b7e <[^>]+> fbc0 9080 smlalbb r9, r0, r0, r0
0+b82 <[^>]+> fbc0 0980 smlalbb r0, r9, r0, r0
0+b86 <[^>]+> fbc9 0080 smlalbb r0, r0, r9, r0
0+b8a <[^>]+> fbc0 0089 smlalbb r0, r0, r0, r9
0+b8e <[^>]+> fbc0 00a0 smlaltb r0, r0, r0, r0
0+b92 <[^>]+> fbc0 0090 smlalbt r0, r0, r0, r0
0+b96 <[^>]+> fbc0 00b0 smlaltt r0, r0, r0, r0
0+b9a <[^>]+> fbc0 00c0 smlald r0, r0, r0, r0
0+b9e <[^>]+> fbc0 00d0 smlaldx r0, r0, r0, r0
0+ba2 <[^>]+> fbd0 00c0 smlsld r0, r0, r0, r0
0+ba6 <[^>]+> fbd0 00d0 smlsldx r0, r0, r0, r0
0+baa <[^>]+> fbe0 0060 umaal r0, r0, r0, r0
0+bae <[^>]+> fb10 f000 smulbb r0, r0, r0
0+bb2 <[^>]+> fb10 f900 smulbb r9, r0, r0
0+bb6 <[^>]+> fb19 f000 smulbb r0, r9, r0
0+bba <[^>]+> fb10 f009 smulbb r0, r0, r9
0+bbe <[^>]+> fb10 f020 smultb r0, r0, r0
0+bc2 <[^>]+> fb10 f010 smulbt r0, r0, r0
0+bc6 <[^>]+> fb10 f030 smultt r0, r0, r0
0+bca <[^>]+> fb30 f000 smulwb r0, r0, r0
0+bce <[^>]+> fb30 f010 smulwt r0, r0, r0
0+bd2 <[^>]+> fb50 f000 smmul r0, r0, r0
0+bd6 <[^>]+> fb50 f010 smmulr r0, r0, r0
0+bda <[^>]+> fb20 f000 smuad r0, r0, r0
0+bde <[^>]+> fb20 f010 smuadx r0, r0, r0
0+be2 <[^>]+> fb40 f000 smusd r0, r0, r0
0+be6 <[^>]+> fb40 f010 smusdx r0, r0, r0
0+bea <[^>]+> fb70 f000 usad8 r0, r0, r0
0+bee <[^>]+> f300 0000 ssat r0, #0, r0
0+bf2 <[^>]+> f300 0000 ssat r0, #0, r0
0+bf6 <[^>]+> f300 0000 ssat r0, #0, r0
0+bfa <[^>]+> f300 0900 ssat r9, #0, r0
0+bfe <[^>]+> f300 0011 ssat r0, #17, r0
0+c02 <[^>]+> f309 0000 ssat r0, #0, r9
0+c06 <[^>]+> f300 7000 ssat r0, #0, r0, lsl #28
0+c0a <[^>]+> f320 00c0 ssat r0, #0, r0, asr #3
0+c0e <[^>]+> f320 0000 ssat16 r0, #0, r0
0+c12 <[^>]+> f320 0900 ssat16 r9, #0, r0
0+c16 <[^>]+> f320 0009 ssat16 r0, #9, r0
0+c1a <[^>]+> f329 0000 ssat16 r0, #0, r9
0+c1e <[^>]+> f380 0000 usat r0, #0, r0
0+c22 <[^>]+> f380 0000 usat r0, #0, r0
0+c26 <[^>]+> f380 0000 usat r0, #0, r0
0+c2a <[^>]+> f380 0900 usat r9, #0, r0
0+c2e <[^>]+> f380 0011 usat r0, #17, r0
0+c32 <[^>]+> f389 0000 usat r0, #0, r9
0+c36 <[^>]+> f380 7000 usat r0, #0, r0, lsl #28
0+c3a <[^>]+> f3a0 00c0 usat r0, #0, r0, asr #3
0+c3e <[^>]+> f3a0 0000 usat16 r0, #0, r0
0+c42 <[^>]+> f3a0 0900 usat16 r9, #0, r0
0+c46 <[^>]+> f3a0 0009 usat16 r0, #9, r0
0+c4a <[^>]+> f3a9 0000 usat16 r0, #0, r9
0+c4e <[^>]+> b240 sxtb r0, r0
0+c50 <[^>]+> b240 sxtb r0, r0
0+c52 <[^>]+> b245 sxtb r5, r0
0+c54 <[^>]+> b268 sxtb r0, r5
0+c56 <[^>]+> fa4f f182 sxtb\.w r1, r2
0+c5a <[^>]+> fa4f f192 sxtb\.w r1, r2, ror #8
0+c5e <[^>]+> fa4f f1a2 sxtb\.w r1, r2, ror #16
0+c62 <[^>]+> fa4f f1b2 sxtb\.w r1, r2, ror #24
0+c66 <[^>]+> fa2f f182 sxtb16 r1, r2
0+c6a <[^>]+> fa2f f889 sxtb16 r8, r9
0+c6e <[^>]+> b211 sxth r1, r2
0+c70 <[^>]+> fa0f f889 sxth\.w r8, r9
0+c74 <[^>]+> b2d1 uxtb r1, r2
0+c76 <[^>]+> fa5f f889 uxtb\.w r8, r9
0+c7a <[^>]+> fa3f f182 uxtb16 r1, r2
0+c7e <[^>]+> fa3f f889 uxtb16 r8, r9
0+c82 <[^>]+> b291 uxth r1, r2
0+c84 <[^>]+> fa1f f889 uxth\.w r8, r9
0+c88 <[^>]+> fa40 f080 sxtab r0, r0, r0
0+c8c <[^>]+> fa40 f080 sxtab r0, r0, r0
0+c90 <[^>]+> fa40 f990 sxtab r9, r0, r0, ror #8
0+c94 <[^>]+> fa49 f0a0 sxtab r0, r9, r0, ror #16
0+c98 <[^>]+> fa40 f0b9 sxtab r0, r0, r9, ror #24
0+c9c <[^>]+> fa22 f183 sxtab16 r1, r2, r3
0+ca0 <[^>]+> fa02 f183 sxtah r1, r2, r3
0+ca4 <[^>]+> fa52 f183 uxtab r1, r2, r3
0+ca8 <[^>]+> fa32 f183 uxtab16 r1, r2, r3
0+cac <[^>]+> fa12 f183 uxtah r1, r2, r3

735
gas/testsuite/gas/arm/thumb32.s Normal file
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.text
.thumb
.syntax unified
encode_thumb32_immediate:
orr r0, r1, #0x00000000
orr r0, r1, #0x000000a5
orr r0, r1, #0x00a500a5
orr r0, r1, #0xa500a500
orr r0, r1, #0xa5a5a5a5
orr r0, r1, #0xa5 << 31
orr r0, r1, #0xa5 << 30
orr r0, r1, #0xa5 << 29
orr r0, r1, #0xa5 << 28
orr r0, r1, #0xa5 << 27
orr r0, r1, #0xa5 << 26
orr r0, r1, #0xa5 << 25
orr r0, r1, #0xa5 << 24
orr r0, r1, #0xa5 << 23
orr r0, r1, #0xa5 << 22
orr r0, r1, #0xa5 << 21
orr r0, r1, #0xa5 << 20
orr r0, r1, #0xa5 << 19
orr r0, r1, #0xa5 << 18
orr r0, r1, #0xa5 << 17
orr r0, r1, #0xa5 << 16
orr r0, r1, #0xa5 << 15
orr r0, r1, #0xa5 << 14
orr r0, r1, #0xa5 << 13
orr r0, r1, #0xa5 << 12
orr r0, r1, #0xa5 << 11
orr r0, r1, #0xa5 << 10
orr r0, r1, #0xa5 << 9
orr r0, r1, #0xa5 << 8
orr r0, r1, #0xa5 << 7
orr r0, r1, #0xa5 << 6
orr r0, r1, #0xa5 << 5
orr r0, r1, #0xa5 << 4
orr r0, r1, #0xa5 << 3
orr r0, r1, #0xa5 << 2
orr r0, r1, #0xa5 << 1
add_sub:
adds r0, r0, #0 @ format 1
adds r5, r0, #0
adds r0, r5, #0
adds r0, r0, #5
adds r0, #129 @ format 2
adds r0, r0, #129
adds r5, #126
adds r0, r0, r0 @ format 3
adds r5, r0, r0
adds r0, r5, r0
adds r0, r0, r5
adds r1, r2, r3
add r8, r0 @ format 4
add r0, r8
add r0, r8, r0
add r0, r0, r8
add r8, r0, r0 @ ... not this one
add r1, r0
add r0, r1
add r0, pc, #0 @ format 5
add r5, pc, #0
add r0, pc, #516
add r0, sp, #0 @ format 6
add r5, sp, #0
add r0, sp, #516
add sp, #0 @ format 7
add sp, sp, #0
add sp, #260
add.w r0, r0, #0 @ T32 format 1
adds.w r0, r0, #0
add.w r9, r0, #0
add.w r0, r9, #0
add.w r0, r0, #129
add.w r0, r0, r0 @ T32 format 2
adds.w r0, r0, r0
add.w r9, r0, r0
add.w r0, r9, r0
add.w r0, r0, r9
add.w r8, r9, r10
add.w r8, r9, r10, lsl #17
add.w r8, r8, r10, lsr #32
add.w r8, r8, r10, lsr #17
add.w r8, r9, r10, asr #32
add.w r8, r9, r10, asr #17
add.w r8, r9, r10, rrx
add.w r8, r9, r10, ror #17
subs r0, r0, #0 @ format 1
subs r5, r0, #0
subs r0, r5, #0
subs r0, r0, #5
subs r0, r0, #129
subs r5, #8
subs r0, r0, r0 @ format 3
subs r5, r0, r0
subs r0, r5, r0
subs r0, r0, r5
sub sp, #260 @ format 4
sub sp, sp, #260
subs r8, r0 @ T32 format 2
subs r0, r8
subs r0, #260 @ T32 format 1
arit3:
.macro arit3 op ops opw opsw
\ops r0, r0
\ops r5, r0
\ops r0, r5
\ops r0, r0, r5
\ops r0, r5, r0
\op r0, r5, r0
\op r0, r1, r2
\op r9, r0, r0
\op r0, r9, r0
\op r0, r0, r9
\opsw r0, r0, r0
\opw r0, r1, r2, asr #17
\opw r0, r1, #129
.endm
arit3 adc adcs adc.w adcs.w
arit3 and ands and.w ands.w
arit3 bic bics bic.w bics.w
arit3 eor eors eor.w eors.w
arit3 orr orrs orr.w orrs.w
arit3 rsb rsbs rsb.w rsbs.w
arit3 sbc sbcs sbc.w sbcs.w
.purgem arit3
bfc_bfi_bfx:
bfc r0, #0, #1
bfc r9, #0, #1
bfi r9, #0, #0, #1
bfc r0, #21, #1
bfc r0, #0, #18
bfi r0, r0, #0, #1
bfi r9, r0, #0, #1
bfi r0, r9, #0, #1
bfi r0, r0, #21, #1
bfi r0, r0, #0, #18
sbfx r0, r0, #0, #1
ubfx r9, r0, #0, #1
sbfx r0, r9, #0, #1
ubfx r0, r0, #21, #1
sbfx r0, r0, #0, #18
.globl branches
branches:
.macro bra op
\op 1b
\op 1f
.endm
1:
bra beq.n
bra bne.n
bra bcs.n
bra bhs.n
bra bcc.n
bra bul.n
bra blo.n
bra bmi.n
bra bpl.n
bra bvs.n
bra bvc.n
bra bhi.n
bra bls.n
bra bvc.n
bra bhi.n
bra bls.n
bra bge.n
bra blt.n
bra bgt.n
bra ble.n
bra bal.n
bra b.n
@ bl, blx have no short form.
.balign 4
1:
bra beq
bra bne
bra bcs
bra bhs
bra bcc
bra bul
bra blo
bra bmi
bra bpl
bra bvs
bra bvc
bra bhi
bra bls
bra bvc
bra bhi
bra bls
bra bge
bra blt
bra bgt
bra ble
bra b
bra bl
bra blx
.balign 4
1:
bx r9
blx r0
blx r9
bxj r0
bxj r9
.purgem bra
clz:
clz r0, r0
clz r9, r0
clz r0, r9
cps:
cpsie f
cpsid i
cpsie a
cpsid.w f
cpsie.w i
cpsid.w a
cpsie i, #0
cpsid i, #17
cps #0
cps #17
cpy:
cpy r0, r0
cpy r9, r0
cpy r0, r9
cpy.w r0, r0
cpy.w r9, r0
cpy.w r0, r9
czb:
cbnz r0, 2f
cbz r5, 1f
nop_hint:
nop
1: yield
2: wfe
wfi
sev
nop.w
yield.w
wfe.w
wfi.w
sev.w
nop {9}
nop {129}
it:
.macro itx opc cond n
\opc \cond
.rept \n
nop
.endr
.endm
itx it eq 1
itx it ne 1
itx it cs 1
itx it hs 1
itx it cc 1
itx it ul 1
itx it lo 1
itx it mi 1
itx it pl 1
itx it vs 1
itx it vc 1
itx it hi 1
itx it ge 1
itx it lt 1
itx it gt 1
itx it le 1
itx it al 1
itx itt eq 2
itx ite eq 2
itx ittt eq 3
itx itet eq 3
itx itte eq 3
itx itee eq 3
itx itttt eq 4
itx itett eq 4
itx ittet eq 4
itx ittte eq 4
itx ittee eq 4
itx itete eq 4
itx iteet eq 4
itx iteee eq 4
itx itt ne 2
itx ite ne 2
itx ittt ne 3
itx itet ne 3
itx itte ne 3
itx itee ne 3
itx itttt ne 4
itx itett ne 4
itx ittet ne 4
itx ittte ne 4
itx ittee ne 4
itx itete ne 4
itx iteet ne 4
itx iteee ne 4
.purgem itx
ldst:
.macro ls op
\op r1, [r5]
\op r1, [r5, #0x330]
\op r1, [r5, #-0x30]
\op r1, [r5], #0x30
\op r1, [r5], #-0x30
\op r1, [r5, #0x30]!
\op r1, [r5, #-0x30]!
\op r1, [r5, r4]
\op r1, [r9, ip]
\op r1, 1f
\op r1, 1b
.endm
1:
ls ldrb
ls ldrsb
ls ldrh
ls ldrsh
ls ldr
1:
ls strb
ls strh
ls str
pld [r5]
pld [r5, #0x330]
pld [r5, #-0x30]
pld [r5], #0x30
pld [r5], #-0x30
pld [r5, #0x30]!
pld [r5, #-0x30]!
pld [r5, r4]
pld [r9, ip]
pld 1f
pld 1b
1:
ldrd r2, r3, [r5]
ldrd r2, [r5, #0x30]
ldrd r2, [r5, #-0x30]
strd r2, r3, [r5]
strd r2, [r5, #0x30]
strd r2, [r5, #-0x30]
ldrbt r1, [r5]
ldrbt r1, [r5, #0x30]
ldrsbt r1, [r5]
ldrsbt r1, [r5, #0x30]
ldrht r1, [r5]
ldrht r1, [r5, #0x30]
ldrsht r1, [r5]
ldrsht r1, [r5, #0x30]
ldrt r1, [r5]
ldrt r1, [r5, #0x30]
.purgem ls
ldxstx:
ldrexb r1, [r4]
ldrexh r1, [r4]
ldrex r1, [r4]
ldrexd r1, r2, [r4]
strexb r1, r2, [r4]
strexh r1, r2, [r4]
strex r1, r2, [r4]
strexd r1, r2, r3, [r4]
ldrex r1, [r4,#516]
strex r1, r2, [r4,#516]
ldmstm:
ldmia r0!, {r1,r2,r3}
ldmia r2, {r0,r1,r2}
ldmia.w r2, {r0,r1,r2}
ldmia r9, {r0,r1,r2}
ldmia r0, {r7,r8,r10}
ldmia r0!, {r7,r8,r10}
stmia r0!, {r1,r2,r3}
stmia r2!, {r0,r1,r3}
stmia.w r2!, {r0,r1,r3}
stmia r9, {r0,r1,r2}
stmia r0, {r7,r8,r10}
stmia r0!, {r7,r8,r10}
ldmdb r0, {r7,r8,r10}
stmdb r0, {r7,r8,r10}
mlas:
mla r0, r0, r0, r0
mls r0, r0, r0, r0
mla r9, r0, r0, r0
mla r0, r9, r0, r0
mla r0, r0, r9, r0
mla r0, r0, r0, r9
tst_teq_cmp_cmn_mov_mvn:
.macro mt op ops opw opsw
\ops r0, r0
\op r0, r0
\ops r5, r0
\op r0, r5
\op r0, r5, asr #17
\opw r0, r0
\ops r9, r0
\opsw r0, r9
\op r0, #129
\op r5, #129
.endm
mt tst tsts tst.w tsts.w
mt teq teqs teq.w teqs.w
mt cmp cmps cmp.w cmps.w
mt cmn cmns cmn.w cmns.w
mt mov movs mov.w movs.w
mt mvn mvns mvn.w mvns.w
.purgem mt
mov16:
movw r0, #0
movt r0, #0
movw r9, #0
movw r0, #0x9000
movw r0, #0x0800
movw r0, #0x0500
movw r0, #0x0081
movw r0, #0xffff
mrs_msr:
mrs r0, CPSR
mrs r0, SPSR
mrs r9, CPSR_all
mrs r9, SPSR_all
msr CPSR_c, r0
msr SPSR_c, r0
msr CPSR_c, r9
msr CPSR_x, r0
msr CPSR_s, r0
msr CPSR_f, r0
mul:
mul r0, r0, r0
mul r0, r9, r0
mul r0, r0, r9
mul r0, r0
mul r9, r0
muls r5, r0
muls r5, r0, r5
muls r0, r5
mull:
smull r0, r1, r0, r0
umull r0, r1, r0, r0
smlal r0, r1, r0, r0
umlal r0, r1, r0, r0
smull r9, r0, r0, r0
smull r0, r9, r0, r0
smull r0, r1, r9, r0
smull r0, r1, r0, r9
neg:
negs r0, r0
negs r0, r5
negs r5, r0
negs.w r0, r0
negs.w r5, r0
negs.w r0, r5
neg r0, r9
neg r9, r0
negs r0, r9
negs r9, r0
pkh:
pkhbt r0, r0, r0
pkhbt r9, r0, r0
pkhbt r0, r9, r0
pkhbt r0, r0, r9
pkhbt r0, r0, r0, lsl #0x14
pkhbt r0, r0, r0, lsl #3
pkhtb r1, r2, r3
pkhtb r1, r2, r3, asr #0x11
push_pop:
push {r0}
pop {r0}
push {r1,lr}
pop {r1,pc}
push {r8,r9,r10,r11,r12}
pop {r8,r9,r10,r11,r12}
qadd:
qadd16 r1, r2, r3
qadd8 r1, r2, r3
qaddsubx r1, r2, r3
qsub16 r1, r2, r3
qsub8 r1, r2, r3
qsubaddx r1, r2, r3
sadd16 r1, r2, r3
sadd8 r1, r2, r3
saddsubx r1, r2, r3
ssub16 r1, r2, r3
ssub8 r1, r2, r3
ssubaddx r1, r2, r3
shadd16 r1, r2, r3
shadd8 r1, r2, r3
shaddsubx r1, r2, r3
shsub16 r1, r2, r3
shsub8 r1, r2, r3
shsubaddx r1, r2, r3
uadd16 r1, r2, r3
uadd8 r1, r2, r3
uaddsubx r1, r2, r3
usub16 r1, r2, r3
usub8 r1, r2, r3
usubaddx r1, r2, r3
uhadd16 r1, r2, r3
uhadd8 r1, r2, r3
uhaddsubx r1, r2, r3
uhsub16 r1, r2, r3
uhsub8 r1, r2, r3
uhsubaddx r1, r2, r3
uqadd16 r1, r2, r3
uqadd8 r1, r2, r3
uqaddsubx r1, r2, r3
uqsub16 r1, r2, r3
uqsub8 r1, r2, r3
uqsubaddx r1, r2, r3
sel r1, r2, r3
rbit_rev:
.macro rx op opw
\op r0, r0
\opw r0, r0
\op r0, r5
\op r5, r0
\op r0, r9
\op r9, r0
.endm
rx rev rev.w
rx rev16 rev16.w
rx revsh revsh.w
rx rbit rbit.w
.purgem rx
shift:
.macro sh op ops opw opsw
\ops r0, #17 @ 16-bit format 1
\ops r0, r0, #14
\ops r5, r0, #17
\ops r0, r5, #14
\ops r0, r0 @ 16-bit format 2
\ops r0, r5
\ops r0, r0, r5
\op r9, #17 @ 32-bit format 1
\op r9, r9, #14
\ops r0, r9, #17
\op r9, r0, #14
\opw r0, r0, r0 @ 32-bit format 2
\op r9, r9
\ops r9, r0
\op r0, r9
\op r0, r5
\ops r0, r1, r2
.endm
sh lsl lsls lsl.w lsls.w
sh lsr lsrs lsr.w lsrs.w
sh asr asrs asr.w asrs.w
sh ror rors ror.w rors.w
.purgem sh
smi:
smi #0
smi #0xabcd
smla:
smlabb r0, r0, r0, r0
smlabb r9, r0, r0, r0
smlabb r0, r9, r0, r0
smlabb r0, r0, r9, r0
smlabb r0, r0, r0, r9
smlatb r0, r0, r0, r0
smlabt r0, r0, r0, r0
smlatt r0, r0, r0, r0
smlawb r0, r0, r0, r0
smlawt r0, r0, r0, r0
smlad r0, r0, r0, r0
smladx r0, r0, r0, r0
smlsd r0, r0, r0, r0
smlsdx r0, r0, r0, r0
smmla r0, r0, r0, r0
smmlar r0, r0, r0, r0
smmls r0, r0, r0, r0
smmlsr r0, r0, r0, r0
usada8 r0, r0, r0, r0
smlal:
smlalbb r0, r0, r0, r0
smlalbb r9, r0, r0, r0
smlalbb r0, r9, r0, r0
smlalbb r0, r0, r9, r0
smlalbb r0, r0, r0, r9
smlaltb r0, r0, r0, r0
smlalbt r0, r0, r0, r0
smlaltt r0, r0, r0, r0
smlald r0, r0, r0, r0
smlaldx r0, r0, r0, r0
smlsld r0, r0, r0, r0
smlsldx r0, r0, r0, r0
umaal r0, r0, r0, r0
smul:
smulbb r0, r0, r0
smulbb r9, r0, r0
smulbb r0, r9, r0
smulbb r0, r0, r9
smultb r0, r0, r0
smulbt r0, r0, r0
smultt r0, r0, r0
smulwb r0, r0, r0
smulwt r0, r0, r0
smmul r0, r0, r0
smmulr r0, r0, r0
smuad r0, r0, r0
smuadx r0, r0, r0
smusd r0, r0, r0
smusdx r0, r0, r0
usad8 r0, r0, r0
sat:
ssat r0, #1, r0
ssat r0, #1, r0, lsl #0
ssat r0, #1, r0, asr #0
ssat r9, #1, r0
ssat r0, #18, r0
ssat r0, #1, r9
ssat r0, #1, r0, lsl #0x1c
ssat r0, #1, r0, asr #0x03
ssat16 r0, #1, r0
ssat16 r9, #1, r0
ssat16 r0, #10, r0
ssat16 r0, #1, r9
usat r0, #0, r0
usat r0, #0, r0, lsl #0
usat r0, #0, r0, asr #0
usat r9, #0, r0
usat r0, #17, r0
usat r0, #0, r9
usat r0, #0, r0, lsl #0x1c
usat r0, #0, r0, asr #0x03
usat16 r0, #0, r0
usat16 r9, #0, r0
usat16 r0, #9, r0
usat16 r0, #0, r9
xt:
sxtb r0, r0
sxtb r0, r0, ror #0
sxtb r5, r0
sxtb r0, r5
sxtb.w r1, r2
sxtb r1, r2, ror #8
sxtb r1, r2, ror #16
sxtb r1, r2, ror #24
sxtb16 r1, r2
sxtb16 r8, r9
sxth r1, r2
sxth r8, r9
uxtb r1, r2
uxtb r8, r9
uxtb16 r1, r2
uxtb16 r8, r9
uxth r1, r2
uxth r8, r9
xta:
sxtab r0, r0, r0
sxtab r0, r0, r0, ror #0
sxtab r9, r0, r0, ror #8
sxtab r0, r9, r0, ror #16
sxtab r0, r0, r9, ror #24
sxtab16 r1, r2, r3
sxtah r1, r2, r3
uxtab r1, r2, r3
uxtab16 r1, r2, r3
uxtah r1, r2, r3

2
gas/testsuite/gas/arm/thumbv6.d
View File

@ -7,7 +7,7 @@
Disassembly of section .text:
0+000 <[^>]*> b666 * cpsie ai
0+002 <[^>]*> b675 * cpsid af
0+004 <[^>]*> 4623 * cpy r3, r4
0+004 <[^>]*> 4623 * mov r3, r4
0+006 <[^>]*> ba3a * rev r2, r7
0+008 <[^>]*> ba4d * rev16 r5, r1
0+00a <[^>]*> baf3 * revsh r3, r6

16
gas/testsuite/gas/arm/vfp-bad.l
View File

@ -1,9 +1,9 @@
[^:]*: Assembler messages:
[^:]*:4: Error: garbage following instruction -- `fstd d0,\[r0\],#8'
[^:]*:5: Error: garbage following instruction -- `fstd d0,\[r0,#-8\]!'
[^:]*:6: Error: garbage following instruction -- `fsts s0,\[r0\],#8'
[^:]*:7: Error: garbage following instruction -- `fsts s0,\[r0,#-8\]!'
[^:]*:8: Error: garbage following instruction -- `fldd d0,\[r0\],#8'
[^:]*:9: Error: garbage following instruction -- `fldd d0,\[r0,#-8\]!'
[^:]*:10: Error: garbage following instruction -- `flds s0,\[r0\],#8'
[^:]*:11: Error: garbage following instruction -- `flds s0,\[r0,#-8\]!'
[^:]*:4: Error: instruction does not support writeback -- `fstd d0,\[r0\],#8'
[^:]*:5: Error: instruction does not support writeback -- `fstd d0,\[r0,#-8\]!'
[^:]*:6: Error: instruction does not support writeback -- `fsts s0,\[r0\],#8'
[^:]*:7: Error: instruction does not support writeback -- `fsts s0,\[r0,#-8\]!'
[^:]*:8: Error: instruction does not support writeback -- `fldd d0,\[r0\],#8'
[^:]*:9: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!'
[^:]*:10: Error: instruction does not support writeback -- `flds s0,\[r0\],#8'
[^:]*:11: Error: instruction does not support writeback -- `flds s0,\[r0,#-8\]!'

6
include/elf/ChangeLog
View File

@ -1,3 +1,9 @@
2005-05-17 Zack Weinberg <zack@codesourcery.com>
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
2005-05-14 Alan Modra <amodra@bigpond.net.au>
* ppc.h (DT_PPC_GOT): Rename from DT_PPC_GLINK.

242
include/elf/arm.h
View File

@ -38,7 +38,7 @@
#define EF_ARM_MAVERICK_FLOAT 0x800
/* Frame unwind information */
#define PT_ARM_EXIDX (PT_LOPROC + 1)
#define PT_ARM_EXIDX (PT_LOPROC + 1)
/* Other constants defined in the ARM ELF spec. version B-01. */
#define EF_ARM_SYMSARESORTED 0x04 /* NB conflicts with EF_INTERWORK */
@ -84,93 +84,159 @@
/* Relocation types. */
START_RELOC_NUMBERS (elf_arm_reloc_type)
RELOC_NUMBER (R_ARM_NONE, 0)
RELOC_NUMBER (R_ARM_PC24, 1)
RELOC_NUMBER (R_ARM_ABS32, 2)
RELOC_NUMBER (R_ARM_REL32, 3)
#ifdef OLD_ARM_ABI
RELOC_NUMBER (R_ARM_ABS8, 4)
RELOC_NUMBER (R_ARM_ABS16, 5)
RELOC_NUMBER (R_ARM_ABS12, 6)
RELOC_NUMBER (R_ARM_THM_ABS5, 7)
RELOC_NUMBER (R_ARM_THM_PC22, 8)
RELOC_NUMBER (R_ARM_SBREL32, 9)
RELOC_NUMBER (R_ARM_AMP_VCALL9, 10)
RELOC_NUMBER (R_ARM_THM_PC11, 11) /* Cygnus extension to abi: Thumb unconditional branch. */
RELOC_NUMBER (R_ARM_THM_PC9, 12) /* Cygnus extension to abi: Thumb conditional branch. */
RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 13)
RELOC_NUMBER (R_ARM_GNU_VTENTRY, 14)
#else /* not OLD_ARM_ABI */
RELOC_NUMBER (R_ARM_PC13, 4)
RELOC_NUMBER (R_ARM_ABS16, 5)
RELOC_NUMBER (R_ARM_ABS12, 6)
RELOC_NUMBER (R_ARM_THM_ABS5, 7)
RELOC_NUMBER (R_ARM_ABS8, 8)
RELOC_NUMBER (R_ARM_SBREL32, 9)
RELOC_NUMBER (R_ARM_THM_PC22, 10)
RELOC_NUMBER (R_ARM_THM_PC8, 11)
RELOC_NUMBER (R_ARM_AMP_VCALL9, 12)
RELOC_NUMBER (R_ARM_SWI24, 13)
RELOC_NUMBER (R_ARM_THM_SWI8, 14)
RELOC_NUMBER (R_ARM_XPC25, 15)
RELOC_NUMBER (R_ARM_THM_XPC22, 16)
RELOC_NUMBER (R_ARM_TLS_DTPMOD32, 17)
RELOC_NUMBER (R_ARM_TLS_DTPOFF32, 18)
RELOC_NUMBER (R_ARM_TLS_TPOFF32, 19)
#endif /* not OLD_ARM_ABI */
RELOC_NUMBER (R_ARM_COPY, 20) /* Copy symbol at runtime. */
RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* Create GOT entry. */
RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* Create PLT entry. */
RELOC_NUMBER (R_ARM_RELATIVE, 23) /* Adjust by program base. */
RELOC_NUMBER (R_ARM_GOTOFF, 24) /* 32 bit offset to GOT. */
RELOC_NUMBER (R_ARM_GOTPC, 25) /* 32 bit PC relative offset to GOT. */
RELOC_NUMBER (R_ARM_GOT32, 26) /* 32 bit GOT entry. */
RELOC_NUMBER (R_ARM_PLT32, 27) /* 32 bit PLT address. */
#ifdef OLD_ARM_ABI
FAKE_RELOC (FIRST_INVALID_RELOC, 28)
FAKE_RELOC (LAST_INVALID_RELOC, 249)
#else /* not OLD_ARM_ABI */
RELOC_NUMBER (R_ARM_CALL, 28)
RELOC_NUMBER (R_ARM_JUMP24, 29)
FAKE_RELOC (FIRST_INVALID_RELOC1, 30)
FAKE_RELOC (LAST_INVALID_RELOC1, 31)
RELOC_NUMBER (R_ARM_ALU_PCREL7_0, 32)
RELOC_NUMBER (R_ARM_ALU_PCREL15_8, 33)
RELOC_NUMBER (R_ARM_ALU_PCREL23_15, 34)
RELOC_NUMBER (R_ARM_LDR_SBREL_11_0, 35)
RELOC_NUMBER (R_ARM_ALU_SBREL_19_12, 36)
RELOC_NUMBER (R_ARM_ALU_SBREL_27_20, 37)
RELOC_NUMBER (R_ARM_TARGET1, 38)
RELOC_NUMBER (R_ARM_ROSEGREL32, 39)
RELOC_NUMBER (R_ARM_V4BX, 40)
RELOC_NUMBER (R_ARM_TARGET2, 41)
RELOC_NUMBER (R_ARM_PREL31, 42)
FAKE_RELOC (FIRST_INVALID_RELOC2, 43)
FAKE_RELOC (LAST_INVALID_RELOC2, 94)
RELOC_NUMBER (R_ARM_GOT_ABS, 95)
RELOC_NUMBER (R_ARM_GOT_PREL, 96)
RELOC_NUMBER (R_ARM_GOT_BREL12, 97)
RELOC_NUMBER (R_ARM_GOTOFF12, 98)
RELOC_NUMBER (R_ARM_GOTRELAX, 99)
RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100)
RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101)
RELOC_NUMBER (R_ARM_THM_PC11, 102) /* Cygnus extension to abi: Thumb unconditional branch. */
RELOC_NUMBER (R_ARM_THM_PC9, 103) /* Cygnus extension to abi: Thumb conditional branch. */
RELOC_NUMBER (R_ARM_TLS_GD32, 104)
RELOC_NUMBER (R_ARM_TLS_LDM32, 105)
RELOC_NUMBER (R_ARM_TLS_LDO32, 106)
RELOC_NUMBER (R_ARM_TLS_IE32, 107)
RELOC_NUMBER (R_ARM_TLS_LE32, 108)
FAKE_RELOC (FIRST_INVALID_RELOC3, 109)
FAKE_RELOC (LAST_INVALID_RELOC3, 248)
RELOC_NUMBER (R_ARM_RXPC25, 249)
#endif /* not OLD_ARM_ABI */
RELOC_NUMBER (R_ARM_RSBREL32, 250)
RELOC_NUMBER (R_ARM_THM_RPC22, 251)
RELOC_NUMBER (R_ARM_RREL32, 252)
RELOC_NUMBER (R_ARM_RABS32, 253)
RELOC_NUMBER (R_ARM_RPC24, 254)
RELOC_NUMBER (R_ARM_RBASE, 255)
/* AAELF official names and numbers. */
RELOC_NUMBER (R_ARM_NONE, 0)
RELOC_NUMBER (R_ARM_PC24, 1) /* deprecated */
RELOC_NUMBER (R_ARM_ABS32, 2)
RELOC_NUMBER (R_ARM_REL32, 3)
#ifndef OLD_ARM_ABI
RELOC_NUMBER (R_ARM_LDR_PC_G0, 4)
RELOC_NUMBER (R_ARM_ABS16, 5)
RELOC_NUMBER (R_ARM_ABS12, 6)
RELOC_NUMBER (R_ARM_THM_ABS5, 7)
RELOC_NUMBER (R_ARM_ABS8, 8)
RELOC_NUMBER (R_ARM_SBREL32, 9)
RELOC_NUMBER (R_ARM_THM_CALL, 10)
RELOC_NUMBER (R_ARM_THM_PC8, 11)
RELOC_NUMBER (R_ARM_BREL_ADJ, 12)
RELOC_NUMBER (R_ARM_SWI24, 13) /* obsolete */
RELOC_NUMBER (R_ARM_THM_SWI8, 14) /* obsolete */
#else
RELOC_NUMBER (R_ARM_ABS8, 4)
RELOC_NUMBER (R_ARM_ABS16, 5)
RELOC_NUMBER (R_ARM_ABS12, 6)
RELOC_NUMBER (R_ARM_THM_ABS5, 7)
RELOC_NUMBER (R_ARM_THM_CALL, 8)
RELOC_NUMBER (R_ARM_SBREL32, 9)
RELOC_NUMBER (R_ARM_BREL_ADJ, 10)
RELOC_NUMBER (R_ARM_THM_JUMP11, 11)
RELOC_NUMBER (R_ARM_THM_JUMP8, 12)
RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 13)
RELOC_NUMBER (R_ARM_GNU_VTENTRY, 14)
#endif
RELOC_NUMBER (R_ARM_XPC25, 15) /* obsolete */
RELOC_NUMBER (R_ARM_THM_XPC22, 16) /* obsolete */
RELOC_NUMBER (R_ARM_TLS_DTPMOD32, 17)
RELOC_NUMBER (R_ARM_TLS_DTPOFF32, 18)
RELOC_NUMBER (R_ARM_TLS_TPOFF32, 19)
RELOC_NUMBER (R_ARM_COPY, 20) /* Copy symbol at runtime. */
RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* Create GOT entry. */
RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* Create PLT entry. */
RELOC_NUMBER (R_ARM_RELATIVE, 23) /* Adjust by program base. */
RELOC_NUMBER (R_ARM_GOTOFF32, 24) /* 32 bit offset to GOT. */
RELOC_NUMBER (R_ARM_BASE_PREL, 25) /* 32 bit PC relative offset to GOT. */
RELOC_NUMBER (R_ARM_GOT_BREL, 26) /* 32 bit GOT entry. */
RELOC_NUMBER (R_ARM_PLT32, 27) /* deprecated - 32 bit PLT address. */
RELOC_NUMBER (R_ARM_CALL, 28)
RELOC_NUMBER (R_ARM_JUMP24, 29)
RELOC_NUMBER (R_ARM_THM_JUMP24, 30)
RELOC_NUMBER (R_ARM_BASE_ABS, 31)
RELOC_NUMBER (R_ARM_ALU_PCREL7_0, 32) /* obsolete */
RELOC_NUMBER (R_ARM_ALU_PCREL15_8, 33) /* obsolete */
RELOC_NUMBER (R_ARM_ALU_PCREL23_15, 34) /* obsolete */
RELOC_NUMBER (R_ARM_LDR_SBREL_11_0, 35) /* deprecated, should have _NC suffix */
RELOC_NUMBER (R_ARM_ALU_SBREL_19_12, 36) /* deprecated, should have _NC suffix */
RELOC_NUMBER (R_ARM_ALU_SBREL_27_20, 37) /* deprecated, should have _CK suffix */
RELOC_NUMBER (R_ARM_TARGET1, 38)
RELOC_NUMBER (R_ARM_SBREL31, 39) /* deprecated */
RELOC_NUMBER (R_ARM_V4BX, 40)
RELOC_NUMBER (R_ARM_TARGET2, 41)
RELOC_NUMBER (R_ARM_PREL31, 42)
RELOC_NUMBER (R_ARM_MOVW_ABS_NC, 43)
RELOC_NUMBER (R_ARM_MOVT_ABS, 44)
RELOC_NUMBER (R_ARM_MOVW_PREL_NC, 45)
RELOC_NUMBER (R_ARM_MOVT_PREL, 46)
RELOC_NUMBER (R_ARM_THM_MOVW_ABS_NC, 47)
RELOC_NUMBER (R_ARM_THM_MOVT_ABS, 48)
RELOC_NUMBER (R_ARM_THM_MOVW_PREL_NC, 49)
RELOC_NUMBER (R_ARM_THM_MOVT_PREL, 50)
RELOC_NUMBER (R_ARM_THM_JUMP19, 51)
RELOC_NUMBER (R_ARM_THM_JUMP6, 52)
RELOC_NUMBER (R_ARM_THM_ALU_PREL_11_0, 53)
RELOC_NUMBER (R_ARM_THM_PC12, 54)
RELOC_NUMBER (R_ARM_ABS32_NOI, 55)
RELOC_NUMBER (R_ARM_REL32_NOI, 56)
RELOC_NUMBER (R_ARM_ALU_PC_G0_NC, 57)
RELOC_NUMBER (R_ARM_ALU_PC_G0, 58)
RELOC_NUMBER (R_ARM_ALU_PC_G1_NC, 59)
RELOC_NUMBER (R_ARM_ALU_PC_G1, 60)
RELOC_NUMBER (R_ARM_ALU_PC_G2, 61)
RELOC_NUMBER (R_ARM_LDR_PC_G1, 62)
RELOC_NUMBER (R_ARM_LDR_PC_G2, 63)
RELOC_NUMBER (R_ARM_LDRS_PC_G0, 64)
RELOC_NUMBER (R_ARM_LDRS_PC_G1, 65)
RELOC_NUMBER (R_ARM_LDRS_PC_G2, 66)
RELOC_NUMBER (R_ARM_LDC_PC_G0, 67)
RELOC_NUMBER (R_ARM_LDC_PC_G1, 68)
RELOC_NUMBER (R_ARM_LDC_PC_G2, 69)
RELOC_NUMBER (R_ARM_ALU_SB_G0_NC, 70)
RELOC_NUMBER (R_ARM_ALU_SB_G0, 71)
RELOC_NUMBER (R_ARM_ALU_SB_G1_NC, 72)
RELOC_NUMBER (R_ARM_ALU_SB_G1, 73)
RELOC_NUMBER (R_ARM_ALU_SB_G2, 74)
RELOC_NUMBER (R_ARM_LDR_SB_G0, 75)
RELOC_NUMBER (R_ARM_LDR_SB_G1, 76)
RELOC_NUMBER (R_ARM_LDR_SB_G2, 77)
RELOC_NUMBER (R_ARM_LDRS_SB_G0, 78)
RELOC_NUMBER (R_ARM_LDRS_SB_G1, 79)
RELOC_NUMBER (R_ARM_LDRS_SB_G2, 80)
RELOC_NUMBER (R_ARM_LDC_G0, 81)
RELOC_NUMBER (R_ARM_LDC_G1, 82)
RELOC_NUMBER (R_ARM_LDC_G2, 83)
RELOC_NUMBER (R_ARM_MOVW_BREL_NC, 84)
RELOC_NUMBER (R_ARM_MOVT_BREL, 85)
RELOC_NUMBER (R_ARM_MOVW_BREL, 86)
RELOC_NUMBER (R_ARM_THM_MOVW_BREL_NC, 87)
RELOC_NUMBER (R_ARM_THM_MOVT_BREL, 88)
RELOC_NUMBER (R_ARM_THM_MOVW_BREL, 89)
/* 90-93 unallocated */
RELOC_NUMBER (R_ARM_PLT32_ABS, 94)
RELOC_NUMBER (R_ARM_GOT_ABS, 95)
RELOC_NUMBER (R_ARM_GOT_PREL, 96)
RELOC_NUMBER (R_ARM_GOT_BREL12, 97)
RELOC_NUMBER (R_ARM_GOTOFF12, 98)
RELOC_NUMBER (R_ARM_GOTRELAX, 99)
#ifndef OLD_ARM_ABI
RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100) /* deprecated - old C++ abi */
RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101) /* deprecated - old C++ abi */
RELOC_NUMBER (R_ARM_THM_JUMP11, 102)
RELOC_NUMBER (R_ARM_THM_JUMP8, 103)
#endif
RELOC_NUMBER (R_ARM_TLS_GD32, 104)
RELOC_NUMBER (R_ARM_TLS_LDM32, 105)
RELOC_NUMBER (R_ARM_TLS_LDO32, 106)
RELOC_NUMBER (R_ARM_TLS_IE32, 107)
RELOC_NUMBER (R_ARM_TLS_LE32, 108)
RELOC_NUMBER (R_ARM_TLS_LDO12, 109)
RELOC_NUMBER (R_ARM_TLS_LE12, 110)
RELOC_NUMBER (R_ARM_TLS_IE12GP, 111)
/* 112 - 127 private range */
RELOC_NUMBER (R_ARM_ME_TOO, 128) /* obsolete */
/* Extensions? R=read-only? */
RELOC_NUMBER (R_ARM_RXPC25, 249)
RELOC_NUMBER (R_ARM_RSBREL32, 250)
RELOC_NUMBER (R_ARM_THM_RPC22, 251)
RELOC_NUMBER (R_ARM_RREL32, 252)
RELOC_NUMBER (R_ARM_RABS32, 253)
RELOC_NUMBER (R_ARM_RPC24, 254)
RELOC_NUMBER (R_ARM_RBASE, 255)
/* Unofficial names for some of the relocs. */
FAKE_RELOC (R_ARM_GOTOFF, R_ARM_GOTOFF32) /* 32 bit offset to GOT. */
FAKE_RELOC (R_ARM_THM_PC22, R_ARM_THM_CALL)
FAKE_RELOC (R_ARM_THM_PC11, R_ARM_THM_JUMP11)
FAKE_RELOC (R_ARM_THM_PC9, R_ARM_THM_JUMP8)
/* Relocs with both a different name, and (apparently) different meaning in
GNU usage. */
FAKE_RELOC (R_ARM_GOTPC, R_ARM_BASE_PREL) /* 32 bit PC relative offset to GOT. */
FAKE_RELOC (R_ARM_GOT32, R_ARM_GOT_BREL) /* 32 bit GOT entry. */
FAKE_RELOC (R_ARM_ROSEGREL32, R_ARM_SBREL31) /* ??? */
FAKE_RELOC (R_ARM_AMP_VCALL9, R_ARM_BREL_ADJ) /* Thumb-something. Not used. */
#ifndef OLD_ARM_ABI
FAKE_RELOC (R_ARM_PC13, R_ARM_LDR_PC_G0) /* Unclear whether meaning is different. */
#endif
END_RELOC_NUMBERS (R_ARM_max)
/* The name of the note section used to identify arm variants. */

8
ld/ChangeLog
View File

@ -1,3 +1,7 @@
2005-05-17 Zack Weinberg <zack@codesourcery.com>
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-17 Daniel Jacobowitz <dan@codesourcery.com>
* Makefile.am (ldver.texi): Don't use $<.
@ -50,8 +54,8 @@
2005-05-17 Lennert Buytenhek <buytenh@wantstofly.org>
Peter S. Mazinger" <ps.m@gmx.net>
* emulparams/armelf_linux.sh (GENERATE_PIE_SCRIPT): Define as "yes".
* emulparams/hppalinux.sh (GENERATE_PIE_SCRIPT): Define as "yes".
* emulparams/armelf_linux.sh (GENERATE_PIE_SCRIPT): Define as "yes".
* emulparams/hppalinux.sh (GENERATE_PIE_SCRIPT): Define as "yes".
2005-05-17 Julian Brown <julian@codesourcery.com>

2
ld/testsuite/ld-arm/mixed-app.d
View File

@ -49,7 +49,7 @@ Disassembly of section .text:
.* <app_tfunc>:
.*: b500 push {lr}
.*: (ffc.f7ff|f7ffffc.) bl .* <_start-0x..>
.*: f7ff ffc. bl .* <_start-0x..>
.*: bd00 pop {pc}
.*: 4770 bx lr
.*: 46c0 nop \(mov r8, r8\)

17
opcodes/ChangeLog
View File

@ -1,3 +1,16 @@
2005-05-17 Zack Weinberg <zack@codesourcery.com>
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
2005-05-07 H.J. Lu <hongjiu.lu@intel.com>
PR 843
@ -124,11 +137,11 @@
2005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
Nick Clifton <nickc@redhat.com>
* vax-dis.c: (entry_addr): New varible: An array of user supplied
function entry mask addresses.
(entry_addr_occupied_slots): New variable: The number of occupied
elements in entry_addr.
elements in entry_addr.
(entry_addr_total_slots): New variable: The total number of
elements in entry_addr.
(parse_disassembler_options): New function. Fills in the entry_addr

1240
opcodes/arm-dis.c
View File

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