x86: Allow 32-bit registers for tpause and umwait
Since only the first 32 bits of input operand are used for tpause and umwait, the REX.W bit is skipped. Both 32-bit registers and 64-bit registers are allowed. gas/ * testsuite/gas/i386/x86-64-waitpkg.s: Add 32-bit registers tests for tpause and umwait. * testsuite/gas/i386/x86-64-waitpkg-intel.d: Updated. * testsuite/gas/i386/x86-64-waitpkg.d: Likewise. opcodes/ * i386-dis.c (prefix_table): Replace Em with Edq on tpause and umwait. * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in 64-bit mode. * i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
parent
7c31c22f1a
commit
ae1d384372
@ -1,3 +1,10 @@
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2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
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* testsuite/gas/i386/x86-64-waitpkg.s: Add 32-bit registers
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tests for tpause and umwait.
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* testsuite/gas/i386/x86-64-waitpkg-intel.d: Updated.
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* testsuite/gas/i386/x86-64-waitpkg.d: Likewise.
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2018-04-12 John Darrington <john@darrington.wattle.id.au>
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* as.c (main): Fail if the output is the same as one of the input
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@ -12,8 +12,12 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*f3 0f ae f0[ ]*umonitor rax
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[ ]*[a-f0-9]+:[ ]*f3 41 0f ae f2[ ]*umonitor r10
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[ ]*[a-f0-9]+:[ ]*67 f3 41 0f ae f2[ ]*umonitor r10d
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait rcx
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[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait r10
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause rcx
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[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause r10
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait ecx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait ecx
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[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait r10d
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[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait r10d
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause ecx
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause ecx
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[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause r10d
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[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause r10d
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#pass
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@ -12,8 +12,12 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*f3 0f ae f0[ ]*umonitor %rax
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[ ]*[a-f0-9]+:[ ]*f3 41 0f ae f2[ ]*umonitor %r10
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[ ]*[a-f0-9]+:[ ]*67 f3 41 0f ae f2[ ]*umonitor %r10d
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait %rcx
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[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait %r10
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause %rcx
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[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause %r10
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait %ecx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait %ecx
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[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait %r10d
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[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait %r10d
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause %ecx
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause %ecx
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[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause %r10d
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[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause %r10d
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#pass
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@ -5,7 +5,11 @@ _start:
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umonitor %rax
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umonitor %r10
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umonitor %r10d
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umwait %ecx
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umwait %rcx
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umwait %r10
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umwait %r10d
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tpause %ecx
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tpause %rcx
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tpause %r10
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tpause %r10d
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@ -1,3 +1,11 @@
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2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (prefix_table): Replace Em with Edq on tpause and
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umwait.
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* i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
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64-bit mode.
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* i386-tbl.h: Regenerated.
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2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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* i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
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@ -4206,8 +4206,8 @@ static const struct dis386 prefix_table[][4] = {
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{
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{ RM_TABLE (RM_0FAE_REG_6) },
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{ "umonitor", { Eva }, PREFIX_OPCODE },
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{ "tpause", { Em }, PREFIX_OPCODE },
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{ "umwait", { Em }, PREFIX_OPCODE },
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{ "tpause", { Edq }, PREFIX_OPCODE },
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{ "umwait", { Edq }, PREFIX_OPCODE },
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},
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/* PREFIX_0FAE_REG_7 */
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@ -5904,10 +5904,8 @@ pconfig, 0, 0x0f01c5, None, 3, CpuPCONFIG, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS
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umonitor, 1, 0xf30fae, 0x6, 2, CpuWAITPKG|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOp0, { Reg16|Reg32 }
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umonitor, 1, 0xf30fae, 0x6, 2, CpuWAITPKG|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOp0|NoRex64, { Reg32|Reg64 }
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tpause, 1, 0x660fae, 0x6, 2, CpuWAITPKG|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
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tpause, 1, 0x660fae, 0x6, 2, CpuWAITPKG|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64 }
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tpause, 1, 0x660fae, 0x6, 2, CpuWAITPKG, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64 }
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umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
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umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64 }
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umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64 }
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// WAITPKG instructions end.
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@ -93810,27 +93810,13 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 0, 0, 0, 1, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0 } } } },
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{ "tpause", 1, 0x660fae, 0x6, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 0, 0, 1, 0, 0 } },
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0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0 } } } },
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{ "umwait", 1, 0xf20fae, 0x6, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -93838,27 +93824,13 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 0, 0, 0, 1, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0 } } } },
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{ "umwait", 1, 0xf20fae, 0x6, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 0, 0, 1, 0, 0 } },
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0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0 } } } },
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{ NULL, 0, 0, 0, 0,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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