[PATCH 35/57][Arm][GAS] Add support for MVE instructions: vshlc and vshll
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vshll): New encoding function. (do_mve_vshlc): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vshlc-bad.d: New test. * testsuite/gas/arm/mve-vshlc-bad.l: New test. * testsuite/gas/arm/mve-vshlc-bad.s: New test. * testsuite/gas/arm/mve-vshll-bad.d: New test. * testsuite/gas/arm/mve-vshll-bad.l: New test. * testsuite/gas/arm/mve-vshll-bad.s: New test.
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Andre Vieira
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@ -1,3 +1,15 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_mve_vshll): New encoding function.
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(do_mve_vshlc): Likewise.
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(insns): Add entries for MVE mnemonics.
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* testsuite/gas/arm/mve-vshlc-bad.d: New test.
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* testsuite/gas/arm/mve-vshlc-bad.l: New test.
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* testsuite/gas/arm/mve-vshlc-bad.s: New test.
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* testsuite/gas/arm/mve-vshll-bad.d: New test.
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* testsuite/gas/arm/mve-vshll-bad.l: New test.
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* testsuite/gas/arm/mve-vshll-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (enum operand_parse_code): Add new operand.
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@ -15771,6 +15771,63 @@ do_mve_vmlas (void)
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inst.is_neon = 1;
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}
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static void
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do_mve_vshll (void)
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{
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struct neon_type_el et
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= neon_check_type (2, NS_QQI, N_EQK, N_S8 | N_U8 | N_S16 | N_U16 | N_KEY);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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int imm = inst.operands[2].imm;
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constraint (imm < 1 || (unsigned)imm > et.size,
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_("immediate value out of range"));
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if ((unsigned)imm == et.size)
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{
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inst.instruction |= neon_logbits (et.size) << 18;
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inst.instruction |= 0x110001;
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}
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else
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{
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inst.instruction |= (et.size + imm) << 16;
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inst.instruction |= 0x800140;
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}
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inst.instruction |= (et.type == NT_unsigned) << 28;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= HI1 (inst.operands[1].reg) << 5;
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inst.instruction |= LOW4 (inst.operands[1].reg);
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inst.is_neon = 1;
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}
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static void
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do_mve_vshlc (void)
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{
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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if (inst.operands[1].reg == REG_PC)
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as_tsktsk (MVE_BAD_PC);
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else if (inst.operands[1].reg == REG_SP)
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as_tsktsk (MVE_BAD_SP);
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int imm = inst.operands[2].imm;
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constraint (imm < 1 || imm > 32, _("immediate value out of range"));
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= (imm & 0x1f) << 16;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= inst.operands[1].reg;
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inst.is_neon = 1;
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}
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static void
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do_mve_vshrn (void)
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{
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@ -25179,6 +25236,10 @@ static const struct asm_opcode insns[] =
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mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mCEF(vqrshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mToC("vshlc", eea00fc0, 3, (RMQ, RR, I32z), mve_vshlc),
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mToC("vshllt", ee201e00, 3, (RMQ, RMQ, I32), mve_vshll),
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mToC("vshllb", ee200e00, 3, (RMQ, RMQ, I32), mve_vshll),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
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5
gas/testsuite/gas/arm/mve-vshlc-bad.d
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5
gas/testsuite/gas/arm/mve-vshlc-bad.d
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@ -0,0 +1,5 @@
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#name: bad MVE VSHLC instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vshlc-bad.l
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.*: +file format .*arm.*
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16
gas/testsuite/gas/arm/mve-vshlc-bad.l
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16
gas/testsuite/gas/arm/mve-vshlc-bad.l
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@ -0,0 +1,16 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: immediate value out of range -- `vshlc q0,r1,#0'
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[^:]*:11: Error: immediate value out of range -- `vshlc q0,r1,#33'
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[^:]*:12: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:13: Warning: instruction is UNPREDICTABLE with PC operand
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Error: syntax error -- `vshlceq q0,r1,#2'
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[^:]*:17: Error: syntax error -- `vshlceq q0,r1,#2'
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[^:]*:19: Error: syntax error -- `vshlceq q0,r1,#2'
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[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vshlct q0,r1,#2'
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[^:]*:22: Error: instruction missing MVE vector predication code -- `vshlc q0,r1,#2'
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22
gas/testsuite/gas/arm/mve-vshlc-bad.s
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22
gas/testsuite/gas/arm/mve-vshlc-bad.s
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@ -0,0 +1,22 @@
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.macro cond
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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vshlc q0, r1, #2
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.endr
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.endm
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.syntax unified
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.thumb
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vshlc q0, r1, #0
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vshlc q0, r1, #33
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vshlc q0, sp, #1
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vshlc q0, pc, #1
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cond
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it eq
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vshlceq q0, r1, #2
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vshlceq q0, r1, #2
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vpst
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vshlceq q0, r1, #2
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vshlct q0, r1, #2
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vpst
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vshlc q0, r1, #2
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5
gas/testsuite/gas/arm/mve-vshll-bad.d
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5
gas/testsuite/gas/arm/mve-vshll-bad.d
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@ -0,0 +1,5 @@
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#name: bad MVE VSHLLT and VSHLLB instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vshll-bad.l
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.*: +file format .*arm.*
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35
gas/testsuite/gas/arm/mve-vshll-bad.l
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35
gas/testsuite/gas/arm/mve-vshll-bad.l
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@ -0,0 +1,35 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vshllt.s32 q0,q1,#1'
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[^:]*:11: Error: bad type in SIMD instruction -- `vshllt.i8 q0,q1,#1'
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[^:]*:12: Error: immediate value out of range -- `vshllt.u8 q0,q1,#0'
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[^:]*:13: Error: immediate value out of range -- `vshllt.u8 q0,q1,#9'
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[^:]*:14: Error: immediate value out of range -- `vshllt.s16 q0,q1,#0'
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[^:]*:15: Error: immediate value out of range -- `vshllt.s16 q0,q1,#17'
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[^:]*:16: Error: bad type in SIMD instruction -- `vshllb.s32 q0,q1,#1'
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[^:]*:17: Error: bad type in SIMD instruction -- `vshllb.i8 q0,q1,#1'
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[^:]*:18: Error: immediate value out of range -- `vshllb.u8 q0,q1,#0'
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[^:]*:19: Error: immediate value out of range -- `vshllb.u8 q0,q1,#9'
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[^:]*:20: Error: immediate value out of range -- `vshllb.s16 q0,q1,#0'
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[^:]*:21: Error: immediate value out of range -- `vshllb.s16 q0,q1,#17'
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Error: syntax error -- `vshllteq.s8 q0,q1,#1'
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[^:]*:26: Error: syntax error -- `vshllteq.s8 q0,q1,#1'
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[^:]*:28: Error: syntax error -- `vshllteq.s8 q0,q1,#1'
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[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vshlltt.s8 q0,q1,#1'
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[^:]*:31: Error: instruction missing MVE vector predication code -- `vshllt.s8 q0,q1,#1'
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[^:]*:33: Error: syntax error -- `vshllbeq.s8 q0,q1,#1'
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[^:]*:34: Error: syntax error -- `vshllbeq.s8 q0,q1,#1'
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[^:]*:36: Error: syntax error -- `vshllbeq.s8 q0,q1,#1'
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[^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vshllbt.s8 q0,q1,#1'
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[^:]*:39: Error: instruction missing MVE vector predication code -- `vshllb.s8 q0,q1,#1'
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39
gas/testsuite/gas/arm/mve-vshll-bad.s
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39
gas/testsuite/gas/arm/mve-vshll-bad.s
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@ -0,0 +1,39 @@
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.macro cond op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s16 q0, q1, #4
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.endr
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.endm
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.syntax unified
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.thumb
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vshllt.s32 q0, q1, #1
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vshllt.i8 q0, q1, #1
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vshllt.u8 q0, q1, #0
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vshllt.u8 q0, q1, #9
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vshllt.s16 q0, q1, #0
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vshllt.s16 q0, q1, #17
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vshllb.s32 q0, q1, #1
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vshllb.i8 q0, q1, #1
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vshllb.u8 q0, q1, #0
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vshllb.u8 q0, q1, #9
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vshllb.s16 q0, q1, #0
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vshllb.s16 q0, q1, #17
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cond vshllt
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cond vshllb
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it eq
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vshllteq.s8 q0, q1, #1
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vshllteq.s8 q0, q1, #1
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vpst
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vshllteq.s8 q0, q1, #1
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vshlltt.s8 q0, q1, #1
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vpst
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vshllt.s8 q0, q1, #1
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it eq
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vshllbeq.s8 q0, q1, #1
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vshllbeq.s8 q0, q1, #1
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vpst
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vshllbeq.s8 q0, q1, #1
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vshllbt.s8 q0, q1, #1
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vpst
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vshllb.s8 q0, q1, #1
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