Add support for Intel TDX instructions.
gas/ * NEWS: Add TDX. * config/tc-i386.c (cpu_arch): Add .tdx. (cpu_noarch): Likewise. * doc/c-i386.texi: Document tdx. * testsuite/gas/i386/i386.exp: Run tdx tests. * testsuite/gas/i386/tdx.d: Likewise. * testsuite/gas/i386/tdx.s: Likewise. * testsuite/gas/i386/x86-64-tdx.d: Likewise. * testsuite/gas/i386/x86-64-tdx.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5, PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7, X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2, X86_64_0F01_REG_1_RM_7_P_2. (prefix_table): Likewise. (x86_64_table): Likewise. (rm_table): Likewise. * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS and CPU_ANY_TDX_FLAGS. (cpu_flags): Add CpuTDX. * i386-opc.h (enum): Add CpuTDX. (i386_cpu_flags): Add cputdx. * i386-opc.tbl: Add TDX insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
This commit is contained in:
Cui,Lili
parent
7469ddd78f
commit
81d54bb7ae
@ -1,4 +1,16 @@
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20200-09-17 Cooper Qu <cooper.qu@linux.alibaba.com>
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2020-09-24 Lili Cui <lili.cui@intel.com>
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* NEWS: Add TDX.
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* config/tc-i386.c (cpu_arch): Add .tdx.
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(cpu_noarch): Likewise.
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* doc/c-i386.texi: Document tdx.
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* testsuite/gas/i386/i386.exp: Run tdx tests.
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* testsuite/gas/i386/tdx.d: Likewise.
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* testsuite/gas/i386/tdx.s: Likewise.
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* testsuite/gas/i386/x86-64-tdx.d: Likewise.
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* testsuite/gas/i386/x86-64-tdx.s: Likewise.
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2020-09-17 Cooper Qu <cooper.qu@linux.alibaba.com>
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* config/tc-csky.c (parse_type_ctrlreg): Use function
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csky_get_control_regno to operand.
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1
gas/NEWS
1
gas/NEWS
@ -1,4 +1,5 @@
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-*- text -*-
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* Add support for Intel TDX instructions.
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* Add support for Intel Key Locker instructions.
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@ -1220,6 +1220,8 @@ static const arch_entry cpu_arch[] =
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CPU_AVX512_BF16_FLAGS, 0 },
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{ STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN,
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CPU_AVX512_VP2INTERSECT_FLAGS, 0 },
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{ STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN,
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CPU_TDX_FLAGS, 0 },
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{ STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN,
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CPU_ENQCMD_FLAGS, 0 },
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{ STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN,
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@ -1282,6 +1284,7 @@ static const noarch_entry cpu_noarch[] =
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{ STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS },
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{ STRING_COMMA_LEN ("noavx512_vp2intersect"),
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CPU_ANY_AVX512_VP2INTERSECT_FLAGS },
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{ STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS },
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{ STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS },
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{ STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS },
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{ STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS },
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@ -209,6 +209,7 @@ accept various extension mnemonics. For example,
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@code{avx512_vnni},
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@code{avx512_bitalg},
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@code{avx512_vp2intersect},
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@code{tdx},
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@code{avx512_bf16},
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@code{noavx512f},
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@code{noavx512cd},
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@ -226,6 +227,7 @@ accept various extension mnemonics. For example,
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@code{noavx512_vnni},
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@code{noavx512_bitalg},
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@code{noavx512_vp2intersect},
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@code{notdx},
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@code{noavx512_bf16},
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@code{noenqcmd},
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@code{noserialize},
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@ -1503,6 +1505,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
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@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
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@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
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@item @samp{.tdx}
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@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
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@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
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@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
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@ -489,6 +489,7 @@ if [gas_32_check] then {
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run_dump_test "enqcmd-intel"
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run_list_test "enqcmd-inval"
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run_dump_test "serialize"
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run_dump_test "tdx"
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run_dump_test "tsxldtrk"
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run_dump_test "vp2intersect"
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run_dump_test "vp2intersect-intel"
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@ -1097,6 +1098,7 @@ if [gas_64_check] then {
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run_dump_test "x86-64-enqcmd-intel"
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run_list_test "x86-64-enqcmd-inval"
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run_dump_test "x86-64-serialize"
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run_dump_test "x86-64-tdx"
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run_dump_test "x86-64-tsxldtrk"
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run_dump_test "x86-64-vp2intersect"
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run_dump_test "x86-64-vp2intersect-intel"
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12
gas/testsuite/gas/i386/tdx.d
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12
gas/testsuite/gas/i386/tdx.d
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@ -0,0 +1,12 @@
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#as:
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#objdump: -dw
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#name: TDX insns
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#source: tdx.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 66 0f 01 cc + tdcall *
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#pass
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5
gas/testsuite/gas/i386/tdx.s
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5
gas/testsuite/gas/i386/tdx.s
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@ -0,0 +1,5 @@
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# Check TDX instructions.
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.text
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_start:
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tdcall
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15
gas/testsuite/gas/i386/x86-64-tdx.d
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15
gas/testsuite/gas/i386/x86-64-tdx.d
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@ -0,0 +1,15 @@
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#as:
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#objdump: -dw
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#name: x86_64 TDX insns
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#source: x86-64-tdx.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 66 0f 01 cc + tdcall *
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[ ]*[a-f0-9]+: 66 0f 01 cd + seamret *
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[ ]*[a-f0-9]+: 66 0f 01 ce + seamops *
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[ ]*[a-f0-9]+: 66 0f 01 cf + seamcall *
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#pass
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8
gas/testsuite/gas/i386/x86-64-tdx.s
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8
gas/testsuite/gas/i386/x86-64-tdx.s
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@ -0,0 +1,8 @@
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# Check TDX instructions.
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.text
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_start:
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tdcall
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seamret
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seamops
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seamcall
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@ -1,3 +1,21 @@
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2020-09-24 Lili Cui <lili.cui@intel.com>
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* i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
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PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
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X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
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X86_64_0F01_REG_1_RM_7_P_2.
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(prefix_table): Likewise.
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(x86_64_table): Likewise.
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(rm_table): Likewise.
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* i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
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and CPU_ANY_TDX_FLAGS.
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(cpu_flags): Add CpuTDX.
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* i386-opc.h (enum): Add CpuTDX.
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(i386_cpu_flags): Add cputdx.
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* i386-opc.tbl: Add TDX insns.
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* i386-init.h: Regenerate.
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* i386-tbl.h: Likewise.
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2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
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opcodes/
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@ -952,6 +952,10 @@ enum
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enum
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{
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PREFIX_90 = 0,
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PREFIX_0F01_REG_1_RM_4,
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PREFIX_0F01_REG_1_RM_5,
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PREFIX_0F01_REG_1_RM_6,
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PREFIX_0F01_REG_1_RM_7,
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PREFIX_0F01_REG_3_RM_1,
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PREFIX_0F01_REG_5_MOD_0,
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PREFIX_0F01_REG_5_MOD_3_RM_0,
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@ -1175,6 +1179,9 @@ enum
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X86_64_EA,
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X86_64_0F01_REG_0,
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X86_64_0F01_REG_1,
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X86_64_0F01_REG_1_RM_5_PREFIX_2,
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X86_64_0F01_REG_1_RM_6_PREFIX_2,
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X86_64_0F01_REG_1_RM_7_PREFIX_2,
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X86_64_0F01_REG_2,
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X86_64_0F01_REG_3,
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X86_64_0F24,
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@ -3083,6 +3090,38 @@ static const struct dis386 prefix_table[][4] = {
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{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
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},
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/* PREFIX_0F01_REG_1_RM_4 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "tdcall", { Skip_MODRM }, 0 },
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{ Bad_Opcode },
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},
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/* PREFIX_0F01_REG_1_RM_5 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
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{ Bad_Opcode },
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},
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/* PREFIX_0F01_REG_1_RM_6 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
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{ Bad_Opcode },
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},
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/* PREFIX_0F01_REG_1_RM_7 */
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{
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{ "encls", { Skip_MODRM }, 0 },
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{ Bad_Opcode },
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{ X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
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{ Bad_Opcode },
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},
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/* PREFIX_0F01_REG_3_RM_1 */
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{
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{ "vmmcall", { Skip_MODRM }, 0 },
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@ -4205,6 +4244,24 @@ static const struct dis386 x86_64_table[][2] = {
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{ "sidt", { M }, 0 },
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},
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/* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
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{
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{ Bad_Opcode },
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{ "seamret", { Skip_MODRM }, 0 },
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},
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/* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
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{
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{ Bad_Opcode },
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{ "seamops", { Skip_MODRM }, 0 },
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},
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/* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
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{
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{ Bad_Opcode },
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{ "seamcall", { Skip_MODRM }, 0 },
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},
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/* X86_64_0F01_REG_2 */
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{
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{ "lgdt{Q|Q}", { M }, 0 },
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@ -8784,10 +8841,10 @@ static const struct dis386 rm_table[][8] = {
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{ "mwait", { { OP_Mwait, 0 } }, 0 },
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{ "clac", { Skip_MODRM }, 0 },
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{ "stac", { Skip_MODRM }, 0 },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "encls", { Skip_MODRM }, 0 },
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{ PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
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{ PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
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{ PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
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{ PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
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},
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{
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/* RM_0F01_REG_2 */
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@ -313,6 +313,8 @@ static initializer cpu_flag_init[] =
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"CpuSERIALIZE" },
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{ "CPU_AVX512_VP2INTERSECT_FLAGS",
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"CpuAVX512_VP2INTERSECT" },
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{ "CPU_TDX_FLAGS",
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"CpuTDX" },
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{ "CPU_RDPRU_FLAGS",
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"CpuRDPRU" },
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{ "CPU_MCOMMIT_FLAGS",
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@ -409,6 +411,8 @@ static initializer cpu_flag_init[] =
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"CpuSERIALIZE" },
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{ "CPU_ANY_AVX512_VP2INTERSECT_FLAGS",
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"CpuAVX512_VP2INTERSECT" },
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{ "CPU_ANY_TDX_FLAGS",
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"CpuTDX" },
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{ "CPU_ANY_TSXLDTRK_FLAGS",
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"CpuTSXLDTRK" },
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{ "CPU_ANY_KL_FLAGS",
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@ -619,6 +623,7 @@ static bitfield cpu_flags[] =
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BITFIELD (CpuAVX512_BITALG),
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BITFIELD (CpuAVX512_BF16),
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BITFIELD (CpuAVX512_VP2INTERSECT),
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BITFIELD (CpuTDX),
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BITFIELD (CpuMWAITX),
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BITFIELD (CpuCLZERO),
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BITFIELD (CpuOSPKE),
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File diff suppressed because it is too large
Load Diff
@ -210,6 +210,8 @@ enum
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CpuAVX512_BF16,
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/* Intel AVX-512 VP2INTERSECT Instructions support required. */
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CpuAVX512_VP2INTERSECT,
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/* TDX Instructions support required. */
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CpuTDX,
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/* mwaitx instruction required */
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CpuMWAITX,
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/* Clzero instruction required */
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@ -375,6 +377,7 @@ typedef union i386_cpu_flags
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unsigned int cpuavx512_bitalg:1;
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unsigned int cpuavx512_bf16:1;
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unsigned int cpuavx512_vp2intersect:1;
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unsigned int cputdx:1;
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unsigned int cpumwaitx:1;
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unsigned int cpuclzero:1;
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unsigned int cpuospke:1;
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@ -4133,3 +4133,12 @@ aesencwide256kl, 1, 0xf30f38d8, 0x2, 3, CpuWideKL, Modrm|No_bSuf|No_wSuf|No_lSuf
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aesdecwide256kl, 1, 0xf30f38d8, 0x3, 3, CpuWideKL, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
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// KEYLOCKER instructions end.
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// TDX instructions.
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tdcall, 0, 0x660f01cc, None, 3, CpuTDX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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seamret, 0, 0x660f01cd, None, 3, CpuTDX|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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seamops, 0, 0x660f01ce, None, 3, CpuTDX|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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seamcall, 0, 0x660f01cf, None, 3, CpuTDX|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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// TDX instructions end.
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8164
opcodes/i386-tbl.h
8164
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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