Add AMD znver3 processor support
gas/ * config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags. (i386_align_code): Add PROCESSOR_ZNVER cases. * doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync. * gas/i386/i386.exp: Add new znver3 test cases. * gas/i386/arch-14-znver3.d: New. * gas/i386/arch-14.d: New. * gas/i386/arch-14.s: New. * gas/i386/invlpgb.d: New. * gas/i386/invlpgb64.d: New. * gas/i386/invlpgb.s: New. * gas/i386/snp.d: New. * gas/i386/snp64.d: New. * gas/i386/snp.s: New. * gas/i386/tlbsync.d: New. * gas/i386/tlbsync.s: New. * gas/i386/x86-64-arch-4-znver3.d: New. * gas/i386/x86-64-arch-4.d: New. * gas/i386/x86-64-arch-4.s: New. opcodes/ * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb. * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS, CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS. Add CPU_ZNVER3_FLAGS. (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate, rmpupdate, rmpadjust. * i386-init.h: Re-generated. * i386-tbl.h: Re-generated.
This commit is contained in:
Ganesh Gopalasubramanian
H.J. Lu
parent
c4464adef2
commit
646cc3e010
@ -1,3 +1,24 @@
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2020-10-20 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
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* config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags.
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(i386_align_code): Add PROCESSOR_ZNVER cases.
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* doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync.
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* gas/i386/i386.exp: Add new znver3 test cases.
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* gas/i386/arch-14-znver3.d: New.
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* gas/i386/arch-14.d: New.
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* gas/i386/arch-14.s: New.
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* gas/i386/invlpgb.d: New.
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* gas/i386/invlpgb64.d: New.
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* gas/i386/invlpgb.s: New.
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* gas/i386/snp.d: New.
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* gas/i386/snp64.d: New.
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* gas/i386/snp.s: New.
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* gas/i386/tlbsync.d: New.
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* gas/i386/tlbsync.s: New.
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* gas/i386/x86-64-arch-4-znver3.d: New.
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* gas/i386/x86-64-arch-4.d: New.
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* gas/i386/x86-64-arch-4.s: New.
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2020-10-17 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/25878
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@ -1014,6 +1014,8 @@ static const arch_entry cpu_arch[] =
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CPU_ZNVER1_FLAGS, 0 },
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{ STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
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CPU_ZNVER2_FLAGS, 0 },
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{ STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER,
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CPU_ZNVER3_FLAGS, 0 },
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{ STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
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CPU_BTVER1_FLAGS, 0 },
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{ STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
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@ -125,6 +125,7 @@ processor names are recognized:
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@code{bdver4},
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@code{znver1},
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@code{znver2},
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@code{znver3},
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@code{btver1},
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@code{btver2},
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@code{generic32} and
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@ -285,6 +286,9 @@ accept various extension mnemonics. For example,
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@code{3dnowa},
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@code{sse4a},
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@code{sse5},
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@code{snp},
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@code{invlpgb},
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@code{tlbsync},
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@code{svme} and
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@code{padlock}.
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Note that rather than extending a basic instruction set, the extension
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@ -1496,8 +1500,8 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
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@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
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@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
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@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
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@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
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@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3}
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@item @samp{btver1} @tab @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
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@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
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@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
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@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
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@ -1526,7 +1530,8 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
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@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
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@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
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@item @samp{.mcommit} @tab @samp{.sev_es}
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@item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb}
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@item @samp{.tlbsync}
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@end multitable
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Apart from the warning, there are only two other effects on
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5
gas/testsuite/gas/i386/arch-14-znver3.d
Normal file
5
gas/testsuite/gas/i386/arch-14-znver3.d
Normal file
@ -0,0 +1,5 @@
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#source: arch-14.s
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#as: -march=znver3
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#objdump: -dw
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#name: i386 arch 14 (znver3)
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#dump: arch-14.d
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14
gas/testsuite/gas/i386/arch-14.d
Normal file
14
gas/testsuite/gas/i386/arch-14.d
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@ -0,0 +1,14 @@
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#objdump: -dw
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#name: i386 arch 14
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.*: file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[0-9a-f]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 ff[ ]+tlbsync[ ]*
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[ ]*[a-f0-9]+:[ ]*f2 0f 01 ff[ ]+pvalidate[ ]*
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[ ]*[a-f0-9]+:[ ]*0f 01 ee[ ]+rdpkru[ ]*
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[ ]*[a-f0-9]+:[ ]*0f 01 ef[ ]+wrpkru[ ]*
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#pass
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12
gas/testsuite/gas/i386/arch-14.s
Normal file
12
gas/testsuite/gas/i386/arch-14.s
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@ -0,0 +1,12 @@
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# Test -march=
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.text
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#INVLPGB
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invlpgb
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#TLBSYNC
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tlbsync
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#SNP - Secure Nested Paging support
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pvalidate
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#OSPKE
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rdpkru
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wrpkru
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@ -183,6 +183,7 @@ if [gas_32_check] then {
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run_dump_test "arch-10-bdver4"
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run_dump_test "arch-13-znver1"
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run_dump_test "arch-13-znver2"
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run_dump_test "arch-14-znver3"
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run_dump_test "arch-10-btver1"
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run_dump_test "arch-10-btver2"
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run_list_test "arch-10-1" "-march=generic32 -I${srcdir}/$subdir -al"
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@ -192,6 +193,7 @@ if [gas_32_check] then {
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run_dump_test "arch-11"
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run_dump_test "arch-12"
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run_dump_test "arch-13"
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run_dump_test "arch-14"
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run_dump_test "8087"
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run_dump_test "287"
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run_dump_test "387"
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@ -462,6 +464,9 @@ if [gas_32_check] then {
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run_list_test "avx-vnni-inval"
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run_list_test "sg"
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run_dump_test "clzero"
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run_dump_test "invlpgb"
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run_dump_test "tlbsync"
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run_dump_test "snp"
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run_dump_test "disassem"
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run_dump_test "mwaitx-bdver4"
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run_list_test "mwaitx-reg"
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@ -755,6 +760,8 @@ if [gas_64_check] then {
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run_dump_test "movz64"
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run_dump_test "x86-64-relax-1"
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run_dump_test "svme64"
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run_dump_test "snp64"
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run_dump_test "invlpgb64"
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run_dump_test "x86-64-amdfam10"
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run_dump_test "x86-64-vmx"
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run_dump_test "x86-64-vmfunc"
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@ -843,6 +850,7 @@ if [gas_64_check] then {
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run_dump_test "x86-64-arch-1"
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run_dump_test "x86-64-arch-2"
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run_dump_test "x86-64-arch-3"
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run_dump_test "x86-64-arch-4"
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run_dump_test "x86-64-arch-2-lzcnt"
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run_dump_test "x86-64-arch-2-prefetchw"
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run_dump_test "x86-64-arch-2-bdver1"
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@ -851,6 +859,7 @@ if [gas_64_check] then {
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run_dump_test "x86-64-arch-2-bdver4"
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run_dump_test "x86-64-arch-3-znver1"
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run_dump_test "x86-64-arch-3-znver2"
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run_dump_test "x86-64-arch-4-znver3"
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run_dump_test "x86-64-arch-2-btver1"
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run_dump_test "x86-64-arch-2-btver2"
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run_list_test "x86-64-arch-2-1" "-march=generic64 -I${srcdir}/$subdir -al"
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14
gas/testsuite/gas/i386/invlpgb.d
Normal file
14
gas/testsuite/gas/i386/invlpgb.d
Normal file
@ -0,0 +1,14 @@
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#objdump: -dw
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#name: 32-bit INVLPGB insn
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <_start>:
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[ ]*[a-f0-9]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
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[0-9a-f]+ <att32>:
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[ ]*[a-f0-9]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
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[0-9a-f]+ <att16>:
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[ ]*[a-f0-9]+:[ ]+67 0f 01 fe[ ]+addr16 invlpgb[ ]*
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#pass
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15
gas/testsuite/gas/i386/invlpgb.s
Normal file
15
gas/testsuite/gas/i386/invlpgb.s
Normal file
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# Check INVLPGB instructions
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.text
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_start:
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invlpgb
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.ifdef __amd64__
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att64:
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invlpgb %rax, %edx
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.endif
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att32:
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invlpgb %eax, %edx
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.ifndef __amd64__
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att16:
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invlpgb %ax, %edx
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.endif
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16
gas/testsuite/gas/i386/invlpgb64.d
Normal file
16
gas/testsuite/gas/i386/invlpgb64.d
Normal file
@ -0,0 +1,16 @@
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#as: --defsym __amd64__=1
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#objdump: -dw
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#name: 64-bit INVLPGB insn
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#source: invlpgb.s
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.*: +file format .*
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Disassembly of section \.text:
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0+000 <_start>:
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[ ]*[a-f0-9]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
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[0-9a-f]+ <att64>:
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[ ]*[a-f0-9]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
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[0-9a-f]+ <att32>:
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[ ]*[a-f0-9]+:[ ]+67 0f 01 fe[ ]+addr32 invlpgb[ ]*
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#pass
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13
gas/testsuite/gas/i386/snp.d
Normal file
13
gas/testsuite/gas/i386/snp.d
Normal file
@ -0,0 +1,13 @@
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#objdump: -dw
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#name: 32-bit SNP insn
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <att32>:
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[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
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[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
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[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 ff[ ]+addr16 pvalidate[ ]*
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#pass
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23
gas/testsuite/gas/i386/snp.s
Normal file
23
gas/testsuite/gas/i386/snp.s
Normal file
@ -0,0 +1,23 @@
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# Check SNP instructions
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.text
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.ifdef __amd64__
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att64:
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psmash %rax
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psmash
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psmash %eax
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pvalidate %rax
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pvalidate %eax
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rmpupdate %rax
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rmpupdate
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rmpupdate %eax
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rmpadjust %rax
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rmpadjust
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rmpadjust %eax
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.endif
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.ifndef __amd64__
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att32:
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pvalidate
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pvalidate %eax
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pvalidate %ax
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.endif
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23
gas/testsuite/gas/i386/snp64.d
Normal file
23
gas/testsuite/gas/i386/snp64.d
Normal file
@ -0,0 +1,23 @@
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#as: --defsym __amd64__=1
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#objdump: -dw
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#name: 64-bit SNP insn
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#source: snp.s
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.*: +file format .*
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Disassembly of section \.text:
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0+000 <att64>:
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[ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash[ ]*
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[ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash[ ]*
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[ ]*[a-f0-9]+:[ ]+67 f3 0f 01 ff[ ]+addr32 psmash[ ]*
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[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
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[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 ff[ ]+addr32 pvalidate[ ]*
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[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate[ ]*
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[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate[ ]*
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[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 fe[ ]+addr32 rmpupdate[ ]*
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[ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust[ ]*
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[ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust[ ]*
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[ ]*[a-f0-9]+:[ ]+67 f3 0f 01 fe[ ]+addr32 rmpadjust[ ]*
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#pass
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11
gas/testsuite/gas/i386/tlbsync.d
Normal file
11
gas/testsuite/gas/i386/tlbsync.d
Normal file
@ -0,0 +1,11 @@
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#objdump: -dw
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#name: i386 TLBSYNC insn
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <_start>:
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[ ]*[a-f0-9]+: 0f 01 ff tlbsync[ ]*
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#pass
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5
gas/testsuite/gas/i386/tlbsync.s
Normal file
5
gas/testsuite/gas/i386/tlbsync.s
Normal file
@ -0,0 +1,5 @@
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# Check TLBSYNC instructions
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.text
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_start:
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tlbsync
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5
gas/testsuite/gas/i386/x86-64-arch-4-znver3.d
Normal file
5
gas/testsuite/gas/i386/x86-64-arch-4-znver3.d
Normal file
@ -0,0 +1,5 @@
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#source: x86-64-arch-4.s
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#as: -march=znver3
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#objdump: -dw
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#name: x86-64 arch 4 (znver3)
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#dump: x86-64-arch-4.d
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33
gas/testsuite/gas/i386/x86-64-arch-4.d
Normal file
33
gas/testsuite/gas/i386/x86-64-arch-4.d
Normal file
@ -0,0 +1,33 @@
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#objdump: -dw
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#name: x86-64 arch 4
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.*: file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[0-9a-f]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
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[ ]*[0-9a-f]+:[ ]+0f 01 ff[ ]+tlbsync[ ]*
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[ ]*[a-f0-9]+:[ ]*c4 43 35 44 d0 ab[ ]*vpclmulqdq \$0xab,%ymm8,%ymm9,%ymm10
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[ ]*[a-f0-9]+:[ ]*c4 23 35 44 94 f0 24 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x124\(%rax,%r14,8\),%ymm9,%ymm10
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[ ]*[a-f0-9]+:[ ]*c4 63 35 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm9,%ymm10
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[ ]*[a-f0-9]+:[ ]*c4 43 25 44 e2 11[ ]*vpclmulhqhqdq %ymm10,%ymm11,%ymm12
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[ ]*[a-f0-9]+:[ ]*c4 43 1d 44 eb 01[ ]*vpclmulhqlqdq %ymm11,%ymm12,%ymm13
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[ ]*[a-f0-9]+:[ ]*c4 43 15 44 f4 10[ ]*vpclmullqhqdq %ymm12,%ymm13,%ymm14
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[ ]*[a-f0-9]+:[ ]*c4 43 0d 44 fd 00[ ]*vpclmullqlqdq %ymm13,%ymm14,%ymm15
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[ ]*[a-f0-9]+: c4 e2 4d dc d4[ ]+vaesenc %ymm4,%ymm6,%ymm2
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[ ]*[a-f0-9]+: c4 e2 4d dc 39[ ]+vaesenc \(%rcx\),%ymm6,%ymm7
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[ ]*[a-f0-9]+: c4 e2 4d dd d4[ ]+vaesenclast %ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e2 4d dd 39[ ]+vaesenclast \(%rcx\),%ymm6,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e2 4d de d4[ ]+vaesdec %ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e2 4d de 39[ ]+vaesdec \(%rcx\),%ymm6,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e2 4d df d4[ ]+vaesdeclast %ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e2 4d df 39[ ]+vaesdeclast \(%rcx\),%ymm6,%ymm7
|
||||
[ ]*[a-f0-9]+: f3 0f 01 ff[ ]+psmash[ ]*
|
||||
[ ]*[a-f0-9]+: f2 0f 01 ff[ ]+pvalidate[ ]*
|
||||
[ ]*[a-f0-9]+: f2 0f 01 fe[ ]+rmpupdate[ ]*
|
||||
[ ]*[a-f0-9]+: f3 0f 01 fe[ ]+rmpadjust[ ]*
|
||||
[ ]*[a-f0-9]+: 66 0f 38 82 10[ ]+invpcid \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 0f 01 ee[ ]+rdpkru[ ]*
|
||||
[ ]*[a-f0-9]+: 0f 01 ef[ ]+wrpkru[ ]*
|
||||
#pass
|
||||
34
gas/testsuite/gas/i386/x86-64-arch-4.s
Normal file
34
gas/testsuite/gas/i386/x86-64-arch-4.s
Normal file
@ -0,0 +1,34 @@
|
||||
# Test -march=
|
||||
.text
|
||||
#INVLPGB
|
||||
invlpgb
|
||||
#TLBSYNC
|
||||
tlbsync
|
||||
#VPCLMUL 256 datapath
|
||||
vpclmulqdq $0xab, %ymm8, %ymm9, %ymm10
|
||||
vpclmulqdq $123, 0x124(%rax,%r14,8), %ymm9, %ymm10
|
||||
vpclmulqdq $123, 4064(%rdx), %ymm9, %ymm10
|
||||
|
||||
vpclmulhqhqdq %ymm10, %ymm11, %ymm12
|
||||
vpclmulhqlqdq %ymm11, %ymm12, %ymm13
|
||||
vpclmullqhqdq %ymm12, %ymm13, %ymm14
|
||||
vpclmullqlqdq %ymm13, %ymm14, %ymm15
|
||||
#VAES
|
||||
vaesenc %ymm4,%ymm6,%ymm2
|
||||
vaesenc (%rcx),%ymm6,%ymm7
|
||||
vaesenclast %ymm4,%ymm6,%ymm2
|
||||
vaesenclast (%rcx),%ymm6,%ymm7
|
||||
vaesdec %ymm4,%ymm6,%ymm2
|
||||
vaesdec (%rcx),%ymm6,%ymm7
|
||||
vaesdeclast %ymm4,%ymm6,%ymm2
|
||||
vaesdeclast (%rcx),%ymm6,%ymm7
|
||||
#SNP - Secure Nested Paging support
|
||||
psmash
|
||||
pvalidate
|
||||
rmpupdate
|
||||
rmpadjust
|
||||
#INVPCID
|
||||
invpcid (%rax), %rdx
|
||||
#OSPKE
|
||||
rdpkru
|
||||
wrpkru
|
||||
@ -1,3 +1,16 @@
|
||||
2020-10-20 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
|
||||
|
||||
* i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
|
||||
* i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
|
||||
CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
|
||||
Add CPU_ZNVER3_FLAGS.
|
||||
(cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
|
||||
* i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
|
||||
* i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
|
||||
rmpupdate, rmpadjust.
|
||||
* i386-init.h: Re-generated.
|
||||
* i386-tbl.h: Re-generated.
|
||||
|
||||
2020-10-16 Lili Cui <lili.cui@intel.com>
|
||||
|
||||
* i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
|
||||
|
||||
@ -969,6 +969,8 @@ enum
|
||||
PREFIX_0F01_REG_5_MOD_3_RM_6,
|
||||
PREFIX_0F01_REG_5_MOD_3_RM_7,
|
||||
PREFIX_0F01_REG_7_MOD_3_RM_2,
|
||||
PREFIX_0F01_REG_7_MOD_3_RM_6,
|
||||
PREFIX_0F01_REG_7_MOD_3_RM_7,
|
||||
PREFIX_0F09,
|
||||
PREFIX_0F10,
|
||||
PREFIX_0F11,
|
||||
@ -1202,6 +1204,9 @@ enum
|
||||
X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
|
||||
X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
|
||||
X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
|
||||
X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
|
||||
X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
|
||||
X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
|
||||
X86_64_0FC7_REG_6_MOD_3_PREFIX_1
|
||||
};
|
||||
|
||||
@ -3210,6 +3215,22 @@ static const struct dis386 prefix_table[][4] = {
|
||||
{ "mcommit", { Skip_MODRM }, 0 },
|
||||
},
|
||||
|
||||
/* PREFIX_0F01_REG_7_MOD_3_RM_6 */
|
||||
{
|
||||
{ "invlpgb", { Skip_MODRM }, 0 },
|
||||
{ X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
|
||||
{ Bad_Opcode },
|
||||
{ X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
|
||||
},
|
||||
|
||||
/* PREFIX_0F01_REG_7_MOD_3_RM_7 */
|
||||
{
|
||||
{ "tlbsync", { Skip_MODRM }, 0 },
|
||||
{ X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
|
||||
{ Bad_Opcode },
|
||||
{ "pvalidate", { Skip_MODRM }, 0 },
|
||||
},
|
||||
|
||||
/* PREFIX_0F09 */
|
||||
{
|
||||
{ "wbinvd", { XX }, 0 },
|
||||
@ -4384,6 +4405,24 @@ static const struct dis386 x86_64_table[][2] = {
|
||||
{ "stui", { Skip_MODRM }, 0 },
|
||||
},
|
||||
|
||||
/* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "rmpadjust", { Skip_MODRM }, 0 },
|
||||
},
|
||||
|
||||
/* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "rmpupdate", { Skip_MODRM }, 0 },
|
||||
},
|
||||
|
||||
/* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "psmash", { Skip_MODRM }, 0 },
|
||||
},
|
||||
|
||||
/* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
@ -8990,6 +9029,8 @@ static const struct dis386 rm_table[][8] = {
|
||||
{ "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
|
||||
{ "clzero", { Skip_MODRM }, 0 },
|
||||
{ "rdpru", { Skip_MODRM }, 0 },
|
||||
{ PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
|
||||
{ PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
|
||||
},
|
||||
{
|
||||
/* RM_0F1E_P_1_MOD_3_REG_7 */
|
||||
|
||||
@ -103,6 +103,8 @@ static initializer cpu_flag_init[] =
|
||||
"CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_AVX2_FLAGS|CpuSSE4A|CpuLZCNT|CpuPOPCNT|CpuSVME|CpuAES|CpuPCLMUL|CpuPRFCHW|CpuFMA|CpuBMI|CpuF16C|CpuXsaveopt|CpuFSGSBase|CpuMovbe|CpuBMI2|CpuRdRnd|CpuADX|CpuRdSeed|CpuSMAP|CpuSHA|CpuXSAVEC|CpuXSAVES|CpuClflushOpt|CpuCLZERO|CpuMWAITX" },
|
||||
{ "CPU_ZNVER2_FLAGS",
|
||||
"CPU_ZNVER1_FLAGS|CpuCLWB|CpuRDPID|CpuRDPRU|CpuMCOMMIT|CpuWBNOINVD" },
|
||||
{ "CPU_ZNVER3_FLAGS",
|
||||
"CPU_ZNVER2_FLAGS|CpuINVLPGB|CpuTLBSYNC|CpuVAES|CpuVPCLMULQDQ|CpuINVPCID|CpuSNP|CpuOSPKE" },
|
||||
{ "CPU_BTVER1_FLAGS",
|
||||
"CPU_GENERIC64_FLAGS|CpuFISTTP|CpuCX16|CpuRdtscp|CPU_SSSE3_FLAGS|CpuSSE4A|CpuLZCNT|CpuPOPCNT|CpuPRFCHW|CpuCX16|CpuClflush|CpuFISTTP|CpuSVME" },
|
||||
{ "CPU_BTVER2_FLAGS",
|
||||
@ -333,6 +335,12 @@ static initializer cpu_flag_init[] =
|
||||
"CpuWideKL" },
|
||||
{ "CPU_HRESET_FLAGS",
|
||||
"CpuHRESET"},
|
||||
{ "CPU_INVLPGB_FLAGS",
|
||||
"CpuINVLPGB" },
|
||||
{ "CPU_TLBSYNC_FLAGS",
|
||||
"CpuTLBSYNC" },
|
||||
{ "CPU_SNP_FLAGS",
|
||||
"CpuSNP" },
|
||||
{ "CPU_ANY_X87_FLAGS",
|
||||
"CPU_ANY_287_FLAGS|Cpu8087" },
|
||||
{ "CPU_ANY_287_FLAGS",
|
||||
@ -666,6 +674,9 @@ static bitfield cpu_flags[] =
|
||||
BITFIELD (CpuKL),
|
||||
BITFIELD (CpuWideKL),
|
||||
BITFIELD (CpuHRESET),
|
||||
BITFIELD (CpuINVLPGB),
|
||||
BITFIELD (CpuTLBSYNC),
|
||||
BITFIELD (CpuSNP),
|
||||
#ifdef CpuUnused
|
||||
BITFIELD (CpuUnused),
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -271,6 +271,12 @@ enum
|
||||
CpuWideKL,
|
||||
/* HRESET instruction required */
|
||||
CpuHRESET,
|
||||
/* INVLPGB instructions required */
|
||||
CpuINVLPGB,
|
||||
/* TLBSYNC instructions required */
|
||||
CpuTLBSYNC,
|
||||
/* SNP instructions required */
|
||||
CpuSNP,
|
||||
/* 64bit support required */
|
||||
Cpu64,
|
||||
/* Not supported in the 64bit mode */
|
||||
@ -414,6 +420,9 @@ typedef union i386_cpu_flags
|
||||
unsigned int cpukl:1;
|
||||
unsigned int cpuwidekl:1;
|
||||
unsigned int cpuhreset:1;
|
||||
unsigned int cpuinvlpgb:1;
|
||||
unsigned int cputlbsync:1;
|
||||
unsigned int cpusnp:1;
|
||||
unsigned int cpu64:1;
|
||||
unsigned int cpuno64:1;
|
||||
#ifdef CpuUnused
|
||||
|
||||
@ -3960,6 +3960,19 @@ vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|OpcodePrefix=
|
||||
|
||||
// AVX512 + VPCLMULQDQ instructions end
|
||||
|
||||
// INVLPGB instructions
|
||||
|
||||
invlpgb, 0, 0xf01fe, None, 3, CpuINVLPGB, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
invlpgb, 2, 0xf01fe, None, 3, CpuINVLPGB, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegD|Dword }
|
||||
|
||||
// INVLPGB instructions end
|
||||
|
||||
// TLBSYNC instructions
|
||||
|
||||
tlbsync, 0, 0xf01ff, None, 3, CpuTLBSYNC, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
|
||||
// TLBSYNC instructions end
|
||||
|
||||
// CLZERO instructions
|
||||
|
||||
clzero, 0, 0xf01fc, None, 3, CpuCLZERO, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
@ -4092,6 +4105,19 @@ mcommit, 0, 0x0f01fa, None, 3, CpuMCOMMIT, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|N
|
||||
|
||||
// MCOMMIT instruction end
|
||||
|
||||
// SNP instructions
|
||||
|
||||
psmash, 0, 0xf01ff, None, 3, CpuSNP|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
psmash, 1, 0xf01ff, None, 3, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword }
|
||||
pvalidate, 0, 0xf01ff, None, 3, CpuSNP, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
pvalidate, 1, 0xf01ff, None, 3, CpuSNP, AddrPrefixOpReg|Prefix_0XF2, { Acc|Word|Dword|Qword }
|
||||
rmpupdate, 0, 0xf01fe, None, 3, CpuSNP|Cpu64, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
rmpupdate, 1, 0xf01fe, None, 3, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF2, { Acc|Dword|Qword }
|
||||
rmpadjust, 0, 0xf01fe, None, 3, CpuSNP|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
rmpadjust, 1, 0xf01fe, None, 3, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword }
|
||||
|
||||
// SNP instructions end
|
||||
|
||||
// RDPRU instruction
|
||||
|
||||
rdpru, 0, 0x0f01fd, None, 3, CpuRDPRU, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
|
||||
8185
opcodes/i386-tbl.h
8185
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user