Implement missing powerpc mtspr and mfspr extended insns
* ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended instructions.
This commit is contained in:
Alan Modra
parent
8b2742a156
commit
3eb651743e
@ -1,3 +1,8 @@
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2020-08-10 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
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instructions.
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2020-08-10 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
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@ -6741,11 +6741,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
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{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
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{"mfudscr", XSPR(31,339, 3), XSPR_MASK, POWER9, 0, {RS}},
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{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
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{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
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{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
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{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
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{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
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{"mfuamr", XSPR(31,339, 13), XSPR_MASK, POWER9, 0, {RS}},
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{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
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{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
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{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
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@ -6756,9 +6758,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
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{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
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{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
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{"mfamr", XSPR(31,339, 29), XSPR_MASK, POWER7, 0, {RS}},
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{"mfpidr", XSPR(31,339, 48), XSPR_MASK, POWER10, 0, {RS}},
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{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfiamr", XSPR(31,339, 61), XSPR_MASK, POWER10, 0, {RS}},
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{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
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@ -6772,16 +6777,28 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
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{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
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{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
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{"mffscr", XSPR(31,339,153), XSPR_MASK, POWER10, 0, {RS}},
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{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
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{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
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{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
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{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
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{"mfuamor", XSPR(31,339,157), XSPR_MASK, POWER7, 0, {RS}},
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{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
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{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
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{"mfpspb", XSPR(31,339,159), XSPR_MASK, POWER10, 0, {RS}},
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{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
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{"mfdpdes", XSPR(31,339,176), XSPR_MASK, POWER10, 0, {RS}},
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{"mfdawr0", XSPR(31,339,180), XSPR_MASK, POWER10, 0, {RS}},
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{"mfdawr1", XSPR(31,339,181), XSPR_MASK, POWER10, 0, {RS}},
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{"mfrpr", XSPR(31,339,186), XSPR_MASK, POWER10, 0, {RS}},
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{"mfciabr", XSPR(31,339,187), XSPR_MASK, POWER10, 0, {RS}},
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{"mfdawrx0", XSPR(31,339,188), XSPR_MASK, POWER10, 0, {RS}},
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{"mfdawrx1", XSPR(31,339,189), XSPR_MASK, POWER10, 0, {RS}},
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{"mfhfscr", XSPR(31,339,190), XSPR_MASK, POWER10, 0, {RS}},
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{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
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{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
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{"mfusprg3", XSPR(31,339,259), XSPR_MASK, POWER10, 0, {RT}},
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{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
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{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
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{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
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@ -6797,20 +6814,37 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
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{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
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{"mfhsprg0", XSPR(31,339,304), XSPR_MASK, POWER10, 0, {RS}},
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{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfhsprg1", XSPR(31,339,305), XSPR_MASK, POWER10, 0, {RS}},
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{"mfhdisr", XSPR(31,339,306), XSPR_MASK, POWER10, 0, {RS}},
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{"mfhdar", XSPR(31,339,307), XSPR_MASK, POWER10, 0, {RS}},
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{"mfspurr", XSPR(31,339,308), XSPR_MASK, POWER10, 0, {RS}},
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{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfpurr", XSPR(31,339,309), XSPR_MASK, POWER10, 0, {RS}},
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{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfhdec", XSPR(31,339,310), XSPR_MASK, POWER10, 0, {RS}},
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{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfhrmor", XSPR(31,339,313), XSPR_MASK, POWER10, 0, {RS}},
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{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfhsrr0", XSPR(31,339,314), XSPR_MASK, POWER10, 0, {RS}},
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{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfhsrr1", XSPR(31,339,315), XSPR_MASK, POWER10, 0, {RS}},
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{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
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{"mflpcr", XSPR(31,339,318), XSPR_MASK, POWER10, 0, {RS}},
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{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
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{"mflpidr", XSPR(31,339,319), XSPR_MASK, POWER10, 0, {RS}},
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{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfhmer", XSPR(31,339,336), XSPR_MASK, POWER7, 0, {RS}},
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{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfhmeer", XSPR(31,339,337), XSPR_MASK, POWER7, 0, {RS}},
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{"mfpcr", XSPR(31,339,338), XSPR_MASK, POWER10, 0, {RS}},
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{"mfheir", XSPR(31,339,339), XSPR_MASK, POWER10, 0, {RS}},
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{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfamor", XSPR(31,339,349), XSPR_MASK, POWER7, 0, {RS}},
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{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
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@ -6827,6 +6861,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
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{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
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{"mftir", XSPR(31,339,446), XSPR_MASK, POWER10, 0, {RS}},
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{"mfptcr", XSPR(31,339,464), XSPR_MASK, POWER10, 0, {RS}},
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{"mfuspgr0", XSPR(31,339,496), XSPR_MASK, POWER10, 0, {RS}},
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{"mfuspgr1", XSPR(31,339,497), XSPR_MASK, POWER10, 0, {RS}},
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{"mfurmor", XSPR(31,339,505), XSPR_MASK, POWER10, 0, {RS}},
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{"mfusrr0", XSPR(31,339,506), XSPR_MASK, POWER10, 0, {RS}},
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{"mfusrr1", XSPR(31,339,507), XSPR_MASK, POWER10, 0, {RS}},
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{"mfsmfctrl", XSPR(31,339,511), XSPR_MASK, POWER10, 0, {RS}},
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{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
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{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
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{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
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@ -6851,18 +6893,36 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
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{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
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{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
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{"mfusier2", XSPR(31,339,736), XSPR_MASK, POWER10, 0, {RT}},
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{"mfsier2", XSPR(31,339,736), XSPR_MASK, POWER10, 0, {RT}},
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{"mfusier3", XSPR(31,339,737), XSPR_MASK, POWER10, 0, {RT}},
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{"mfsier3", XSPR(31,339,737), XSPR_MASK, POWER10, 0, {RT}},
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{"mfummcr3", XSPR(31,339,738), XSPR_MASK, POWER10, 0, {RT}},
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{"mfmmcr3", XSPR(31,339,738), XSPR_MASK, POWER10, 0, {RT}},
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{"mfusier", XSPR(31,339,768), XSPR_MASK, POWER10, 0, {RT}},
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{"mfsier", XSPR(31,339,768), XSPR_MASK, POWER10, 0, {RT}},
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{"mfummcra", XSPR(31,339,770), XSPR_MASK, POWER9, 0, {RS}},
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{"mfmmcra", XSPR(31,339,770), XSPR_MASK, POWER7, 0, {RS}},
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{"mfupmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}},
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{"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}},
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{"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER7, 0, {RT}},
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{"mfupmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}},
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{"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}},
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{"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER7, 0, {RT}},
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{"mfupmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}},
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{"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}},
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{"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER7, 0, {RT}},
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{"mfupmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}},
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{"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}},
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{"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER7, 0, {RT}},
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{"mfupmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}},
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{"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}},
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{"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER7, 0, {RT}},
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{"mfupmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}},
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{"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}},
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{"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER7, 0, {RT}},
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{"mfummcr0", XSPR(31,339,779), XSPR_MASK, POWER9, 0, {RS}},
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{"mfmmcr0", XSPR(31,339,779), XSPR_MASK, POWER7, 0, {RS}},
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{"mfusiar", XSPR(31,339,780), XSPR_MASK, POWER9, 0, {RS}},
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{"mfsiar", XSPR(31,339,780), XSPR_MASK, POWER9, 0, {RS}},
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{"mfusdar", XSPR(31,339,781), XSPR_MASK, POWER9, 0, {RS}},
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{"mfsdar", XSPR(31,339,781), XSPR_MASK, POWER9, 0, {RS}},
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{"mfummcr1", XSPR(31,339,782), XSPR_MASK, POWER9, 0, {RS}},
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{"mfmmcr1", XSPR(31,339,782), XSPR_MASK, POWER7, 0, {RS}},
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{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
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{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
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{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
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@ -6876,12 +6936,25 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
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{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
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{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
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{"mfbescrs", XSPR(31,339,800), XSPR_MASK, POWER9, 0, {RS}},
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{"mfbescrsu", XSPR(31,339,801), XSPR_MASK, POWER9, 0, {RS}},
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{"mfbescrr", XSPR(31,339,802), XSPR_MASK, POWER9, 0, {RS}},
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{"mfbescrru", XSPR(31,339,803), XSPR_MASK, POWER9, 0, {RS}},
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{"mfebbhr", XSPR(31,339,804), XSPR_MASK, POWER9, 0, {RS}},
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{"mfebbrr", XSPR(31,339,805), XSPR_MASK, POWER9, 0, {RS}},
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{"mfbescr", XSPR(31,339,806), XSPR_MASK, POWER9, 0, {RS}},
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{"mftar", XSPR(31,339,815), XSPR_MASK, POWER9, 0, {RS}},
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{"mfasdr", XSPR(31,339,816), XSPR_MASK, POWER10, 0, {RS}},
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{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
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{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
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{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
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{"mfpsscr", XSPR(31,339,823), XSPR_MASK, POWER10, 0, {RS}},
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{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
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{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
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{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
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{"mfic", XSPR(31,339,848), XSPR_MASK, POWER8, 0, {RS}},
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{"mfvtb", XSPR(31,339,849), XSPR_MASK, POWER8, 0, {RS}},
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{"mfhpsscr", XSPR(31,339,855), XSPR_MASK, POWER10, 0, {RS}},
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{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
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{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
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{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
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@ -7128,8 +7201,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
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{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
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{"mtudscr", XSPR(31,467, 3), XSPR_MASK, POWER9, 0, {RS}},
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{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
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{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
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{"mtuamr", XSPR(31,467, 13), XSPR_MASK, POWER9, 0, {RS}},
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{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
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{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
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{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
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@ -7142,13 +7217,20 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
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{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
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{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
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{"mtamr", XSPR(31,467, 29), XSPR_MASK, POWER7, 0, {RS}},
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{"mtpidr", XSPR(31,467, 48), XSPR_MASK, POWER10, 0, {RS}},
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{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
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{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
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{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
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{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
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{"mtiamr", XSPR(31,467, 61), XSPR_MASK, POWER10, 0, {RS}},
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{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
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{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mttfhar", XSPR(31,467,128), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mttfiar", XSPR(31,467,129), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mttexasr", XSPR(31,467,130), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mttexasru", XSPR(31,467,131), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
|
||||
{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
|
||||
{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
|
||||
@ -7159,13 +7241,24 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
|
||||
{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
|
||||
{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
|
||||
{"mtfscr", XSPR(31,467,153), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
|
||||
{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
|
||||
{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
|
||||
{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
|
||||
{"mtuamor", XSPR(31,467,157), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
|
||||
{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
|
||||
{"mtpspb", XSPR(31,467,159), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
|
||||
{"mtdpdes", XSPR(31,467,176), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtdawr0", XSPR(31,467,180), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtdawr1", XSPR(31,467,181), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtrpr", XSPR(31,467,186), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtciabr", XSPR(31,467,187), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtdawrx0", XSPR(31,467,188), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtdawrx1", XSPR(31,467,189), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mthfscr", XSPR(31,467,190), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
|
||||
{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
|
||||
@ -7181,20 +7274,38 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
|
||||
{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
|
||||
{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
|
||||
{"mttbu40", XSPR(31,467,286), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mthsprg0", XSPR(31,467,304), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mthsprg1", XSPR(31,467,305), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mthdisr", XSPR(31,467,306), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mthdar", XSPR(31,467,307), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtspurr", XSPR(31,467,308), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtpurr", XSPR(31,467,309), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mthdec", XSPR(31,467,310), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mthrmor", XSPR(31,467,313), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mthsrr0", XSPR(31,467,314), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mthsrr1", XSPR(31,467,315), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtlpcr", XSPR(31,467,318), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtlpidr", XSPR(31,467,319), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mthmer", XSPR(31,467,336), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mthmeer", XSPR(31,467,337), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mtpcr", XSPR(31,467,338), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtheir", XSPR(31,467,339), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtamor", XSPR(31,467,349), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
@ -7211,6 +7322,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
|
||||
{"mtptcr", XSPR(31,467,464), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtuspgr0", XSPR(31,467,496), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtuspgr1", XSPR(31,467,497), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mturmor", XSPR(31,467,505), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtusrr0", XSPR(31,467,506), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtusrr1", XSPR(31,467,507), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtsmfctrl", XSPR(31,467,511), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
|
||||
{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
|
||||
{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
|
||||
@ -7225,12 +7343,44 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
|
||||
{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
|
||||
{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
|
||||
{"mtsier2", XSPR(31,467,752), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtsier3", XSPR(31,467,753), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtmmcr3", XSPR(31,467,754), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtummcr2", XSPR(31,467,769), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtmmcr2", XSPR(31,467,769), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtummcra", XSPR(31,467,770), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtupmc1", XSPR(31,467,771), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtupmc2", XSPR(31,467,772), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtupmc3", XSPR(31,467,773), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtupmc4", XSPR(31,467,774), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtupmc5", XSPR(31,467,775), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtupmc6", XSPR(31,467,776), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtummcr0", XSPR(31,467,779), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtsier", XSPR(31,467,784), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtmmcra", XSPR(31,467,786), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mtpmc1", XSPR(31,467,787), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mtpmc2", XSPR(31,467,788), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mtpmc3", XSPR(31,467,789), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mtpmc4", XSPR(31,467,790), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mtpmc5", XSPR(31,467,791), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mtpmc6", XSPR(31,467,792), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mtmmcr0", XSPR(31,467,795), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mtsiar", XSPR(31,467,796), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtsdar", XSPR(31,467,797), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtmmcr1", XSPR(31,467,798), XSPR_MASK, POWER7, 0, {RS}},
|
||||
{"mtbescrs", XSPR(31,467,800), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtbescrsu", XSPR(31,467,801), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtbescrr", XSPR(31,467,802), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtbescrru", XSPR(31,467,803), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtebbhr", XSPR(31,467,804), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtebbrr", XSPR(31,467,805), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtbescr", XSPR(31,467,806), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mttar", XSPR(31,467,815), XSPR_MASK, POWER9, 0, {RS}},
|
||||
{"mtasdr", XSPR(31,467,816), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtpsscr", XSPR(31,467,823), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtic", XSPR(31,467,848), XSPR_MASK, POWER8, 0, {RS}},
|
||||
{"mtvtb", XSPR(31,467,849), XSPR_MASK, POWER8, 0, {RS}},
|
||||
{"mthpsscr", XSPR(31,467,855), XSPR_MASK, POWER10, 0, {RS}},
|
||||
{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
|
||||
{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
|
||||
{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user